From nobody Mon Jun 8 08:36:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49E7D33F5B4; Sun, 31 May 2026 09:10:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780218645; cv=none; b=k9Wqph0+6hfiQMYybbndOWF90yYs7pAfDSIUSslF4KL8umgp/CVyWlGrNNLWWY/jyv/uO81vp5opqTIJcSVxtpiEzio4lKc5Gj5fQJiOZp9U6f3P/XDe1unnf2pBxbl8Dk+ScJ+JXJh1fzoRh2PLExVPLl1qOZnF7fajWxt+T2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780218645; c=relaxed/simple; bh=fl0iUdi5y/WRY0Tl1PLawS93frhYjgaC429L2//ta2o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sm4bq4SGe6Tnr/T5LUM/TQMQY5VawwEYH78jXJgkNnlSvJGfvE67hl9HsYT20mAj+gBjglE6KtA1LnnnsqDK7At60Wus1tWYSqAPyNWmjmbyciaLbLjMVRqeOb2orQ5JC+3p4mGhBAKZ0/uDEb9Ha92FwYOpUSMJ2lVvlbx+zaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vea4tJa6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vea4tJa6" Received: by smtp.kernel.org (Postfix) with ESMTPS id F2330C2BCC4; Sun, 31 May 2026 09:10:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780218645; bh=fl0iUdi5y/WRY0Tl1PLawS93frhYjgaC429L2//ta2o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Vea4tJa6nDmbCYqrfAXD+hOgB1RtiooRwmw05Az9Xgx/6ESpQ0ym5iKQ8/EpIUh8r 8dsnqjyk/q6V5YvqKrbvnni166jSXi5mL2fZ5A8iIysD4/0MVdJ7Yvrzo+69pPUCKA iIqdm1TGDbnvsjTWo8//nUlZ8UINgUvOJ7+B++rKzVhk5uHVpV+D1vl/mnkOvfILQZ VzIoRdftWpIcVNNHRrZzIBNVIwEANABBlDpsORaTABq16piTcJyIAKQ2iGe5NJtMcg ymv2zfnO8nD8vN30SP0SP5m98BCe79/yFQPlPBBsgtepMNF17CJfOXZEajIIUndG6a w5dvDX5mxG/4Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBC6DCD5BD1; Sun, 31 May 2026 09:10:44 +0000 (UTC) From: Yassine Oudjana via B4 Relay Date: Sun, 31 May 2026 11:10:42 +0200 Subject: [PATCH v2 1/4] dt-bindings: mediatek: pwrap: Add MT6735 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-mt6735-pwrap-mt6328-pmic-v2-1-dac37bf92894@protonmail.com> References: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com> In-Reply-To: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Flora Fu , Alexandre Mergnat , Liam Girdwood , Mark Brown , Dmitry Torokhov Cc: Yassine Oudjana , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-input@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780218643; l=978; i=y.oudjana@protonmail.com; s=20260531; h=from:subject:message-id; bh=m78Bi8O6FvM9feF/O3ItPJ/iTAy8mD+DaEC7H/m00nc=; b=GHskc8UWok3K7CWbObkaLMAe27510F7dQRsRfHaOcFA8ar+qNdXa+Z49m9YRPxOHT2fKv3KCA aeM8he7n6ZdA91JPIj0D4ccd0iemNy8Zl39+H42lJVXnk/8NH/Xysnw X-Developer-Key: i=y.oudjana@protonmail.com; a=ed25519; pk=sr7uwnyVqGKAIhvwnIwormkDM3d2VNc3VOTEU1GmsEM= X-Endpoint-Received: by B4 Relay for y.oudjana@protonmail.com/20260531 with auth_id=802 X-Original-From: Yassine Oudjana Reply-To: y.oudjana@protonmail.com From: Yassine Oudjana Add a compatible string for MT6735 PMIC wrapper. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.= yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index e7c4a3984c60..3a5fd46ce282 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -31,6 +31,7 @@ properties: - items: - enum: - mediatek,mt2701-pwrap + - mediatek,mt6735-pwrap - mediatek,mt6765-pwrap - mediatek,mt6779-pwrap - mediatek,mt6795-pwrap --=20 2.54.0 From nobody Mon Jun 8 08:36:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49D5C243951; Sun, 31 May 2026 09:10:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780218645; cv=none; b=hJf44GwoJYV9zIAOosZZTgD3aLinGOFyj3tCbZ21KdLjf3QhLxcKwsrp1lp/0kThNmDYJ78xh0s5PJBluI8y/RrEQ3yFq+NiWTnkw+ESwSv547c+yINX7zCoyzjBH2p0u4KtQoWA+DJRzcVnJhv+ScrFZKB+tyFHph+XpwDW0R4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780218645; c=relaxed/simple; bh=2rLn7+BL0CSKSPRXVYOwPg6tEAx5CUi5V4H8JQk/s9A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oZihnFn7fNphbvqU679mvGv4NnZdZA76O1cUqdlIXxj1o+GcJU4jHn4rkgrKZNdAOoWiTdVDqLUCWahBYea3RJYHLMQ5JKSOEkbFuzUrLtXSN3rkIl+4iJx7HJeGIF62E+qe6vxLsLNUwtbhii1IYsStkGdMvZZJPhOZaI2JxVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bnL+Hwuk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bnL+Hwuk" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0D552C2BCF4; Sun, 31 May 2026 09:10:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780218645; bh=2rLn7+BL0CSKSPRXVYOwPg6tEAx5CUi5V4H8JQk/s9A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bnL+HwukVlOjF5w77/U7myNt/USmXY6NRrOaZHkxRDb9M/ecMUvKzbtJIw0bi6vgY XkYoMHkL6NUvCoi9A98i1eoaeUZOuanUI52OF16fsJ3D5HusP6Az7jbq0S4O0gC7kZ 13279qoa0KOS1EJPrJ5ciBbMKUMHA+febP8DCzPqidMwk7ObzB0auW1YvHbmnBEHz4 A22kyMGI3OXmcE+Vmqtq/NtiMGu4fU5RSkVShpZTP44uCUQ41eoKd11BLvUVx2foOv tEJvx3k/u8XGHgstU8SXiQ8dHV6+Zud8cPXjuQIfcC4Q+UIWDjFOY1N7Q1xRQXyq7D 6jO+aNmdVB34A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07340CD6E57; Sun, 31 May 2026 09:10:45 +0000 (UTC) From: Yassine Oudjana via B4 Relay Date: Sun, 31 May 2026 11:10:43 +0200 Subject: [PATCH v2 2/4] soc: mediatek: pwrap: Add support for MT6735 and MT6328 SoC/PMIC pair Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-mt6735-pwrap-mt6328-pmic-v2-2-dac37bf92894@protonmail.com> References: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com> In-Reply-To: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Flora Fu , Alexandre Mergnat , Liam Girdwood , Mark Brown , Dmitry Torokhov Cc: Yassine Oudjana , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-input@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780218643; l=9618; i=y.oudjana@protonmail.com; s=20260531; h=from:subject:message-id; bh=4sX0Mc13Y67E7+CkHSrLBQ5VssU6E+LoNwfXa6SDJOY=; b=uZ2KaiWCsnQzgGRnS2AGox7rSF2hzKvF5lZ6gXm5v3a+j29oP4H4cvHKueLEKep/3BZEMeV2J uV5eMgqx09iBo8Nf1Bz3VSAjqK5TqwzIf6vtFzDbWkYbavg8croRITD X-Developer-Key: i=y.oudjana@protonmail.com; a=ed25519; pk=sr7uwnyVqGKAIhvwnIwormkDM3d2VNc3VOTEU1GmsEM= X-Endpoint-Received: by B4 Relay for y.oudjana@protonmail.com/20260531 with auth_id=802 X-Original-From: Yassine Oudjana Reply-To: y.oudjana@protonmail.com From: Yassine Oudjana Add register definitions and configuration for the MT6735 SoC and the MT6328 PMIC which are commonly paired and communicate through the PMIC wrapper. Note that the PMIC wrapper on MT6735M has a slightly different register map and is therefore NOT compatible with MT6735. Signed-off-by: Yassine Oudjana --- drivers/soc/mediatek/mtk-pmic-wrap.c | 177 +++++++++++++++++++++++++++++++= +++- 1 file changed, 174 insertions(+), 3 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index 0bcd85826375..0f14dca5609d 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -3,6 +3,7 @@ * Copyright (c) 2014 MediaTek Inc. * Author: Flora Fu, MediaTek */ + #include #include #include @@ -100,7 +101,7 @@ enum dew_regs { PWRAP_DEW_CIPHER_MODE, PWRAP_DEW_CIPHER_SWRST, =20 - /* MT6323 only regs */ + /* MT6323 and MT6328 only regs */ PWRAP_DEW_CIPHER_EN, PWRAP_DEW_RDDMY_NO, =20 @@ -121,8 +122,10 @@ enum dew_regs { PWRAP_RG_SPI_CON13, PWRAP_SPISLV_KEY, =20 - /* MT6359 only regs */ + /* MT6359 and MT6328 only regs */ PWRAP_DEW_CRC_SWRST, + + /* MT6359 only regs */ PWRAP_DEW_RG_EN_RECORD, PWRAP_DEW_RECORD_CMD0, PWRAP_DEW_RECORD_CMD1, @@ -171,6 +174,23 @@ static const u32 mt6323_regs[] =3D { [PWRAP_DEW_RDDMY_NO] =3D 0x01a4, }; =20 +static const u32 mt6328_regs[] =3D { + [PWRAP_DEW_DIO_EN] =3D 0x02d4, + [PWRAP_DEW_READ_TEST] =3D 0x02d6, + [PWRAP_DEW_WRITE_TEST] =3D 0x02d8, + [PWRAP_DEW_CRC_SWRST] =3D 0x02da, + [PWRAP_DEW_CRC_EN] =3D 0x02dc, + [PWRAP_DEW_CRC_VAL] =3D 0x02de, + [PWRAP_DEW_MON_GRP_SEL] =3D 0x02e0, + [PWRAP_DEW_CIPHER_KEY_SEL] =3D 0x02e2, + [PWRAP_DEW_CIPHER_IV_SEL] =3D 0x02e4, + [PWRAP_DEW_CIPHER_EN] =3D 0x02e6, + [PWRAP_DEW_CIPHER_RDY] =3D 0x02e8, + [PWRAP_DEW_CIPHER_MODE] =3D 0x02ea, + [PWRAP_DEW_CIPHER_SWRST] =3D 0x02ec, + [PWRAP_DEW_RDDMY_NO] =3D 0x02ee, +}; + static const u32 mt6331_regs[] =3D { [PWRAP_DEW_DIO_EN] =3D 0x018c, [PWRAP_DEW_READ_TEST] =3D 0x018e, @@ -394,7 +414,7 @@ enum pwrap_regs { PWRAP_ADC_RDATA_ADDR1, PWRAP_ADC_RDATA_ADDR2, =20 - /* MT7622 only regs */ + /* MT7622 and MT6735 only regs */ PWRAP_STA, PWRAP_CLR, PWRAP_DVFS_ADR8, @@ -417,6 +437,8 @@ enum pwrap_regs { PWRAP_ADC_RDATA_ADDR, PWRAP_GPS_STA, PWRAP_SW_RST, + + /* MT7622 only regs */ PWRAP_DVFS_STEP_CTRL0, PWRAP_DVFS_STEP_CTRL1, PWRAP_DVFS_STEP_CTRL2, @@ -481,6 +503,13 @@ enum pwrap_regs { /* MT8516 only regs */ PWRAP_OP_TYPE, PWRAP_MSB_FIRST, + + /* MT6735 only regs */ + PWRAP_WACS3_EN, + PWRAP_INIT_DONE3, + PWRAP_WACS3_CMD, + PWRAP_WACS3_RDATA, + PWRAP_WACS3_VLDCLR, }; =20 static const int mt2701_regs[] =3D { @@ -569,6 +598,119 @@ static const int mt2701_regs[] =3D { [PWRAP_ADC_RDATA_ADDR2] =3D 0x154, }; =20 +static const int mt6735_regs[] =3D { + [PWRAP_MUX_SEL] =3D 0x0, + [PWRAP_WRAP_EN] =3D 0x4, + [PWRAP_DIO_EN] =3D 0x8, + [PWRAP_SIDLY] =3D 0xc, + [PWRAP_RDDMY] =3D 0x10, + [PWRAP_SI_CK_CON] =3D 0x14, + [PWRAP_CSHEXT_WRITE] =3D 0x18, + [PWRAP_CSHEXT_READ] =3D 0x1c, + [PWRAP_CSLEXT_START] =3D 0x20, + [PWRAP_CSLEXT_END] =3D 0x24, + [PWRAP_STAUPD_PRD] =3D 0x28, + [PWRAP_STAUPD_GRPEN] =3D 0x2c, + [PWRAP_EINT_STA0_ADR] =3D 0x30, + [PWRAP_EINT_STA1_ADR] =3D 0x34, + [PWRAP_STA] =3D 0x38, + [PWRAP_CLR] =3D 0x3c, + [PWRAP_STAUPD_MAN_TRIG] =3D 0x40, + [PWRAP_STAUPD_STA] =3D 0x44, + [PWRAP_WRAP_STA] =3D 0x48, + [PWRAP_HARB_INIT] =3D 0x4c, + [PWRAP_HARB_HPRIO] =3D 0x50, + [PWRAP_HIPRIO_ARB_EN] =3D 0x54, + [PWRAP_HARB_STA0] =3D 0x58, + [PWRAP_HARB_STA1] =3D 0x5c, + [PWRAP_MAN_EN] =3D 0x60, + [PWRAP_MAN_CMD] =3D 0x64, + [PWRAP_MAN_RDATA] =3D 0x68, + [PWRAP_MAN_VLDCLR] =3D 0x6c, + [PWRAP_WACS0_EN] =3D 0x70, + [PWRAP_INIT_DONE0] =3D 0x74, + [PWRAP_WACS0_CMD] =3D 0x78, + [PWRAP_WACS0_RDATA] =3D 0x7c, + [PWRAP_WACS0_VLDCLR] =3D 0x80, + [PWRAP_WACS1_EN] =3D 0x84, + [PWRAP_INIT_DONE1] =3D 0x88, + [PWRAP_WACS1_CMD] =3D 0x8c, + [PWRAP_WACS1_RDATA] =3D 0x90, + [PWRAP_WACS1_VLDCLR] =3D 0x94, + [PWRAP_WACS2_EN] =3D 0x98, + [PWRAP_INIT_DONE2] =3D 0x9c, + [PWRAP_WACS2_CMD] =3D 0xa0, + [PWRAP_WACS2_RDATA] =3D 0xa4, + [PWRAP_WACS2_VLDCLR] =3D 0xa8, + [PWRAP_WACS3_EN] =3D 0xac, + [PWRAP_INIT_DONE3] =3D 0xb0, + [PWRAP_WACS3_CMD] =3D 0xb4, + [PWRAP_WACS3_RDATA] =3D 0xb8, + [PWRAP_WACS3_VLDCLR] =3D 0xbc, + [PWRAP_INT_EN] =3D 0xc0, + [PWRAP_INT_FLG_RAW] =3D 0xc4, + [PWRAP_INT_FLG] =3D 0xc8, + [PWRAP_INT_CLR] =3D 0xcc, + [PWRAP_SIG_ADR] =3D 0xd0, + [PWRAP_SIG_MODE] =3D 0xd4, + [PWRAP_SIG_VALUE] =3D 0xd8, + [PWRAP_SIG_ERRVAL] =3D 0xdc, + [PWRAP_CRC_EN] =3D 0xe0, + [PWRAP_TIMER_EN] =3D 0xe4, + [PWRAP_TIMER_STA] =3D 0xe8, + [PWRAP_WDT_UNIT] =3D 0xec, + [PWRAP_WDT_SRC_EN] =3D 0xf0, + [PWRAP_WDT_FLG] =3D 0xf4, + [PWRAP_DEBUG_INT_SEL] =3D 0xf8, + [PWRAP_DVFS_ADR0] =3D 0xfc, + [PWRAP_DVFS_WDATA0] =3D 0x100, + [PWRAP_DVFS_ADR1] =3D 0x104, + [PWRAP_DVFS_WDATA1] =3D 0x108, + [PWRAP_DVFS_ADR2] =3D 0x10c, + [PWRAP_DVFS_WDATA2] =3D 0x110, + [PWRAP_DVFS_ADR3] =3D 0x114, + [PWRAP_DVFS_WDATA3] =3D 0x118, + [PWRAP_DVFS_ADR4] =3D 0x11c, + [PWRAP_DVFS_WDATA4] =3D 0x120, + [PWRAP_DVFS_ADR5] =3D 0x124, + [PWRAP_DVFS_WDATA5] =3D 0x128, + [PWRAP_DVFS_ADR6] =3D 0x12c, + [PWRAP_DVFS_WDATA6] =3D 0x130, + [PWRAP_DVFS_ADR7] =3D 0x134, + [PWRAP_DVFS_WDATA7] =3D 0x138, + [PWRAP_DVFS_ADR8] =3D 0x13c, + [PWRAP_DVFS_WDATA8] =3D 0x140, + [PWRAP_DVFS_ADR9] =3D 0x144, + [PWRAP_DVFS_WDATA9] =3D 0x148, + [PWRAP_DVFS_ADR10] =3D 0x14c, + [PWRAP_DVFS_WDATA10] =3D 0x150, + [PWRAP_DVFS_ADR11] =3D 0x154, + [PWRAP_DVFS_WDATA11] =3D 0x158, + [PWRAP_DVFS_ADR12] =3D 0x15c, + [PWRAP_DVFS_WDATA12] =3D 0x160, + [PWRAP_DVFS_ADR13] =3D 0x164, + [PWRAP_DVFS_WDATA13] =3D 0x168, + [PWRAP_DVFS_ADR14] =3D 0x16c, + [PWRAP_DVFS_WDATA14] =3D 0x170, + [PWRAP_DVFS_ADR15] =3D 0x174, + [PWRAP_DVFS_WDATA15] =3D 0x178, + [PWRAP_SPMINF_STA] =3D 0x17c, + [PWRAP_CIPHER_KEY_SEL] =3D 0x180, + [PWRAP_CIPHER_IV_SEL] =3D 0x184, + [PWRAP_CIPHER_EN] =3D 0x188, + [PWRAP_CIPHER_RDY] =3D 0x18c, + [PWRAP_CIPHER_MODE] =3D 0x190, + [PWRAP_CIPHER_SWRST] =3D 0x194, + [PWRAP_DCM_EN] =3D 0x198, + [PWRAP_DCM_DBC_PRD] =3D 0x19c, + [PWRAP_EXT_CK] =3D 0x1a0, + [PWRAP_ADC_CMD_ADDR] =3D 0x1a4, + [PWRAP_PWRAP_ADC_CMD] =3D 0x1a8, + [PWRAP_ADC_RDATA_ADDR] =3D 0x1ac, + [PWRAP_GPS_STA] =3D 0x1b0, + [PWRAP_SW_RST] =3D 0x1b4, +}; + static const int mt6765_regs[] =3D { [PWRAP_MUX_SEL] =3D 0x0, [PWRAP_WRAP_EN] =3D 0x4, @@ -1302,6 +1444,7 @@ static const int mt8186_regs[] =3D { =20 enum pmic_type { PMIC_MT6323, + PMIC_MT6328, PMIC_MT6331, PMIC_MT6332, PMIC_MT6351, @@ -1314,6 +1457,7 @@ enum pmic_type { =20 enum pwrap_type { PWRAP_MT2701, + PWRAP_MT6735, PWRAP_MT6765, PWRAP_MT6779, PWRAP_MT6795, @@ -1733,6 +1877,10 @@ static void pwrap_init_chip_select_ext(struct pmic_w= rapper *wrp, u8 hext_write, static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) { switch (wrp->master->type) { + case PWRAP_MT6735: + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + pwrap_init_chip_select_ext(wrp, 0, 6, 0, 0); + break; case PWRAP_MT6795: if (wrp->slave->type =3D=3D PMIC_MT6331) { const u32 *dew_regs =3D wrp->slave->dew_regs; @@ -1839,6 +1987,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_CIPHER_START); break; case PWRAP_MT2701: + case PWRAP_MT6735: case PWRAP_MT6765: case PWRAP_MT6779: case PWRAP_MT6795: @@ -2194,6 +2343,14 @@ static const struct pwrap_slv_type pmic_mt6323 =3D { PWRAP_SLV_CAP_SECURITY, }; =20 +static const struct pwrap_slv_type pmic_mt6328 =3D { + .dew_regs =3D mt6328_regs, + .type =3D PMIC_MT6328, + .regops =3D &pwrap_regops16, + .caps =3D PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6331 =3D { .dew_regs =3D mt6331_regs, .type =3D PMIC_MT6331, @@ -2249,6 +2406,7 @@ static const struct pwrap_slv_type pmic_mt6397 =3D { =20 static const struct of_device_id of_slave_match_tbl[] =3D { { .compatible =3D "mediatek,mt6323", .data =3D &pmic_mt6323 }, + { .compatible =3D "mediatek,mt6328", .data =3D &pmic_mt6328 }, { .compatible =3D "mediatek,mt6331", .data =3D &pmic_mt6331 }, { .compatible =3D "mediatek,mt6351", .data =3D &pmic_mt6351 }, { .compatible =3D "mediatek,mt6357", .data =3D &pmic_mt6357 }, @@ -2277,6 +2435,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = =3D { .init_soc_specific =3D pwrap_mt2701_init_soc_specific, }; =20 +static const struct pmic_wrapper_type pwrap_mt6735 =3D { + .regs =3D mt6735_regs, + .type =3D PWRAP_MT6735, + .arb_en_all =3D GENMASK(9, 0), + .int_en_all =3D GENMASK(31, 0), + .spi_w =3D PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src =3D PWRAP_WDT_SRC_MASK_ALL, + .caps =3D PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock =3D pwrap_common_init_reg_clock, + .init_soc_specific =3D NULL, +}; + static const struct pmic_wrapper_type pwrap_mt6765 =3D { .regs =3D mt6765_regs, .type =3D PWRAP_MT6765, @@ -2446,6 +2616,7 @@ static const struct pmic_wrapper_type pwrap_mt8186 = =3D { =20 static const struct of_device_id of_pwrap_match_tbl[] =3D { { .compatible =3D "mediatek,mt2701-pwrap", .data =3D &pwrap_mt2701 }, + { .compatible =3D "mediatek,mt6735-pwrap", .data =3D &pwrap_mt6735 }, { .compatible =3D "mediatek,mt6765-pwrap", .data =3D &pwrap_mt6765 }, { .compatible =3D "mediatek,mt6779-pwrap", .data =3D &pwrap_mt6779 }, { .compatible =3D "mediatek,mt6795-pwrap", .data =3D &pwrap_mt6795 }, --=20 2.54.0 From nobody Mon Jun 8 08:36:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DF6B347536; Sun, 31 May 2026 09:10:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780218645; cv=none; b=LSpVep48INzl7S8HESbwfl3EPmlTATdZ5Rpb3Zxg7WWK2EMcxYW7w8JmlgEwrffE3UnxJ3xBbLNMh0qJ72LjWaiN0Y4+23y18Ol7DzX8h8c5ldsyMZIu/hSGa6Wmgby2BfaNPIiVSKEcIdCi7Vlcii9hfmh2rGd+y6mDe183+K0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780218645; c=relaxed/simple; bh=DdqK/2BJJV4g3ZVIXmhNOzVMvYMc2YKKn/YlljPOYyA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z5avaD33NIooxFhF2UoVVf0if/sC7U1u4zQSIKLN6AGDQsNv787Q+JEVU+qj6NbDy8VZ/rreiOKDiAc3zNsQ6ahbIIVAi6Ml0oamkuhLL5gAxQRclsP2+JiMAZFKYZflPIgXfOiT/29XW/n4BO32TKZ6LxLy0WwR2O3N882KB/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n73raWqb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n73raWqb" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1BBEAC2BCF5; Sun, 31 May 2026 09:10:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780218645; bh=DdqK/2BJJV4g3ZVIXmhNOzVMvYMc2YKKn/YlljPOYyA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=n73raWqbjb0ATFxppb/6Chv6vumNTbtsPKETdLkdbVcNH2MkbKBL6RWfjmt1qNQ8S EOSdkdJMKaQZvLG3pqrEv0Zh2iyK8AKKc38Va8SC3AUfQQMoNO+nPbpzENhALQYPI8 zX3qn5AjBTEMwDO1Kt5iWZWi6KoqCq0FE+xEmYUCUmvDEXFBTian0mQ4SMcuM4p0m4 bgy+pN85XQiGo881VVimKuZgwyid+FSQvtYMq4K0/LR9wWxr6AZSkZVSX9YYBUoXmU 41+LdneUI4C8tY+0g4QnmhZ9Q2c18EvTmyBKX1VgRyWpwG99F0u4UIcyHb4ti0stW7 Uyh7HEQ7CwtaA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15311CD6E5C; Sun, 31 May 2026 09:10:45 +0000 (UTC) From: Yassine Oudjana via B4 Relay Date: Sun, 31 May 2026 11:10:44 +0200 Subject: [PATCH v2 3/4] regulator: Add driver for MediaTek MT6328 PMIC regulators Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-mt6735-pwrap-mt6328-pmic-v2-3-dac37bf92894@protonmail.com> References: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com> In-Reply-To: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Flora Fu , Alexandre Mergnat , Liam Girdwood , Mark Brown , Dmitry Torokhov Cc: Yassine Oudjana , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-input@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780218643; l=20909; i=y.oudjana@protonmail.com; s=20260531; h=from:subject:message-id; bh=ZV16eUJqqhhkDsRYYP9hM6ap9Qo59vq8Wp4PUhyZHVU=; b=W8t9FvvKZhuZP+j4vECBTgcsXhD4zBoArzrZkqBDMx7AojbQ9tLViEm4BEV6mg0aB7mWCwzSV EKVv0UKLRT3D83wEoABi8ye5sCYBZQOemlQMopSZHZ9V6brrD/9Dua2 X-Developer-Key: i=y.oudjana@protonmail.com; a=ed25519; pk=sr7uwnyVqGKAIhvwnIwormkDM3d2VNc3VOTEU1GmsEM= X-Endpoint-Received: by B4 Relay for y.oudjana@protonmail.com/20260531 with auth_id=802 X-Original-From: Yassine Oudjana Reply-To: y.oudjana@protonmail.com From: Yassine Oudjana Add a driver for the regulators on the MT6328 PMIC. Signed-off-by: Yassine Oudjana --- drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6328-regulator.c | 500 +++++++++++++++++++++++++= ++++ include/linux/regulator/mt6328-regulator.h | 49 +++ 4 files changed, 559 insertions(+) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index a54a549196fe..a4f0c21aa6ea 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -919,6 +919,15 @@ config REGULATOR_MT6323 This driver supports the control of different power rails of device through regulator interface. =20 +config REGULATOR_MT6328 + tristate "MediaTek MT6328 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6328 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6331 tristate "MediaTek MT6331 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 134eee274dbf..4d1e40f0f911 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -109,6 +109,7 @@ obj-$(CONFIG_REGULATOR_MT6311) +=3D mt6311-regulator.o obj-$(CONFIG_REGULATOR_MT6315) +=3D mt6315-regulator.o obj-$(CONFIG_REGULATOR_MT6315) +=3D mt6316-regulator.o obj-$(CONFIG_REGULATOR_MT6323) +=3D mt6323-regulator.o +obj-$(CONFIG_REGULATOR_MT6328) +=3D mt6328-regulator.o obj-$(CONFIG_REGULATOR_MT6331) +=3D mt6331-regulator.o obj-$(CONFIG_REGULATOR_MT6332) +=3D mt6332-regulator.o obj-$(CONFIG_REGULATOR_MT6357) +=3D mt6357-regulator.o diff --git a/drivers/regulator/mt6328-regulator.c b/drivers/regulator/mt632= 8-regulator.c new file mode 100644 index 000000000000..a0e4226ffe37 --- /dev/null +++ b/drivers/regulator/mt6328-regulator.c @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MT6328 regulator driver + * Based on MT6323 driver. + * + * Copyright (c) 2016 MediaTek Inc. + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT6328_LDO_TABLE_MODE_NORMAL 0 +#define MT6328_LDO_TABLE_MODE_LP 1 + +/* + * MT6328 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + * @vselon_reg: Register sections for hardware control mode of bucks + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + */ +struct mt6328_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; +}; + +#define MT6328_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl) \ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + }, \ + .qi =3D BIT(13), \ + .vselon_reg =3D voselon, \ + .vselctrl_reg =3D vosel_ctrl, \ + .vselctrl_mask =3D BIT(1), \ +} + +#define MT6328_LDO_RANGE(match, vreg, min, max, step, volt_ranges, \ + enreg, enbit, vosel, vosel_mask, _modeset_reg, \ + _modeset_mask) \ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6328_LDO_TABLE(match, vreg, ldo_volt_table, enreg, enbit, \ + vosel, vosel_mask, _modeset_reg, _modeset_mask)\ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_table_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6328_LDO_TABLE_SINGLE_MODE(match, vreg, ldo_volt_table, enreg,\ + enbit, vosel, vosel_mask) \ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_table_single_mode_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D 0, \ + .modeset_mask =3D 0, \ +} + +#define MT6328_REG_FIXED(match, vreg, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask) \ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6328_REG_FIXED_SINGLE_MODE(match, vreg, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask) \ +[MT6328_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6328_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6328_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +static const struct linear_range buck_volt_range1[] =3D { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000) +}; + +static const struct linear_range buck_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(600000, 0, 0x7f, 6250) +}; + +static const struct linear_range buck_volt_range3[] =3D { + REGULATOR_LINEAR_RANGE(1200000, 0, 0x7f, 6250) +}; + +static const unsigned int ldo_volt_table1[] =3D { + 1500000, 1800000, 2500000, 2800000 +}; + +static const unsigned int ldo_volt_table2[] =3D { + 3300000, 3400000, 3500000, 3600000 +}; + +static const unsigned int ldo_volt_table3[] =3D { + 0, 0, 0, 1800000, 1900000, 2000000, 2100000, 2200000 +}; + +static const unsigned int ldo_volt_table4[] =3D { + 1700000, 1800000, 1860000, 2760000, 3000000, 3100000 +}; + +static const unsigned int ldo_volt_table5[] =3D { + 1800000, 2900000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table6[] =3D { + 2900000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table7[] =3D { + 2500000, 2900000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table8[] =3D { + 1300000, 1800000, 2900000, 3300000 +}; + +static const unsigned int ldo_volt_table9[] =3D { + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table10[] =3D { + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000 +}; + +static const unsigned int ldo_volt_table11[] =3D { + 900000, 1000000, 1100000, 1200000, 1300000, 1500000 +}; + +static const unsigned int ldo_volt_table12[] =3D { + 1200000, 1300000, 1500000, 1800000, 1825000 +}; + +static const unsigned int ldo_volt_table13[] =3D { + 1200000, 1300000, 1500000, 1800000 +}; + +static const unsigned int ldo_volt_table14[] =3D { + 1240000, 1390000, 1540000 +}; + +static const struct linear_range ldo_volt_range1[] =3D { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250) +}; + +static int mt6328_get_status(struct regulator_dev *rdev) +{ + int ret; + u32 regval; + struct mt6328_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->desc.enable_reg, ®val); + if (ret !=3D 0) { + dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); + return ret; + } + + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; +} + +static int mt6328_ldo_table_set_mode(struct regulator_dev *rdev, unsigned = int mode) +{ + int ret, val =3D 0; + struct mt6328_regulator_info *info =3D rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val =3D MT6328_LDO_TABLE_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6328_LDO_TABLE_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6328_ldo_table_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6328_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_STANDBY; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6328_volt_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6328_get_status, +}; + +static const struct regulator_ops mt6328_volt_table_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6328_get_status, + .set_mode =3D mt6328_ldo_table_set_mode, + .get_mode =3D mt6328_ldo_table_get_mode, +}; + +static const struct regulator_ops mt6328_volt_table_single_mode_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6328_get_status, +}; + +static const struct regulator_ops mt6328_volt_fixed_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6328_get_status, + .set_mode =3D mt6328_ldo_table_set_mode, + .get_mode =3D mt6328_ldo_table_get_mode, +}; + +/* The array is indexed by id(MT6328_ID_XXX) */ +static struct mt6328_regulator_info mt6328_regulators[] =3D { + MT6328_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, buck_volt_range1, MT= 6328_VPA_CON9, + MT6328_VPA_CON11, 0x3f, MT6328_VPA_CON12, MT6328_VPA_CON7), + MT6328_BUCK("buck_vproc", VPROC, 600000, 1393750, 6250, buck_volt_range2,= MT6328_VPROC_CON9, + MT6328_VPA_CON11, 0x7f, MT6328_VPROC_CON12, MT6328_VPROC_CON7), + MT6328_BUCK("buck_vcore1", VCORE1, 600000, 1393750, 6250, buck_volt_range= 2, + MT6328_VCORE1_CON9, MT6328_VCORE1_CON11, 0x7f, MT6328_VCORE1_CON12, + MT6328_VCORE1_CON7), + MT6328_BUCK("buck_vsys22", VSYS22, 1200000, 1993750, 6250, buck_volt_rang= e3, + MT6328_VSYS22_CON9, MT6328_VSYS22_CON11, 0x7f, MT6328_VSYS22_CON12, + MT6328_VSYS22_CON7), + MT6328_BUCK("buck_vlte", VLTE, 600000, 1393750, 6250, buck_volt_range2, M= T6328_VLTE_CON9, + MT6328_VLTE_CON11, 0x7f, MT6328_VLTE_CON12, MT6328_VLTE_CON7), + MT6328_REG_FIXED("ldo_vaux18", VAUX18, MT6328_VAUX18_CON0, 1, 1800000, MT= 6328_VAUX18_CON0, + BIT(0)), + MT6328_REG_FIXED("ldo_vtcxo_0", VTCXO_0, MT6328_VTCXO_0_CON0, 1, 2800000, + MT6328_VTCXO_0_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vtcxo_1", VTCXO_1, MT6328_VTCXO_1_CON0, 1, 2800000, + MT6328_VTCXO_1_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vaud28", VAUD28, MT6328_VAUD28_CON0, 1, 2800000, MT= 6328_VAUD28_CON0, + BIT(0)), + MT6328_REG_FIXED("ldo_vcn28", VCN28, MT6328_VCN28_CON0, 1, 2800000, MT632= 8_VCN28_CON0, + BIT(0)), + MT6328_LDO_TABLE_SINGLE_MODE("ldo_vcama", VCAMA, ldo_volt_table1, MT6328_= VCAMA_CON0, 1, + MT6328_ADLDO_ANA_CON5, 0x30), + MT6328_LDO_TABLE("ldo_vcn33_bt", VCN33_BT, ldo_volt_table2, MT6328_VCN33_= CON2, 1, + MT6328_ADLDO_ANA_CON6, 0x70, MT6328_VCN33_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcn33_wifi", VCN33_WIFI, ldo_volt_table2, MT6328_VC= N33_CON1, 1, + MT6328_ADLDO_ANA_CON6, 0x70, MT6328_VCN33_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vusb33", VUSB33, MT6328_VUSB33_CON0, 1, 3300000, MT= 6328_VUSB33_CON0, + BIT(0)), + MT6328_LDO_TABLE("ldo_vefuse", VEFUSE, ldo_volt_table3, MT6328_VEFUSE_CON= 0, 1, + MT6328_ADLDO_ANA_CON8, 0x70, MT6328_VEFUSE_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vsim1", VSIM1, ldo_volt_table4, MT6328_VSIM1_CON0, = 1, + MT6328_ADLDO_ANA_CON9, 0x70, MT6328_VSIM1_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vsim2", VSIM2, ldo_volt_table4, MT6328_VSIM2_CON0, = 1, + MT6328_ADLDO_ANA_CON10, 0x70, MT6328_VSIM2_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vemc_3v3", VEMC_3V3, ldo_volt_table5, MT6328_VEMC_3= V3_CON0, 1, + MT6328_ADLDO_ANA_CON11, 0x30, MT6328_VEMC_3V3_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vmch", VMCH, ldo_volt_table6, MT6328_VMCH_CON0, 1, + MT6328_ADLDO_ANA_CON12, 0x30, MT6328_VMCH_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vtref", VTREF, MT6328_VTREF_CON0, 1, 1800000, 0, 0), + MT6328_LDO_TABLE("ldo_vmc", VMC, ldo_volt_table5, MT6328_VMC_CON0, 1, MT6= 328_DLDO_ANA_CON0, + 0x30, MT6328_VMC_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcamaf", VCAMAF, ldo_volt_table9, MT6328_VCAMAF_CON= 0, 1, + MT6328_DLDO_ANA_CON1, 0x70, MT6328_VCAMAF_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vibr", VIBR, ldo_volt_table9, MT6328_VIBR_CON0, 1, + MT6328_DLDO_ANA_CON2, 0x70, MT6328_VIBR_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vio28", VIO28, MT6328_VIO28_CON0, 1, 2800000, MT632= 8_VIO28_CON0, + BIT(0)), + MT6328_LDO_TABLE("ldo_vgp1", VGP1, ldo_volt_table10, MT6328_VGP1_CON0, 1, + MT6328_DLDO_ANA_CON4, 0x70, MT6328_VGP1_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcamd", VCAMD, ldo_volt_table11, MT6328_VCAM_CON0, = 1, + MT6328_SLDO_ANA_CON2, 0x70, MT6328_VCAM_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vrf18_0", VRF18_0, MT6328_VRF18_0_CON0, 1, 1825000, + MT6328_VRF18_0_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vrf18_1", VRF18_1, ldo_volt_table12, MT6328_VRF18_1= _CON0, 1, + MT6328_SLDO_ANA_CON4, 0x30, MT6328_VRF18_1_CON0, BIT(0)), + MT6328_REG_FIXED("ldo_vio18", VIO18, MT6328_VIO18_CON0, 1, 1800000, MT632= 8_VIO18_CON0, + BIT(0)), + MT6328_REG_FIXED("ldo_vcn18", VCN18, MT6328_VCN18_CON0, 1, 1800000, MT632= 8_VCN18_CON0, + BIT(0)), + MT6328_LDO_TABLE("ldo_vcamio", VCAMIO, ldo_volt_table13, MT6328_VCAMIO_CO= N0, 1, + MT6328_SLDO_ANA_CON7, 0x30, MT6328_VCAMIO_CON0, BIT(0)), + MT6328_LDO_TABLE("ldo_vcamio", VCAMIO, ldo_volt_table13, MT6328_VCAMIO_CO= N0, 1, + MT6328_SLDO_ANA_CON7, 0x30, MT6328_VCAMIO_CON0, BIT(0)), + MT6328_LDO_RANGE("ldo_vsram", VSRAM, 700000, 1493750, 6250, ldo_volt_rang= e1, + MT6328_VSRAM_CON9, 1, MT6328_SLDO_ANA_CON9, 0x7f, MT6328_LDO_VSRAM_CON= 0, + BIT(0)), + MT6328_LDO_TABLE("ldo_vm", VM, ldo_volt_table14, MT6328_VM_CON0, 1, MT632= 8_SLDO_ANA_CON0, + 0x3, MT6328_VM_CON0, BIT(0)), +}; + +static int mt6328_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6328 =3D dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i =3D 0; i < MT6328_MAX_REGULATOR; i++) { + if (mt6328_regulators[i].vselctrl_reg) { + if (regmap_read(mt6328->regmap, + mt6328_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6328_regulators[i].vselctrl_mask) { + mt6328_regulators[i].desc.vsel_reg =3D + mt6328_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6328_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6328 =3D dev_get_drvdata(pdev->dev.parent); + struct regulator_config config =3D {}; + struct regulator_dev *rdev; + int i; + + /* Query buck controller to select activated voltage register part */ + if (mt6328_set_buck_vosel_reg(pdev)) + return -EIO; + + for (i =3D 0; i < MT6328_MAX_REGULATOR; i++) { + config.dev =3D &pdev->dev; + config.driver_data =3D &mt6328_regulators[i]; + config.regmap =3D mt6328->regmap; + rdev =3D devm_regulator_register(&pdev->dev, + &mt6328_regulators[i].desc, &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6328_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + return 0; +} + +static const struct platform_device_id mt6328_platform_ids[] =3D { + { "mt6328-regulator" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6328_platform_ids); + +static struct platform_driver mt6328_regulator_driver =3D { + .driver =3D { + .name =3D "mt6328-regulator", + }, + .probe =3D mt6328_regulator_probe, + .id_table =3D mt6328_platform_ids, +}; + +module_platform_driver(mt6328_regulator_driver); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6328 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/regulator/mt6328-regulator.h b/include/linux/reg= ulator/mt6328-regulator.h new file mode 100644 index 000000000000..0f82aa88493b --- /dev/null +++ b/include/linux/regulator/mt6328-regulator.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016 MediaTek Inc. + * Copyright (c) 2022 Yassine Oudjana + */ + +#ifndef __LINUX_REGULATOR_MT6328_H +#define __LINUX_REGULATOR_MT6328_H + +enum { + MT6328_ID_VPA =3D 0, + MT6328_ID_VPROC, + MT6328_ID_VCORE1, + MT6328_ID_VSYS22, + MT6328_ID_VLTE, + MT6328_ID_VAUX18, + MT6328_ID_VTCXO_0, + MT6328_ID_VTCXO_1, + MT6328_ID_VAUD28, + MT6328_ID_VCN28, + MT6328_ID_VCAMA, + MT6328_ID_VCN33_BT, + MT6328_ID_VCN33_WIFI, + MT6328_ID_VUSB33, + MT6328_ID_VEFUSE, + MT6328_ID_VSIM1, + MT6328_ID_VSIM2, + MT6328_ID_VEMC_3V3, + MT6328_ID_VMCH, + MT6328_ID_VTREF, + MT6328_ID_VMC, + MT6328_ID_VCAMAF, + MT6328_ID_VIBR, + MT6328_ID_VIO28, + MT6328_ID_VGP1, + MT6328_ID_VCAMD, + MT6328_ID_VRF18_0, + MT6328_ID_VRF18_1, + MT6328_ID_VIO18, + MT6328_ID_VCN18, + MT6328_ID_VCAMIO, + MT6328_ID_VSRAM, + MT6328_ID_VM, + MT6328_ID_RG_MAX, +}; + +#define MT6328_MAX_REGULATOR MT6328_ID_RG_MAX + +#endif /* __LINUX_REGULATOR_MT6328_H */ --=20 2.54.0 From nobody Mon Jun 8 08:36:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5628A348C65; Sun, 31 May 2026 09:10:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780218645; cv=none; b=PvNklpiyzyMaOFTSkPCGkVf6wlVpt4ZPwOvwBKWgzG+gLdnHVX5QX8OsEpmHHScSmWt405c9rbT7c4eFjPWsmNPasuXghd7KWcrnPhBmHLZwueVA09gKVqs8qd5RuDAORBLsZQ4qaKKXNfj5X6jU5UR6zbAxhE1gTpJS4dx1zgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780218645; c=relaxed/simple; bh=6/oMIOAJ1Qzv7x2FN/hHsOLQFSqBCNkvqDPY2Y8JW24=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OitWnE2kNJ1poSYuHrSjrxC2YXMeddMVSz9UztbSujgLzbDX9VmwCpObHp4REPNnScqCdI1Y6IzujcVvod2f9J0mRde0ghi51i+NTOugGe6rCrR8wHyVa4bPqJkjSqYP55sGeXTKeIr05m9GOXrYEwvq2yp/LxVu9EMdM/6Rvqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iXzL26yt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iXzL26yt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 292D9C2BCFA; Sun, 31 May 2026 09:10:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780218645; bh=6/oMIOAJ1Qzv7x2FN/hHsOLQFSqBCNkvqDPY2Y8JW24=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iXzL26ytLKY2kWbtMH/8kkPcRAd5Ri2U43UyF30R34udyttJ9oNcm92e04e4iPZYJ v9HEQdLnKUchGkU8BQ/li2h4ligNIAFb5b+JKr7Q5RJ4ZzCqb3NdLRgSWHyWW1W2RP tWY60yFH12g+m0itr24pb+mTL45tdNKuWHQqBonIEAgNyfwio8Cb5HUUwwIETHgYLk 0vmDetHL4sJZyfAs1RHULpIBau3DsUGIOgjrRA5MU5TjKjI5+AIEJoE3GLyPOSzsnE sH3YhntSnx1RBh1z5wnp2Cme6AcAfGf5v07TimLnNzrV2TQQl75sIzJ/jZYhcRGdxa XuXgocVUctWOw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20867CD6E56; Sun, 31 May 2026 09:10:45 +0000 (UTC) From: Yassine Oudjana via B4 Relay Date: Sun, 31 May 2026 11:10:45 +0200 Subject: [PATCH v2 4/4] Input: mtk-pmic-keys - Add support for MT6328 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-mt6735-pwrap-mt6328-pmic-v2-4-dac37bf92894@protonmail.com> References: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com> In-Reply-To: <20260531-mt6735-pwrap-mt6328-pmic-v2-0-dac37bf92894@protonmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Flora Fu , Alexandre Mergnat , Liam Girdwood , Mark Brown , Dmitry Torokhov Cc: Yassine Oudjana , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-input@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780218643; l=1904; i=y.oudjana@protonmail.com; s=20260531; h=from:subject:message-id; bh=CI2JtjrfQGfceMW9Mo7uuZDEncWSbsLSjy6NPimDCZ8=; b=YumAYlYpzOnp4NdRv+QSZzgC27vFRedblud7yqmZoD1WccQnx+bmUwOBZrHH5iqjvuYbuKUR/ 4msldZHl4rBCGFN1KEIleh8cgcC0AuzhnP4TgGssjazW09rDi/Yage7 X-Developer-Key: i=y.oudjana@protonmail.com; a=ed25519; pk=sr7uwnyVqGKAIhvwnIwormkDM3d2VNc3VOTEU1GmsEM= X-Endpoint-Received: by B4 Relay for y.oudjana@protonmail.com/20260531 with auth_id=802 X-Original-From: Yassine Oudjana Reply-To: y.oudjana@protonmail.com From: Yassine Oudjana Add a compatible string and related data for the PMIC keys on the MT6328 PMIC. Signed-off-by: Yassine Oudjana Acked-by: Dmitry Torokhov Reviewed-by: AngeloGioacchino Del Regno --- drivers/input/keyboard/mtk-pmic-keys.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboar= d/mtk-pmic-keys.c index c78d9f6d97c4..6aaca67e7703 100644 --- a/drivers/input/keyboard/mtk-pmic-keys.c +++ b/drivers/input/keyboard/mtk-pmic-keys.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -80,6 +81,17 @@ static const struct mtk_pmic_regs mt6323_regs =3D { .rst_lprst_mask =3D MTK_PMIC_RST_DU_MASK, }; =20 +static const struct mtk_pmic_regs mt6328_regs =3D { + .keys_regs[MTK_PMIC_PWRKEY_INDEX] =3D + MTK_PMIC_KEYS_REGS(MT6328_TOPSTATUS, + 0x2, MT6328_INT_MISC_CON, 0x4, MTK_PMIC_PWRKEY_RST), + .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =3D + MTK_PMIC_KEYS_REGS(MT6328_TOPSTATUS, + 0x4, MT6328_INT_MISC_CON, 0x2, MTK_PMIC_HOMEKEY_RST), + .pmic_rst_reg =3D MT6328_TOP_RST_MISC, + .rst_lprst_mask =3D MTK_PMIC_RST_DU_MASK, +}; + static const struct mtk_pmic_regs mt6331_regs =3D { .keys_regs[MTK_PMIC_PWRKEY_INDEX] =3D MTK_PMIC_KEYS_REGS(MT6331_TOPSTATUS, 0x2, @@ -304,6 +316,9 @@ static const struct of_device_id of_mtk_pmic_keys_match= _tbl[] =3D { }, { .compatible =3D "mediatek,mt6323-keys", .data =3D &mt6323_regs, + }, { + .compatible =3D "mediatek,mt6328-keys", + .data =3D &mt6328_regs, }, { .compatible =3D "mediatek,mt6331-keys", .data =3D &mt6331_regs, --=20 2.54.0