From nobody Mon Jun 8 09:49:40 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32B3732B132; Sat, 30 May 2026 15:31:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155103; cv=none; b=jC3zmR7cF/tR5VZ2rQiXpfa2nYjQ+xCl+IZUdFssuvWq+G9RoXE1nzG6Aa4Id+jsn8urbVWXvKAj3zkpvhDXcqhomsQ4W7A6+miMHPnGxA6k1aQbvw+FtcSn3EkElB2Jpnt5ASC2DPbM2n6vw3ZwEY/wxgw8nR+ilQHVvxKL+N8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155103; c=relaxed/simple; bh=9Wi8kdht8lhxIjVDT1F1ydsI+q/9FXN2ycAGic8ObUM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tgIOZrZq7eAEGWGbA96NtGOEg/KzIxUZoM/9goINA+5AquJFMuuQz16QvvYJC45HTikIfdZCkOtL7t4Ajf4i+iDUeUFC0AqF5caE6NeanStbUcBWBrGj0/pT+tyoZRm7QLMgkHrcr1Uaxsy73zf1rvfVDIt5sPfGnezFA/NcyQ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=DE7HBqXE; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="DE7HBqXE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=uU GqaCcyquHK8pE7kIHQ3gogw7hU58ZTcDwGQkRQHYQ=; b=DE7HBqXE2n39u44hH3 Q79Q8U0OHWgG4rN2L8BQay9lC0uIsRaTM/1+58yr4Ca7JpONou740vwYhtWsZYUL FxFAb6Njn0uF63QALQKuaSB+diq1PVX37AYKJC8HVZe3UpWOEKFueHMVg/ePpu3O SqkwtELU6Pj27vHiTwkBZt29c= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnfA+4AhtqjqjeAQ--.36562S3; Sat, 30 May 2026 23:31:06 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 01/16] PCI: dwc: Add pcie_cap field and helper in designware header Date: Sat, 30 May 2026 23:30:46 +0800 Message-Id: <20260530153101.695580-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnfA+4AhtqjqjeAQ--.36562S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7KFWxCF4kArWUWw4fGr1fXrb_yoW8Ww45pa y7JF1akF48AFWavF43AanxZr15tF93ArW7Ga9rKw1SgFyaya4UGa10yryYyF17Kr4Ikrya kw45t34rCF45JFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zN4E_UUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6xoQs2obArovlAAA3g Content-Type: text/plain; charset="utf-8" Add a pcie_cap field to struct dw_pcie to store the offset of the PCI Express Capability structure. Provide a helper dw_pcie_get_pcie_cap() which performs the capability search on first call and caches the result. This is a preparatory step for replacing repetitive capability searches in both core and platform drivers. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 7dac37521b8e..561b434fe335 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -596,6 +596,8 @@ struct dw_pcie { * use_parent_dt_ranges to true to avoid this warning. */ bool use_parent_dt_ranges; + + u8 pcie_cap; /* PCIe capability offset */ }; =20 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -834,6 +836,21 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pci= e *pci) dw_pcie_writel_dbi(pci, reg, val); } =20 +/** + * dw_pcie_get_pcie_cap() - Return cached PCIe Capability offset + * @pci: DWC instance + * + * Finds and caches the offset of PCI_CAP_ID_EXP on first call. + * Returns 0 if the capability is not present. + */ +static inline u8 dw_pcie_get_pcie_cap(struct dw_pcie *pci) +{ + if (!pci->pcie_cap) + pci->pcie_cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + return pci->pcie_cap; +} + static inline int dw_pcie_start_link(struct dw_pcie *pci) { if (pci->ops && pci->ops->start_link) --=20 2.34.1 From nobody Mon Jun 8 09:49:40 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23FD532AAB5; Sat, 30 May 2026 15:36:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155383; cv=none; b=BQ1RGxin6i6Gp0vzB17C5GI2LlX5GXApS7oYakNj0vun2n516wlyVD4fCrixx/rNU5wtiP8/MTgUNdB36dF+ht+Hn80VsLw0lPCkD0i6CqMDSNNLEjq6nhatv6EZTMySAnd4Z4z3i2qr77tDRRb3q04tX5CFxdsPMmYtpAkJiBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155383; c=relaxed/simple; bh=CYQKlMS4vwJEVcoNDL4H9KtJy4p/r0VknULP3APC4go=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UzsJC60ekEB6MH56EFL1kJNvBdnLtY+XdJJsz5l4RA876y55prrUpAKaguqmX2Y7C/sXsuVEolIQ/5IPfq1h+tbqa+EZslKsRTv5BP9XFA38GKX6QPImtXr97K9rk8JQOXyTrWZ3EzRzwFTwCe+r2dagAFyPT67jzv9l0ZsniP0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=le3EBQBl; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="le3EBQBl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Di vrsgUAlYu1c4Ug4K0z9/9Rqe9VK3xx/y1rw22Gnx8=; b=le3EBQBlT1SY1/VUFY qjBR1Yo8F8gJZieTuRsR30DdK9PsSXljr5uQJBFwMCCl20AG+qS9i7tN4Q3Iw3FD AE0xDIB75i4whcOpQaf7WRyTiof8V79hfo69IuFd7soEJcvtINNJcLjx0ioH9lku co7ReVYm+gY13lug+NWbqGlo4= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnfA+4AhtqjqjeAQ--.36562S4; Sat, 30 May 2026 23:31:07 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 02/16] PCI: dwc: Use cached PCIe capability offset in core Date: Sat, 30 May 2026 23:30:47 +0800 Message-Id: <20260530153101.695580-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnfA+4AhtqjqjeAQ--.36562S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxtr1xCFWfZw4UCFW3tr4kXrb_yoW7AF47pa y3XF1FyF18AF45ZFnI9a95Zr13tF9xAFW7Ca92gr1SvFy2yFW7Ka10yry3trn7KFsFvryY 9w18trW5Cw15JFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zMmhFUUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBsQs2obArt5rwAA3i Content-Type: text/plain; charset="utf-8" Modify the DWC core functions to use the cached pcie_cap offset instead of calling dw_pcie_find_capability() each time. In the DWC core, dw_pcie_find_capability() is called at several locations: - dw_pcie_ep_init_non_sticky_registers() - dw_pcie_wait_for_link() - dw_pcie_link_set_max_speed() - dw_pcie_link_get_max_link_width() - dw_pcie_link_set_max_link_width() The cached offset is initialized after hardware is ready: - In host mode: dw_pcie_host_init() calls pp->ops->host_init() (enables clocks/resets), then dw_pcie_get_pcie_cap() caches the offset. - In endpoint mode: dw_pcie_ep_init() calls ep->ops->pre_init() (enables hardware), then dw_pcie_get_pcie_cap() caches the offset. dw_pcie_ep_init_non_sticky_registers() is called after pre_init, so it can use dw_pcie_get_pcie_cap() safely. The other functions run after probe, so pci->pcie_cap is already valid and can be used directly. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware-ep.c | 4 +++- .../pci/controller/dwc/pcie-designware-host.c | 2 ++ drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++---------- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index a396b58d6746..11b4fa6d129c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -1246,7 +1246,7 @@ static void dw_pcie_ep_init_non_sticky_registers(stru= ct dw_pcie *pci) * to all other functions as well. */ if (funcs > 1) { - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); func0_lnkcap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); func0_lnkcap =3D FIELD_GET(PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS, func0_lnkcap); @@ -1524,6 +1524,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ep->ops->pre_init) ep->ops->pre_init(ep); =20 + dw_pcie_get_pcie_cap(pci); + ret =3D pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, ep->page_size); if (ret < 0) { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index cffb34f6f3a9..b8175138e47a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -593,6 +593,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) goto err_free_ecam; } =20 + dw_pcie_get_pcie_cap(pci); + if (pci_msi_enabled()) { pp->use_imsi_rx =3D !(pp->ops->msi_init || of_property_present(np, "msi-parent") || diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 37d2715e38eb..810e920c1d8b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -765,7 +765,7 @@ const char *dw_pcie_ltssm_status_string(enum dw_pcie_lt= ssm ltssm) */ int dw_pcie_wait_for_link(struct dw_pcie *pci) { - u32 offset, val, ltssm; + u32 val, ltssm; int retries; =20 /* Check if the link is up or not */ @@ -811,8 +811,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) if (pci->max_link_speed > 2) msleep(PCIE_RESET_CONFIG_WAIT_MS); =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); =20 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", FIELD_GET(PCI_EXP_LNKSTA_CLS, val), @@ -848,7 +847,7 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) { u32 cap, ctrl2, link_speed; - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; =20 cap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); =20 @@ -894,8 +893,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *= pci) =20 int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) { - u8 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u32 lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + u32 lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); =20 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); } @@ -903,7 +901,6 @@ int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { u32 lnkcap, lwsc, plc; - u8 cap; =20 if (!num_lanes) return; @@ -940,10 +937,9 @@ static void dw_pcie_link_set_max_link_width(struct dw_= pcie *pci, u32 num_lanes) dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); =20 - cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_writel_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP, lnkcap); } =20 void dw_pcie_iatu_detect(struct dw_pcie *pci) --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F31F032A3C8; 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(unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnfA+4AhtqjqjeAQ--.36562S5; Sat, 30 May 2026 23:31:08 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 03/16] PCI: dwc: imx6: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:48 +0800 Message-Id: <20260530153101.695580-4-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnfA+4AhtqjqjeAQ--.36562S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7CF18ZFW7uF45Zr4ktry7ZFb_yoW8uF43pa y3u3yFyr4rJF42qFsFy3Z8ur13tasIkw47Jw47Kw1Sq347JryDWFy0yry3ta1akrWkKFy7 AF1xtFyfJryFyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zKsjUbUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7BwRtGobArw5dgAA3V Content-Type: text/plain; charset="utf-8" Thus, the cached offset is available when these functions are called, and DBI access occurs only after hardware is enabled. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pci-imx6, dw_pcie_find_capability() is called in the following call chain: static const struct dw_pcie_ops dw_pcie_ops =3D { .start_link =3D imx_pcie_start_link, }; imx_pcie_start_link() -> dw_pcie_find_capability() -> imx_pcie_ltssm_enable() -> dw_pcie_find_capability() Replace these calls with the cached pci->pcie_cap. The call chain after modification becomes: dw_pcie_host_init() -> pp->ops->init() [imx6_pcie_host_init] -> dw_pcie_get_pcie_cap() (caches offset) -> pci->ops->start_link =3D imx_pcie_start_link -> uses pci->pcie_cap -> imx_pcie_ltssm_enable() -> uses pci->pcie_cap --- drivers/pci/controller/dwc/pci-imx6.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 773ab65b2afa..de06ff429eff 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -933,10 +933,10 @@ static void imx_pcie_ltssm_enable(struct device *dev) { struct imx_pcie *imx_pcie =3D dev_get_drvdata(dev); const struct imx_pcie_drvdata *drvdata =3D imx_pcie->drvdata; - u8 offset =3D dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); + struct dw_pcie *pci =3D imx_pcie->pci; u32 tmp; =20 - tmp =3D dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); + tmp =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp)); if (drvdata->ltssm_mask) regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->lt= ssm_mask, @@ -962,7 +962,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci) { struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); struct device *dev =3D pci->dev; - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 tmp; int ret; =20 --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC28514ABE; Sat, 30 May 2026 15:31:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155101; cv=none; b=XMAGscBt6TOCw35sZpsDpKNlMt9FQT2SGIN8GK59jKD2QUav39/xGNw9Si3VWgF1eVGoo7fuD6DUfJPeLerOcJMgv/6HWouL7sn8shqAX1iSkIzA/8n6iYApq8hESGWUysTyHfcQ+vcAvtg012//baDs2sFPsR5RQxWwxlcO8ds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155101; c=relaxed/simple; bh=CwQvJhYMmSpEtBnu8YgoO14KM8+fei2hTUBjvIMzffE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jnOxItW8QkPBX+rFQe2X7L9wgt7vduwMIcoJOW0vG5mlLfmMS9th3tgR9N/Dsz1ihib++rh63/6XIgQWPvb8hq5gnzFlbrK0AdJO1zCygOJjSJ9yT8E6jkxHMBqCCyL4peYEPShT97/QGotgfUQThUpe1t627tk26u0oBFSnmbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=eT8GqHUC; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="eT8GqHUC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=sC 5IK7rcAYFVlcW/qRjCYlhzV8RYd8qBA49KkuguIVM=; b=eT8GqHUCGLC9IgExlr m7fELH0xN24rgY9XrNisOTFUZ76V/XRZclI+SkVjn9KyidK8trIHHYR82M7n1MN5 YnvNpOPCp5wD52jDlJPooF6O9bQOElbUxlpAcNBVLka493ELYFo2q8UgPHlfmi1k 4gEPT7bMi00N8RSm0gI5jJjHM= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnfA+4AhtqjqjeAQ--.36562S6; Sat, 30 May 2026 23:31:08 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 04/16] PCI: dwc: layerscape-ep: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:49 +0800 Message-Id: <20260530153101.695580-5-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnfA+4AhtqjqjeAQ--.36562S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxZF15KF4kXF1ktr18Gry8Xwb_yoW5GF1kpF WUXF4YkF18Jr4SgFsrZan8Wr13GF9akFy7J397Kr1aqry2vryUGa90yry5tFn7GFWqkFyj 934rtFy7u345JrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRByIUUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwxwRtGobArx1sAAA3w Content-Type: text/plain; charset="utf-8" Replace these with dw_pcie_get_pcie_cap(). The hardware is already enabled by the driver before ls_pcie_ep_probe() and before the interrupt handler runs. dw_pcie_get_pcie_cap() will cache the offset on first call, and subsequent calls (including inside dw_pcie_ep_init) will use the cached value without re-searching. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pci-layerscape-ep, dw_pcie_find_capability() is called in: ls_pcie_ep_probe() -> offset =3D dw_pcie_find_capability() -> pcie->lnkcap =3D dw_pcie_readl_dbi(offset + PCI_EXP_LNKCAP) -> dw_pcie_ep_init() -> ls_pcie_ep_interrupt_init() -> devm_request_irq(..., ls_pcie_ep_event_handler) -> ls_pcie_ep_event_handler() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pci-layerscape-ep.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/c= ontroller/dwc/pci-layerscape-ep.c index 8936975ff104..b2d0b51df3c5 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -74,7 +74,6 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) struct ls_pcie_ep *pcie =3D dev_id; struct dw_pcie *pci =3D pcie->pci; u32 val, cfg; - u8 offset; =20 val =3D ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR); ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); @@ -83,9 +82,6 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) return IRQ_NONE; =20 if (val & PEX_PF0_PME_MES_DR_LUD) { - - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - /* * The values of the Maximum Link Width and Supported Link * Speed from the Link Capabilities Register will be lost @@ -93,7 +89,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) * that configured by the Reset Configuration Word (RCW). */ dw_pcie_dbi_ro_wr_en(pci); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); + dw_pcie_writel_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP, + pcie->lnkcap); dw_pcie_dbi_ro_wr_dis(pci); =20 cfg =3D ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG); @@ -266,7 +263,7 @@ static int __init ls_pcie_ep_probe(struct platform_devi= ce *pdev) =20 platform_set_drvdata(pdev, pcie); =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); pcie->lnkcap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); =20 ret =3D dw_pcie_ep_init(&pci->ep); --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A692532BF51; Sat, 30 May 2026 15:33:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155240; cv=none; b=cPmKKErZiES4VKgOWKh+2aYxCEPVLhjD/DhAWJeluiFRK8F87W6/frUcZVTqFC+WmYUqHZoRfli7/iW+iVxydm0Wsqhb2YhCTv4Sh+h090lKPKVEHzEsj2vRqptNaLmch1XNyxinC78hDOknjVkdBbAWVtEsFs39feEsD0hDYCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155240; c=relaxed/simple; bh=7u0KqMhAmfZ5YzxjvWVxWLyTqnuiOJ8Zwl6g1JFDc0s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SLc+VyYCVoz3SZe97LqWIRbRlcDdxrYIjGrV5sm3HYR7bBkGwUWO/WqhGA8PSpVk+g3NGx9dMch98ijqOtD4g75XY42OLmAHPDiBOQ39ceSG25QFc7156njxbJJK+46f4hyp33xcjrOGfTOF5nUZl/DQy6nDOldH2qx9Lm8VclU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=BCYxZx27; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="BCYxZx27" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Ne ek+llzPudCPeZmIqDmflPD95hch6yR65a+6hnW9n0=; b=BCYxZx275ZAh7SiUm0 J5ZfDuMzpXn77fu1RBjV8/JBS17LByeLr1IwPDLoi3V04JlbK7ikrLhfGYLpLWUq vVRdjf5nLrjq1gnTKkD11U1PmxPPlAqSFqZzTNADGaFrs2fgMtQ5xxjAvlhh9zFs 93QTC3g/CjtUw28FuxjUMu78g= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnfA+4AhtqjqjeAQ--.36562S7; Sat, 30 May 2026 23:31:09 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 05/16] PCI: dwc: meson: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:50 +0800 Message-Id: <20260530153101.695580-6-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnfA+4AhtqjqjeAQ--.36562S7 X-Coremail-Antispam: 1Uf129KBjvJXoW7CFy3CFyDGrWDZw47Jw1xGrg_yoW8AFWkpF WYgr4jyr18Ar4YgwnrCan5ZFy3J3Z8Ar47Ja93Kw1SvFy7KFsrJ34akFWYka4xWF4293W5 CF98tryUZwn5trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRBMKZUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwx0RtGobAr11ygAA3K Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() calls pp->ops->init (meson_pcie_host_init) before caching the offset. Therefore, inside .init we must call dw_pcie_get_pcie_cap() to obtain the offset (the helper will perform the DBI read and cache the result). This is safe because the hardware is already enabled by the driver's own initialization. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pci-meson, the call chain is: static const struct dw_pcie_host_ops meson_pcie_host_ops =3D { .init =3D meson_pcie_host_init, }; meson_pcie_host_init() -> meson_set_max_payload() -> dw_pcie_find_capability() -> meson_set_max_rd_req_size() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pci-meson.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index 0694084f612b..81767d010c84 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -276,7 +276,7 @@ static void meson_set_max_payload(struct meson_pcie *mp= , int size) { struct dw_pcie *pci =3D &mp->pci; u32 val; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D dw_pcie_get_pcie_cap(pci); int max_payload_size =3D meson_size_to_payload(mp, size); =20 val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); @@ -292,7 +292,7 @@ static void meson_set_max_rd_req_size(struct meson_pcie= *mp, int size) { struct dw_pcie *pci =3D &mp->pci; u32 val; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D dw_pcie_get_pcie_cap(pci); int max_rd_req_size =3D meson_size_to_payload(mp, size); =20 val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CEDE32470A; Sat, 30 May 2026 15:31:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155101; cv=none; b=o/f4BvwzdCas37pspU5myuppiRpaUMNbybbnqZw50kqHHqbbC72Sr5td0cYqNScye2VyYPnCal/GxHtSkjv+MQcY+k4xr/RsljSkD8gTqRBg9A1LSUe4AdNAJr+GNxzO1bd3C52pi0JbD62CtU1ixT3G9FyWi8kEd+jhR3k6hRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155101; c=relaxed/simple; bh=mIytoK3lew0cX17GUo/AcvnZGAx0EilUFv+nt/as9Ms=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rz8J1uzRjNyOOfIS4Iu11a8xEf6F0Ph0XooBy0lg4Zfl1XDvkljVzXC2YTU50L785G/l2lun0BIvJ4e3vK1yUpsjlphX+wKQh6hz1vKKReU0nsEfG3ZFoyNHqoVHrB/MB86AxMtpXD6ODNB0LN0flJDTeeNITzSsEqMwmoy3Qdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=IP8e1nK+; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="IP8e1nK+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=4y 5vcEN60ecF7HKIQYbaUtTi06S+eWZoH1exAeXgq1g=; b=IP8e1nK+YQJKgRSENz A4hPpTSnQju/btwFm6lTAJyGXOT08Y4XTZNx75sth5nXlKu2wLCOrdtz/XCBNYA7 Ur/dESOOCWkHAwiDvG8KF4l/wZyWWvl8nwDcIkG+uUXBB9Q7j+OG+k4/rhdqtsA7 03GKZR23MrpJMZ2tfzLfJw3Hg= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnfA+4AhtqjqjeAQ--.36562S8; Sat, 30 May 2026 23:31:09 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 06/16] PCI: dwc: rockchip: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:51 +0800 Message-Id: <20260530153101.695580-7-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnfA+4AhtqjqjeAQ--.36562S8 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZFy3CF1kCF43ZrW7AF15XFb_yoW8JF4Dpa yYyryjyryrGr4Sg3Z2v3Z8ur1SqF9xArW7Ja97Gw1SvFy2k34UG3yYkr98tFn7GF4jyFyY kw1Ut34rGrsxAFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRBMKZUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6x0RtGobAr0v7QAA3f Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() calls .init before caching the offset. So inside .init we call dw_pcie_get_pcie_cap() to trigger caching. The helper will perform the DBI read (hardware is already enabled) and cache the result. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Sebastian Reichel --- In pcie-dw-rockchip, the call chain is: static const struct dw_pcie_host_ops rockchip_pcie_host_ops =3D { .init =3D rockchip_pcie_host_init, }; rockchip_pcie_host_init() -> rockchip_pcie_enable_l0s() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 731d93663cca..be8b6187913d 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -369,7 +369,7 @@ static void rockchip_pcie_enable_l0s(struct dw_pcie *pc= i) u32 cap, lnkcap; =20 /* Enable L0S capability for all SoCs */ - cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + cap =3D dw_pcie_get_pcie_cap(pci); if (cap) { lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); lnkcap |=3D PCI_EXP_LNKCAP_ASPM_L0S; --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2F96306B08; Sat, 30 May 2026 15:31:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155104; cv=none; b=A/3c61Z8sjy8B97aG2mslYTWvpLVSpCx1XZMNrxIdVyTXyEzWiYrSlzGo3gyPMz4zzENZ7brTjzNyL2/1w5xYEBk/9Tx0bUaRU2sggnHjLY7Uz0Pd/gb82FaILYgPdFg9tqbgYN0V3da8UB10S/56R1WjAzcZQitX41vqiNgoiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155104; c=relaxed/simple; bh=aTSU8cGptt1iIE491RxaEDXSLRqZ0TwtMEh+pilwLoU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lq5wRCBQ2rmebsp4iSiaIu5SGToPMRy63Zk2rPh+TDsppko6SKS30amWYFWPlxwB+6pko64Nm2/kaoJYRifNrHwc4JxflIxCc+Ok8/OaJD+USEvBCaM9m3Pqq8S023o3jCT5MF1wRTpo1HcZagm9hpG4pYKDeWW1f30txdOT2pg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=J3ObC2xs; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="J3ObC2xs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=S4 lPlR1q4qSCvgYn9gZFu5HucqogfFBKik1eEg5ZKUU=; b=J3ObC2xs9IuhhNFDur R19XIdKEIuYSWquw8LzS/KzTWzLBaJt6PCujE45xBlnPi0RwyruDgsW5i4bimK3e 8QHGPDDdxH2YF2pIli1zUZ8A5Oo3wANTgLjvAy5/n4sOK/xwQbJwa5TXODHV8Cdn PJlWiFy3eeAbvvj9SKNLGmBxs= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnfA+4AhtqjqjeAQ--.36562S9; Sat, 30 May 2026 23:31:10 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 07/16] PCI: dwc: eswin: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:52 +0800 Message-Id: <20260530153101.695580-8-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnfA+4AhtqjqjeAQ--.36562S9 X-Coremail-Antispam: 1Uf129KBjvdXoWrKF4UZFW8XF4kWw18tr1DZFb_yoWkuFXE9a 4DKr9rAr47GF90k3Zavw4fAF9Fya4xXr1293WFyF9xZFyIgr1jgrnFqF98AFWxCFn5XFyr Jr4qvFyxAryUJjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRi6pB3UUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7B4RtGobAr45vAAA3f Content-Type: text/plain; charset="utf-8" This function is called after dw_pcie_host_init() has already cached the offset (dw_pcie_link_up() is called after .init and after caching). Therefore, we can directly use pci->pcie_cap. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-eswin, the call chain is: static const struct dw_pcie_ops dw_pcie_ops =3D { .link_up =3D eswin_pcie_link_up, }; eswin_pcie_link_up() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-eswin.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-eswin.c b/drivers/pci/controll= er/dwc/pcie-eswin.c index ce8d64f8a395..6a37fd5a8384 100644 --- a/drivers/pci/controller/dwc/pcie-eswin.c +++ b/drivers/pci/controller/dwc/pcie-eswin.c @@ -84,8 +84,7 @@ static int eswin_pcie_start_link(struct dw_pcie *pci) =20 static bool eswin_pcie_link_up(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u16 val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + u16 val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); =20 return val & PCI_EXP_LNKSTA_DLLLA; } --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 596D772603; Sat, 30 May 2026 15:36:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155389; cv=none; b=Ixf+tINAVWmUq4ToEUMHqIqFuFNReIDafaeSUAA3KvKlt2lthARL/oAwVT+l9EC3rxJPiYUjzBcvGqmrWo7Eon5e540v5h6FT9dDFKNFQWwkf7K/y963GbBNTVKnH/vq66uPr9S0ESagUOjr8ET3hO8BdJi1ssUFLK/CehAG14I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155389; c=relaxed/simple; bh=KFNywJY77A37y9C7nyuYTxEOSJ8mD3bMQuXrniAKLF0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZBeDGKhpnPH6qR64Ubc3S3KidnMmxxs/l5nKILVw+/CljsDBsm9/aJ61fJto4WeQPLfTbN+k3udXz5UiZoz1kxCGH370sOzWJyuEcnzdTJe7FLowlTft8ETU9/a/9+cp5718zwMASGmVrNHvo/14m1/BQCkqf6WJeTUbyRDpkS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=m/NAqZd2; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="m/NAqZd2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Ff B7GrmVp8WAki9+UnmVSGGvKtwSZ9GLa+Vb7MYQ6is=; b=m/NAqZd21P60aUUhbU Pu5nR8SfSePKBWaGuAsf2PghhTDjRFvXtkX+E+YUktmaNorVAt6w0R0QfMUHy67k x2QY94Cav3EjXHTc5zTiJMk+JTK2iayw+yYnufWEA2M/IWbPutByMtw7xMbZX+xa aNsJiizteQSMnBMHDhr86QnYE= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDXxtTBAhtqVqDdFA--.47036S2; Sat, 30 May 2026 23:31:16 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 08/16] PCI: dwc: fu740: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:53 +0800 Message-Id: <20260530153101.695580-9-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDXxtTBAhtqVqDdFA--.47036S2 X-Coremail-Antispam: 1Uf129KBjvdXoW7Xw1UXr4rWw1rCr47Xr13urg_yoWDArbE9a 4UGFs7ArWUKryFy3W2k3yfJF97Za47WF1UKa1rtFW3ZF97Xw18Wr9FqFyDJF48W34DXF1x JF4qvF40ka9rAjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7VUUec_7UUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AQTtmobAsQ6cwAA3z Content-Type: text/plain; charset="utf-8" This callback is invoked after dw_pcie_host_init() has cached the offset, so we can use pci->pcie_cap directly. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-fu740, the call chain is: static const struct dw_pcie_ops dw_pcie_ops =3D { .start_link =3D fu740_pcie_start_link, }; fu740_pcie_start_link() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-fu740.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controll= er/dwc/pcie-fu740.c index d0a34f680397..72c0a6316fff 100644 --- a/drivers/pci/controller/dwc/pcie-fu740.c +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -178,7 +178,7 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) { struct device *dev =3D pci->dev; struct fu740_pcie *afp =3D dev_get_drvdata(dev); - u8 cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 cap_exp =3D pci->pcie_cap; int ret; u32 orig, tmp; =20 --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F34A914ABE; Sat, 30 May 2026 15:33:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155202; cv=none; b=fgtCEijYFJF4sFsfXQ+GZbEMHKIMlbWXXYocgxg2A24oayYE/5BhU2vvFHMybOgXbmR/rMO2XyAnH42kyKbzxS+NbP7v+CvFpBTKYAaakDF7+D4JL2c1KOUjZDdBm9noXdNtwkoBAVZ6ebFLx1bicSjFxapYLFKVhqt1NX/cgRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155202; c=relaxed/simple; bh=pnXKQBJq6earf0edjrVkf+cqRAKnG9E6poxbRczunzc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cnxVaOpaZ3QZquC+Ga0whf6vFA8dZ26o5uPAhr4z0zBPw6S9ajOgjALSDuId0DcP4G+XfQa7RYz9Er2hSE7K9ja4G+a0IqpEXI1V8gdz7CZbabdrNy2yUcDluxlpJHE6S+syO1bM8imFdUOYsoxTK1oM9q2/eHpM9r1qMfPOjOg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=bZ02ICVu; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="bZ02ICVu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=xR XrUPtqRKYJ1Qp5pLJQlLNj/mO3wbu1mld9QcgpMXw=; b=bZ02ICVurB31mEIusJ famXGFv5H6oyW1WhOqqp+R3/NKfDekPYpHglyd9mvlYt2H00dh3e4GJ07yR3NBCT PA1wOuLVoRggcWiSdqO2sIoXX7YFSCmA78JUq7rs1dLkXQ7KCGr1NiCMGc86pNSC 5v7icpkAh531sLoc5vfTsxELg= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDXxtTBAhtqVqDdFA--.47036S3; Sat, 30 May 2026 23:31:17 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 09/16] PCI: dwc: intel-gw: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:54 +0800 Message-Id: <20260530153101.695580-10-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDXxtTBAhtqVqDdFA--.47036S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7GF1xWrW8JrykKFy3Cr1fCrg_yoW8JF17pa y5Xr1jyFn5XF429F17A3Z8WF1Yy3ZxA3s3Ga97Gw1SvF9rCryDK3yvkryFyF9rGrW0vr1a kw1Utw17WrnxJrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pR5DGOUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wUTtmobAsUw2AAA3V Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() calls .init before caching the offset, so inside .init we must call dw_pcie_get_pcie_cap() to obtain the offset (hardware is already enabled). The helper will cache the result for later use. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-intel-gw, the call chain is: static const struct dw_pcie_host_ops intel_pcie_dw_ops =3D { .init =3D intel_pcie_rc_init, }; intel_pcie_rc_init() -> intel_pcie_host_setup() -> intel_pcie_link_setup() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index 2674cd376f49..568b2634d08d 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -120,7 +120,7 @@ static void intel_pcie_ltssm_disable(struct intel_pcie = *pcie) static void intel_pcie_link_setup(struct intel_pcie *pcie) { u32 val; - u8 offset =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); + u8 offset =3D dw_pcie_get_pcie_cap(&pcie->pci); =20 val =3D pcie_rc_cfg_rd(pcie, offset + PCI_EXP_LNKCTL); =20 --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8387932E68D; Sat, 30 May 2026 15:40:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155645; cv=none; b=J6LsjsnidK5ZxGhG5gH0pxWGJmS4WwzBCUwFq+KG1KvSjzIxpzIE8j2LeY08hHwCmwp/4h2rquZG3SmbJ+ihYa5RPgqfcpAf/DDRQvLi6fVpuw4TMlpmYgPdRVN+LmY5LBWgOM1HeuTUNEN8h4NzYQ1skLCAXFHYF+qz6dvCaQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155645; c=relaxed/simple; bh=grGdtXOwD1+VjoAQoMk0QP1EWIxmg313YgHNMTrVNy8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XOS4pHIbfte+0Iyl+A+6oKD9Lte95c2tV5UzV/0DN7KNbxa8z90/FXQMFM1849XjKuC5ZZ73i5YtXlfXZNRLv/wE/vZyUeZu2o2TyhEexF57+n7auZvam+OFZi35NZyO5Am7oAL+LJG4DK+u3cYXXIXHKJltTRT0sh0Lh2AUy3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=f300qt3g; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="f300qt3g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=YQ KiS1Zc2ks7okKcTAWY33gQ3mSdya0KjH2tZs/3Xws=; b=f300qt3gZrvnVaMrfM GuMeGnCoMPu/G3pu97r3Sg6knoV5ITeGpMhUrMIkFIhK/4QPP79lSRJ1A1eeSE7n g8NUPqI4NqYhwOqYd7ZFc92qUhrEjgQW2EFMQqJovZAHPOTQLRWSzB/XNjjWnECO b3FihsjO1Gks4K1qoH4fnMyFc= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDXxtTBAhtqVqDdFA--.47036S4; Sat, 30 May 2026 23:31:18 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 10/16] PCI: dwc: qcom-ep: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:55 +0800 Message-Id: <20260530153101.695580-11-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDXxtTBAhtqVqDdFA--.47036S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7uFy7Cr4rAryUWry5WFWDXFb_yoW5Jr1kpa s0qrsIyr18Jr48XrsFkan8XrnrWrn8Ary7Ja97KF1SvFy2v3y7Ja1jyryftFn7GF47Kry5 Cr1ktrWfu3W3tFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pR8nY7UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AYTtmobAsY6mAAA3Y Content-Type: text/plain; charset="utf-8" dw_pcie_ep_init() calls ep->ops->pre_init() (enables hardware) and then dw_pcie_get_pcie_cap() to cache the offset. Therefore, the IRQ handlers run after the cache is populated, so they can safely use pci->pcie_cap directly. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-qcom-ep, dw_pcie_find_capability() appears in: qcom_pcie_ep_probe() -> dw_pcie_ep_init() -> qcom_pcie_ep_enable_irq_resources() -> qcom_pcie_ep_global_irq_thread() -> qcom_pcie_ep_icc_update() -> dw_pcie_find_capability() -> qcom_pcie_ep_perst_irq_thread() -> qcom_pcie_perst_deassert() -> offset =3D dw_pcie_find_capability() (called twice) --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 56184e6ca6e6..0471f96d3c78 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -307,15 +307,13 @@ static void qcom_pcie_dw_write_dbi2(struct dw_pcie *p= ci, void __iomem *base, static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci =3D &pcie_ep->pci; - u32 offset, status; - int speed, width; - int ret; + int speed, width, ret; + u32 status; =20 if (!pcie_ep->icc_mem) return; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + status =3D readw(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKSTA); =20 speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, status); @@ -492,13 +490,12 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) dw_pcie_dbi_ro_wr_en(pci); =20 /* Set the L0s Exit Latency to 2us-4us =3D 0x6 */ - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D pci->pcie_cap; val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); FIELD_MODIFY(PCI_EXP_LNKCAP_L0SEL, &val, 0x6); dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); =20 /* Set the L1 Exit Latency to be 32us-64 us =3D 0x6 */ - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); FIELD_MODIFY(PCI_EXP_LNKCAP_L1EL, &val, 0x6); dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F31C3382F7; Sat, 30 May 2026 15:31:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155108; cv=none; b=bVEU3Qy481vWuSwyYkKn0TTj5LRt/4WotEFgE9KG9qJ08TCuw6uHIJ4/833SegyIFM4ZlZ+aMZiiReDwzpeWXgMqD70vcODQCBFdGGl7cnYI2+MRcRgCeX7f7EZvn4t92P9TLcNe6/kXZh5yoFUS6Y7tN1Nk/4J/QdhO78pT7Ds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155108; c=relaxed/simple; bh=32M/PdsAFc/9DPQK2sFcE+ASvTTCe66eK5B3WyZp7/4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Riv0QKfEMJ2GrzAEnlNaebYmLbXfTLoC+FLKtA2YyOyjPjqdpNaXN1oRQOKYVUiesnMrZl52HRCFjlvwclzeU+Y0pgC6NPv2Fmu749XrqS5xxbGxyHUvHimD5XPbYiqoKTO7uvccKFUxiqsBu12gMSfWJ2DBHDVAtsC4/8tdalI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Xs2/nOCb; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Xs2/nOCb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Tu ra2KdjQW2HVx3hWRZaEz0M07jdxiudkOkLoIpL7hg=; b=Xs2/nOCbi7kYCh5SeX 0FlHHHNZ+Vv43rivL3380Bwm6EuO4t2622wWPeozIGAVvkHO7s4l9gRf6SKxjO28 ubRS+cYKZWnhuVFWE/wQcOvpeIwUIvaLIxTFMF2a7O4oPrqZDIFTDrMCNGvlZHRW yo924VGLZniLfgLz4YYlulwVA= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDXxtTBAhtqVqDdFA--.47036S5; Sat, 30 May 2026 23:31:18 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 11/16] PCI: dwc: qcom: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:56 +0800 Message-Id: <20260530153101.695580-12-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDXxtTBAhtqVqDdFA--.47036S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxCF4xJFWUKFWfWFyfXr47Jwb_yoWrCw4Dpa s0vrn0yF45Jr48WFnFyFZ3Xr1agrnxArW7Aa97Kr1SqF9xtryUGa1jyrySyFn3GFZrtFy7 Gry8tryUX3Wrtr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ptYLm3UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAYTtmobAsZ6-QAA3V Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() caches the offset after .init, so .post_init callbacks and later functions (.link_up, icc_opp_update) can use pci->pcie_cap directly. For .init itself, we must call dw_pcie_get_pcie_cap() inside qcom_pcie_host_init() to obtain the offset (hardware is already enabled). Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-qcom, dw_pcie_find_capability() appears in multiple call chains: static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .init =3D qcom_pcie_host_init, }; qcom_pcie_host_init() -> qcom_pcie_clear_aspm_l0s() -> dw_pcie_find_capability() static const struct qcom_pcie_ops ops_* =3D { .post_init =3D qcom_pcie_post_init_*, }; qcom_pcie_post_init_*() -> qcom_pcie_set_slot_nccs() (for many versions) -> dw_pcie_find_capability() -> For 2_3_3 and 2_9_0: also calls dw_pcie_find_capability() directly static const struct dw_pcie_ops dw_pcie_ops =3D { .link_up =3D qcom_pcie_link_up, }; qcom_pcie_link_up() -> dw_pcie_find_capability() qcom_pcie_probe() -> dw_pcie_host_init() -> qcom_pcie_icc_opp_update() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-qcom.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 11fc60489892..80783353d539 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -341,13 +341,13 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) { struct qcom_pcie *pcie =3D to_qcom_pcie(pci); - u16 offset; + u8 offset; u32 val; =20 if (!pcie->cfg->no_l0s) return; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); =20 dw_pcie_dbi_ro_wr_en(pci); =20 @@ -360,7 +360,6 @@ static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pc= i) =20 static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; =20 dw_pcie_dbi_ro_wr_en(pci); @@ -370,9 +369,9 @@ static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci) * notifications for the Hot-Plug commands. So set the NCCS field to * avoid waiting for the completions. */ - val =3D readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); + val =3D readl(pci->dbi_base + pci->pcie_cap + PCI_EXP_SLTCAP); val |=3D PCI_EXP_SLTCAP_NCCS; - writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); + writel(val, pci->dbi_base + pci->pcie_cap + PCI_EXP_SLTCAP); =20 dw_pcie_dbi_ro_wr_dis(pci); } @@ -935,7 +934,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) { struct dw_pcie *pci =3D pcie->pci; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 val; =20 /* Force PHY out of lowest power state */ @@ -1257,7 +1256,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pci= e) static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) { struct dw_pcie *pci =3D pcie->pci; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 val; int i; =20 @@ -1303,8 +1302,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) =20 static bool qcom_pcie_link_up(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u16 val =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + u16 val =3D readw(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKSTA); =20 return val & PCI_EXP_LNKSTA_DLLLA; } @@ -1663,15 +1661,14 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pci= e) =20 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) { - u32 offset, status, width, speed; + u32 status, width, speed; struct dw_pcie *pci =3D pcie->pci; struct dev_pm_opp_key key =3D {}; unsigned long freq_kbps; struct dev_pm_opp *opp; int ret, freq_mbps; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + status =3D readw(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKSTA); =20 /* Only update constraints if link is up. */ if (!(status & PCI_EXP_LNKSTA_DLLLA)) --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E88E262809; Sat, 30 May 2026 15:32:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155157; cv=none; b=m9OhItjwpEY1seEqA9u8Y0sq+kdLwPcVRfNuFzvH+B+H/ZuB+Y8HgQMLQAt4u3vcbZ2c6fJFTVHQvXuQSb5puBexf043q0v7awCH/45iKW5p+XiVonIlK61BGOsJcga9cN7ytJOZ755TWyxoRqey49a+TBKIe2VY8tzPF98FyJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155157; c=relaxed/simple; bh=GZRRdIebw/R7rBRANI0WHKYmQLKIYwinmBYXNPBBtRU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tdh2+qJrmGxyGHtPP2KI4vF1kI1lHdfctA5vYLiu1Q2BAdJmHDH1TKE7b5FGLlIgs6K0mN5yMB29nl3lUmweynZWqUQIQLafMJAzqVGQhUhzztW/f7BwFSpYKp3zq9mmSr9L1mlaXEqhXSng9T4RaR5D/+s0uIBSxwSFLfgqldU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=FcWfnuTS; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="FcWfnuTS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=mA 809+5dKgIh5hEU/u2sEYn54hA7ngIexLFJ1RFII/4=; b=FcWfnuTSkXszkV2tSq an3ds2TRzXXeeip9zCL5sALjeMFASs8H7zhoo+4PPB2T39ba5u8lKyXjPzCNzpm1 v4XdQqiIGIOFvUV1mb2kDD/5m7SDmjqdAvIfgOR1McKYeqbKUrPjeRRGqNqZ5xUY UzEpZM7YTUiigkcTI/4jTXkx4= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDXxtTBAhtqVqDdFA--.47036S6; Sat, 30 May 2026 23:31:19 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 12/16] PCI: dwc: sophgo: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:57 +0800 Message-Id: <20260530153101.695580-13-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDXxtTBAhtqVqDdFA--.47036S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7CF48WFW5tr1rXryrCry3Arb_yoW8Jw1kpa y5Zr4FkF4rJF4Yqa1Iy3WkZr1Yq3sxAryxJa93Gw4av34akFyDJw45tFyYgFnrGFWjyry3 KFn8t3W3WF98AwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRmhFxUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAcTtmobAsd7FQAA38 Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() calls .init before caching, so we must call dw_pcie_get_pcie_cap() inside .init. The hardware is already enabled by the driver's own initialization before this point. The helper will cache the offset and avoid redundant searches. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-sophgo, the call chain is: static const struct dw_pcie_host_ops sophgo_pcie_host_ops =3D { .init =3D sophgo_pcie_host_init, }; sophgo_pcie_host_init() -> sophgo_pcie_disable_l0s_l1() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-sophgo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-sophgo.c b/drivers/pci/control= ler/dwc/pcie-sophgo.c index 044088898819..39703d2b7b5f 100644 --- a/drivers/pci/controller/dwc/pcie-sophgo.c +++ b/drivers/pci/controller/dwc/pcie-sophgo.c @@ -164,9 +164,10 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp *= pp) static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u32 offset, val; + u8 offset; + u32 val; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); =20 dw_pcie_dbi_ro_wr_en(pci); =20 --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C04CC29ACC5; Sat, 30 May 2026 15:34:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155249; cv=none; b=RBAUqR5EqJjs2B1SOeTSXMyFUJRhbFNHVLsEkBUu3G+0C16ZaINiZznl1ifjISoifmDhKRLkMgfk8PMianVyuVA2l/XfKPnylGIn3ci+KjIKGSLF/EigY8Gm+uFh2pQp285VlfH2RX6/OB83b/a1mV/9MXUV9pWZjXFLhPetZ8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155249; c=relaxed/simple; bh=EMeMc0iFRqLpL/KQvt8hykCRj2VOWWvM4KBs+phGhsM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MD5vDZ+G4IfPeyMiCkHFxbT+H3AU8MNQkylcJhsylwppJUZjAX7jfYw71YUPyws0V5Fsmt8SnCKZ9zryaLSL0vj3+NSCXJZc/8mLeNRA2lqLV2yvD5jg5Pnu/a5BEtpK7XLMS/b2o655cWkl7M2fkSe7CN3RaINr48bJyoDRyQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=RurMCD4Z; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="RurMCD4Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=17 vIuTQTz9uvJnUYcBHWYZyruRUvjU3S7yCS0jwplyM=; b=RurMCD4ZVZVttgWP95 9yKIEkUa+rWBfDnyUJQ05VFTBeEeDFpuJOZc7ewnOSqheotV12FfAqIhJrnQhKjM U9ePatb44xOkmE0lm40QnMl+v7kZPsmkq1TimEFm9D2B9uCIZdyL8aeVjHd0h07X XXaJ4VdF+LaX6FEgmoOvwe1pk= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDXxtTBAhtqVqDdFA--.47036S7; Sat, 30 May 2026 23:31:19 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 13/16] PCI: dwc: spacemit-k1: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:58 +0800 Message-Id: <20260530153101.695580-14-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDXxtTBAhtqVqDdFA--.47036S7 X-Coremail-Antispam: 1Uf129KBjvdXoWrKr1fWF1UGr15JF4rXr1kZrb_yoWkCrgE9F y3Jan7JrW5CF93C3Zayw1aqF9Yy347X3Wj9a1fKF9xZ3Z2q345XrWDZFWkAa18GrWkXr93 Gw1qvF1rAayUKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRivtC7UUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AgUt2obAsg65wAA3h Content-Type: text/plain; charset="utf-8" Because .init runs before core caching, we call dw_pcie_get_pcie_cap() inside k1_pcie_disable_aspm_l1() to get the capability base, then add PCI_EXP_LNKCAP. Hardware is already enabled at this point. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-spacemit-k1, the call chain is: static const struct dw_pcie_host_ops k1_pcie_host_ops =3D { .init =3D k1_pcie_init, }; k1_pcie_init() -> k1_pcie_disable_aspm_l1() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/co= ntroller/dwc/pcie-spacemit-k1.c index be20a520255b..65114060311e 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -117,7 +117,7 @@ static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) u8 offset; u32 val; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); offset +=3D PCI_EXP_LNKCAP; =20 dw_pcie_dbi_ro_wr_en(pci); --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from mail-proxy25256.mail.163.com (mail-proxy25256.mail.163.com [103.129.252.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90CA830674D; Sat, 30 May 2026 15:53:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.129.252.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780156405; cv=none; b=Teb/UtfutI8yI180gSh7Utnx+OLofgct2wtemKEX+bggu6i2dRPu3CpKv43Ppdod9iJiEjsYWPP3E/VQjFRJNTlAf6hqbFeIn3sGG5V6NDKzZqdsYK0JIKpqimhQW0hKx3Ez+ztL/S1oHOadyooOi1i0dA73LyNe8p0v3q+H9ls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780156405; c=relaxed/simple; bh=lUMJBA5oUnnTXQALxg7z88nPxjG8v70kIBk50sr5d1k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N30dsHM2kVPvil7g1rlym0ac4uB+KtkvQnlHvMTB4D/HP27aJXR5HT55CeHH1joRto24KlVoPtgSjjTVJ+TRViO6GUsmV9eO/CcgBFymOSP8s6wvOXZBEKHuTV+0J86OqnhojFu/vy1adNrvUdfkfhn0hK3Psn/LpSrbiqY8h1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Ie2fyZmw; arc=none smtp.client-ip=103.129.252.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Ie2fyZmw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=/i OTdtu/aTwGdJUNHIqJwX0fu5L6Cd4Ns7bFgW3B/CE=; b=Ie2fyZmwHRchW0mM3Z c5uqFeKgNeypIeGngV++7kvMTqHvybFfpsyeJI29xvf7VdPuO1MXVsdkU8g+EgMH I0IlKzP8MljJLZUAgjAn+g99A51EtLdyR/JaL3PYUoikFSQCmfiOJ79FHkIDggc7 7so96tXQBZmKSKnNOzpNaaxD4= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDXxtTBAhtqVqDdFA--.47036S8; Sat, 30 May 2026 23:31:20 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 14/16] PCI: dwc: spear13xx: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:30:59 +0800 Message-Id: <20260530153101.695580-15-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDXxtTBAhtqVqDdFA--.47036S8 X-Coremail-Antispam: 1Uf129KBjvJXoW7GF1DKr1kCFyruF4ftrW8Zwb_yoW8JF1rpa 9xXry2yF1rJr4aqr42v3Z8Xr15t3s8urWqq39akw1SvF17CryUtrW5t34YyF13WFWqyry3 Kr1Uta4xWF98Jw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRmhFxUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AgUt2obAsg7AgAA3F Content-Type: text/plain; charset="utf-8" Inside .init we must call dw_pcie_get_pcie_cap() to obtain the offset, because the core has not yet cached it. The hardware is already enabled by the driver's own initialization before this point. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-spear13xx, the call chain is: static const struct dw_pcie_host_ops spear13xx_pcie_host_ops =3D { .init =3D spear13xx_pcie_host_init, }; spear13xx_pcie_host_init() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/cont= roller/dwc/pcie-spear13xx.c index 01794a9d3ad2..6e4c11b497d4 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -122,7 +122,7 @@ static int spear13xx_pcie_host_init(struct dw_pcie_rp *= pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct spear13xx_pcie *spear13xx_pcie =3D to_spear13xx_pcie(pci); - u32 exp_cap_off =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 exp_cap_off =3D dw_pcie_get_pcie_cap(pci); u32 val; =20 spear13xx_pcie->app_base =3D pci->dbi_base + 0x2000; --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4510914ABE; Sat, 30 May 2026 15:33:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155207; cv=none; b=tIIQrqVo90anSOodnS1A0/5yYD4/MH3gdyvmxCpMrAdXYx9sl0xmlwN6YxoqWBS77ZtpGhCn0LzZlrLLeJHrBh2/+/bKn5BoKuaq+bvPnNCIgkM4XCeuFjB8A6e2wAPIKDAeUkQrV5DM/k4R+F1H523u6g4t7hYYetPIRAmMKcI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155207; c=relaxed/simple; bh=6FHXvjev7Gd8QIJ6TC6cZHqJAh/folx2I9bLZ1sWT1o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=D2SBNRUX/5X7wL0KpvpnWJC/BYEvD7TDxM8V+H0C62uZpgRyHbZe5Q0SrYplHRsZGb5faCS3vCZu3tuZpOw9vlJlXkD4g3fkScPAcjyD8kCMVIjO545j5KCqIZUEXPKBPPSrglrPO2aBTkAZoN0AJNEOBReaIjwG61NvwcpO6fw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=QdlMK/5N; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="QdlMK/5N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=7N jckmR/hN8kDZXFriSmoFWbpgDw7fbuJlZj3KiCUGU=; b=QdlMK/5NSu3mn4Jv6w JWNSFhSJn9cGKxRHg/27nZEP0PsgFq79AE74CQXdl9a0FEpjl9xqMlnTNe6JHoGO uZpXo8I5Gqldw+1wFruDrxCiglpftX3v/2mbOC25DUUW28cbGPPb5nznJI17XFz1 U9VGL24dPJqJhUnPInB72+ZsU= Received: from zhb.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDXxtTBAhtqVqDdFA--.47036S9; Sat, 30 May 2026 23:31:21 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 15/16] PCI: dwc: tegra194: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:31:00 +0800 Message-Id: <20260530153101.695580-16-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDXxtTBAhtqVqDdFA--.47036S9 X-Coremail-Antispam: 1Uf129KBjvJXoW7trWfJrW7Kw1xGw1fZw4kXrb_yoW8tFy5pa yrXrWFkr1UJr4aqFsrAan8ZF15t3sIyrW7Gwsagw4aqr17C347WwsYk3y5tF17CFZFyryU Cr1UtFy7Gr15JwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRmhFxUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAkUt2obAsl7YQAA3O Content-Type: text/plain; charset="utf-8" In host mode: tegra_pcie_dw_host_init() runs inside .start_link, which is called after dw_pcie_host_init() has cached the offset. However, the driver's own initialization already enables hardware, so calling dw_pcie_get_pcie_cap() is safe and will return the cached value. In endpoint mode: pex_ep_event_pex_rst_deassert() runs before dw_pcie_ep_init(), but the driver has already enabled hardware. dw_pcie_get_pcie_cap() will perform the DBI read and cache the offset. Thus, the private pcie_cap_base is always valid and can still be used for register accesses. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-tegra194, dw_pcie_find_capability() appears in: static const struct dw_pcie_ops tegra_dw_pcie_ops =3D { .start_link =3D tegra_pcie_dw_start_link, }; tegra_pcie_dw_start_link() -> tegra_pcie_dw_host_init() -> dw_pcie_find_capability() tegra_pcie_dw_probe() case DW_PCIE_EP_TYPE: tegra_pcie_config_ep() -> pex_ep_event_pex_rst_deassert() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 795cef5a915d..bf482bc66a92 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -905,8 +905,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) pp->bridge->ops =3D &tegra_pci_ops; =20 if (!pcie->pcie_cap_base) - pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + pcie->pcie_cap_base =3D dw_pcie_get_pcie_cap(pci); =20 val =3D dw_pcie_readl_dbi(pci, PCI_IO_BASE); val &=3D ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); @@ -1889,8 +1888,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegr= a_pcie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); } =20 - pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + pcie->pcie_cap_base =3D dw_pcie_get_pcie_cap(pci); =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { --=20 2.34.1 From nobody Mon Jun 8 09:49:41 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13EC52C029D; Sat, 30 May 2026 15:31:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155106; cv=none; b=Dq4UqrMTYXYpuX90+K12V6q004raBiT0Zd4+IOPyfpfn/uWa1PBnAF28+eSTuLTPNO20NC2fzFgqBm0hrwVxlsAt/CpxdT5KMRf4hpcw8pIXMkgHaF7Vm4yKjIAvE5XyK0AMNAHyNH/6pRmOt7u8y4IsEUhXeF8pkxN/3fKVdFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780155106; c=relaxed/simple; bh=66IBhF1pQmHCc5Bn86cYjQ39VKbzO0j4snPG+BTKAT0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Oggn26Tb5+bO5O1lAe6XkNJWK84b5ScQoxYtsztg8h7gxqTvRlmvf/H4bAS+q9rXZ2HJn1TbRzDQbJI3iPeWyBAW6quSbi+A7X3DgVCz0gP4uk3FLiAidvBqfLvj9afxaQlDzBBb/Z3fBmCbThVkBiEB1hMwtcM1g7UCH730G7k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=OdbPTRUj; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="OdbPTRUj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=VX L2XKRY5F3qPW2VboJTa9SPw1RX8rEnzJV3c1g8W44=; b=OdbPTRUjqvSt9jCAW8 uupSQCWrQrsDTWqnjOFkTdtYUB72XpNAhkq8EEkiqWk3D5KhHe9FJC1MaRo2SXN7 PQItcQk6144y3/eYwLKsYPZmCcOVJwvgXf4ppNoANiJQcfuToGiCHzzLEqyJD6uy JzswNO3J/cb9s0r1JYkkjkTSM= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wD3Hm7MAhtqXFHjAQ--.23733S2; Sat, 30 May 2026 23:31:25 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com, a-garg7@ti.com Cc: robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 16/16] PCI: dwc: ultrarisc: Use cached PCIe capability offset Date: Sat, 30 May 2026 23:31:01 +0800 Message-Id: <20260530153101.695580-17-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260530153101.695580-1-18255117159@163.com> References: <20260530153101.695580-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3Hm7MAhtqXFHjAQ--.23733S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZFy7CF43CF1xGry8JFy7KFg_yoW8Grykpa y3WryjyF1Dtr4YvFs2v3WDXF13tFnxAr9xJanrGrnIvF1akrWUJ390k34rtFn7GFWUKryY kr1YyFy5Ga4rtwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUbzVUUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxA0VuGobAs172wAA36 Content-Type: text/plain; charset="utf-8" Inside .init we call dw_pcie_get_pcie_cap() to obtain the offset, because the core has not yet cached it. Hardware is already enabled by the driver before this point. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-ultrarisc, the call chain is: static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops =3D { .init =3D ultrarisc_pcie_host_init, }; ultrarisc_pcie_host_init() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-ultrarisc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/cont= roller/dwc/pcie-ultrarisc.c index 6ee661ceff67..3f6e3ab0aa69 100644 --- a/drivers/pci/controller/dwc/pcie-ultrarisc.c +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c @@ -49,7 +49,7 @@ static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); =20 - cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + cap_exp =3D dw_pcie_get_pcie_cap(pci); val =3D dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); --=20 2.34.1