From nobody Mon Jun 8 09:48:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57433239E60; Sat, 30 May 2026 02:07:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780106831; cv=none; b=Bsa/eBZ2v3Z8d+FK9pRM9SdtA3hcTslJvAUEVvFaLVzEYfm4mt1m2KklpFG8kNq5lxZ+BqD4QOGvP6wLBmFKlCBhGpUd4JYEWd/sq8+9jPk8yc7O59stkeCnMwS2+jFdR93ZF2pZNavWijYoUQNTrBjFnzQn3sJ47gYqewoTZ2c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780106831; c=relaxed/simple; bh=1wcyuj7dq4hdewVAFqTdvs1tFjn6zSc7/qBQJmpq48E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PT3MMeno7VoOHrS56adyaGfYkUIbn9sEcXSx+Ub/jMrQxkobhFTx0n87A+Mkg+EccxQXPmmJpnSL8Ds6EBUyD5yF1c7Q011U8du/MeH5ItYHvY0ZHF+pknjQBW1Wkehg7yCQC4/KCd97ETgbccbP9U2GA2LlvtV0bX9EWZkCvSA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BGLnoD6e; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BGLnoD6e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8D911F00899; Sat, 30 May 2026 02:07:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780106830; bh=0z/PWEVZMcEl2xNn3u/IQ3QAWI3jmJkJOckw6jHCQjM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BGLnoD6eLC69jbuIV+wkmHkKT3tp93PtLoujAf56mhIct2VPZxw4FhMWcurDGcnaR 19Mf8H7ralAwQi8qtteaKfeOyI6mcHEuo7Cu2i8jFvtavA9PLh6QId9upOucaXHg2l hBr79CLhTtaN0GENQ9SKyega85KBUCI9SuHLwL8bRZL75MvQ0QVmPiiOw5jX/UBGZA eGAP0CM0gvEeeBskQzpMK1FIkaWKKylq1lUY5YMDOD6BNwBfbEiRDZZYOzZxy9LoJb +jr8tRP4MrEOFZQG//0DbeWwTgjwKZOwsIUqqYD6JJqpd+PXULqakL1SWF/+4YowD4 9ju+GYLJPDbUw== From: Eric Biggers To: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Om Prakash Singh , Bjorn Andersson , Neil Armstrong , linux-arm-msm@vger.kernel.org, Olivia Mackall , Eric Biggers , stable@vger.kernel.org Subject: [PATCH 1/4] crypto: qcom-rng - Enable clock in hwrng case Date: Fri, 29 May 2026 19:03:29 -0700 Message-ID: <20260530020332.143058-2-ebiggers@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260530020332.143058-1-ebiggers@kernel.org> References: <20260530020332.143058-1-ebiggers@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix qcom-rng.c to enable the clock before accessing the hardware. Fixes: f29cd5bb64c2 ("crypto: qcom-rng - Add hw_random interface support") Cc: stable@vger.kernel.org Signed-off-by: Eric Biggers Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/crypto/qcom-rng.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c index 150e5802e351..f31a7fe07ba7 100644 --- a/drivers/crypto/qcom-rng.c +++ b/drivers/crypto/qcom-rng.c @@ -111,17 +111,31 @@ static int qcom_rng_seed(struct crypto_rng *tfm, cons= t u8 *seed, unsigned int slen) { return 0; } =20 +static int qcom_hwrng_init(struct hwrng *hwrng) +{ + struct qcom_rng *qrng =3D container_of(hwrng, struct qcom_rng, hwrng); + + return clk_prepare_enable(qrng->clk); +} + static int qcom_hwrng_read(struct hwrng *hwrng, void *data, size_t max, bo= ol wait) { struct qcom_rng *qrng =3D container_of(hwrng, struct qcom_rng, hwrng); =20 return qcom_rng_read(qrng, data, max); } =20 +static void qcom_hwrng_cleanup(struct hwrng *hwrng) +{ + struct qcom_rng *qrng =3D container_of(hwrng, struct qcom_rng, hwrng); + + clk_disable_unprepare(qrng->clk); +} + static int qcom_rng_enable(struct qcom_rng *rng) { u32 val; int ret; =20 @@ -206,11 +220,13 @@ static int qcom_rng_probe(struct platform_device *pde= v) return ret; } =20 if (rng->match_data->hwrng_support) { rng->hwrng.name =3D "qcom_hwrng"; + rng->hwrng.init =3D qcom_hwrng_init; rng->hwrng.read =3D qcom_hwrng_read; + rng->hwrng.cleanup =3D qcom_hwrng_cleanup; rng->hwrng.quality =3D QCOM_TRNG_QUALITY; ret =3D devm_hwrng_register(&pdev->dev, &rng->hwrng); if (ret) { dev_err(&pdev->dev, "Register hwrng failed: %d\n", ret); qcom_rng_dev =3D NULL; --=20 2.54.0 From nobody Mon Jun 8 09:48:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF59D2C21C4; Sat, 30 May 2026 02:07:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780106831; cv=none; b=mNv8eDgfbGuZIVdwvwflD9rDf4HtxRJATYNqEy5+CMbimxNrq2R/S+8fnpd01EG28efFFgkcXQT9SUIs+NwqnREk5btgVkuIZfIqLetIwuhK/X58ZWMidq9euiAVkraWDaWUtAIJERYgpZfYu8RK1KREUxa79pn1CRN+P7HBSB4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780106831; c=relaxed/simple; bh=VYOIDtqd4ucDLDzEURmfG+r+wD9zt0qWUndPEy33i3A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R+uz1EgNsjumBAUmh0Q+T6XH4d0mpoDIimBDZpt4FgkZhpEKD/i2J/rLtPIFhgVlvLRa6CJeQpqo6FdcqROcyjGc1ZHVtXkq2oiFwpY8Qm/ZtYw3LqvvzB/M3VLF4NYx2ZUQ3z73GCfBOXUNeo6OsMEvAaZglKUG+Ojm5jqIz8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PdrX/Q8n; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PdrX/Q8n" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 572761F0089A; Sat, 30 May 2026 02:07:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780106830; bh=BAk+/NT38mB/njzldbjiOKe+YbzIHJjolZLkTM2lZpo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=PdrX/Q8n46fAd3ekIrXqV9vvz0fL8KXJuZmSPCng+qVdyuDdRPb20ntsVZsEomczR H7j1k5YByEll9Q1lj13Sp1c46a/3+DsZpZkrM4EY2oDKN/dG3e4rB/hQ2fJevFvfEC DKdUBiZhEIVbkZM5bTw0FdpHEwqR6uv+SJlWlcfWYwhqIGzWaXutnh9QXRvpuwuCrC OE5SisJS+68l4efImuJeDIdH/5D7qJ2UnS59RESjqRDYw8h36Oupb/ONVvi7EfC0W6 JjmWqkS1paaAWdZ8nYo/Pn4KNstmdyfh5HTyIaeKbJJMvjwnJmq3IFXPVaGuPDfPVv hW4oo/Zjo42vw== From: Eric Biggers To: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Om Prakash Singh , Bjorn Andersson , Neil Armstrong , linux-arm-msm@vger.kernel.org, Olivia Mackall , Eric Biggers , stable@vger.kernel.org Subject: [PATCH 2/4] crypto: qcom-rng - Allow zero as a random number Date: Fri, 29 May 2026 19:03:30 -0700 Message-ID: <20260530020332.143058-3-ebiggers@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260530020332.143058-1-ebiggers@kernel.org> References: <20260530020332.143058-1-ebiggers@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Zero is a valid random number and needs to be allowed. Otherwise the output is distinguishable from random. Fixes: f29cd5bb64c2 ("crypto: qcom-rng - Add hw_random interface support") Cc: stable@vger.kernel.org Signed-off-by: Eric Biggers Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/crypto/qcom-rng.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c index f31a7fe07ba7..b7f3b9695dac 100644 --- a/drivers/crypto/qcom-rng.c +++ b/drivers/crypto/qcom-rng.c @@ -63,13 +63,10 @@ static int qcom_rng_read(struct qcom_rng *rng, u8 *data= , unsigned int max) 200, 10000); if (ret) return ret; =20 val =3D readl_relaxed(rng->base + PRNG_DATA_OUT); - if (!val) - return -EINVAL; - if ((max - currsize) >=3D WORD_SZ) { memcpy(data, &val, WORD_SZ); data +=3D WORD_SZ; currsize +=3D WORD_SZ; } else { --=20 2.54.0 From nobody Mon Jun 8 09:48:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 452B22E266C; Sat, 30 May 2026 02:07:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780106832; cv=none; b=duIlaWFqMyLtva5fm/GC1dodMr9esKeO4WQG3LC3xFaQVMNrJ6iwaBZrieyyw91wai5lthknjGzYY9VimNezbbDjF73W7MZ2kfeLWcRINAWUBReRG45lJ2fQ1FAtcv+JLhfporOehOY3PaYkHQ1xBgu825eUoSy5jXAWts+XHV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780106832; c=relaxed/simple; bh=LkbJex8xqdSgG+33yzcRKv0At/+OBsWjEl20xaLjFK4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NH1/nR+vXvUNkNUOyuUDIh1DS+3fcqDU1oRDxrvzuEt1/UMPnE5zUF5IpTXQh5Wl2vkYubzMXkjNYTnjW3ffAuiyNGvSv9hXTGY3z0fgWOEulwRvQQf0SRVzfI6ih8KGV4mUCHIYcAcAQzilAly6moQ18oZIEh3Hgua4bi+bGus= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RsXWuC/k; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RsXWuC/k" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B94B71F0089B; Sat, 30 May 2026 02:07:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780106831; bh=j3VIzOPOR8EypDkapRpxZiDkFleZVLuUy2NfDvqrsCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=RsXWuC/kdwl4kaAN4HZozxs4Ht5QvElyk89Jf9OFHm1lO+RIu6n7Y5b7T6Oxj2WKa 7NDtWwWHvpL/iVtOdUc2lbYCpEXybV0X1ri69dHD+0kfPVVQcXXUsGxYyFn0FwWabW LzWnMes5wIhyyo0MQIVNGn1a/UgMbELI1rHoSe8D/C27qLiE9aArQ8T93M3kO4+zh2 d7Fw009fKYneWtcK0IHHPhzeq21xR/OJZBMRDBUn8BjuDmk32bty6Bz1LxidxkWxya E+ImhXKJpsjtcpQVyAtu87X2bYiAhD1va27PBnQZIdVqh0JIEDQ9j1YbSl26FCG4U/ fbdiAZyz23sjw== From: Eric Biggers To: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Om Prakash Singh , Bjorn Andersson , Neil Armstrong , linux-arm-msm@vger.kernel.org, Olivia Mackall , Eric Biggers , stable@vger.kernel.org Subject: [PATCH 3/4] crypto: qcom-rng - Remove crypto_rng interface Date: Fri, 29 May 2026 19:03:31 -0700 Message-ID: <20260530020332.143058-4-ebiggers@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260530020332.143058-1-ebiggers@kernel.org> References: <20260530020332.143058-1-ebiggers@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" qcom-rng.c exposes the same hardware through two completely separate interfaces, crypto_rng and hwrng. However, the implementation of this is buggy because it permits generation operations from these interfaces to run concurrently with each other, accessing the same registers. That is, qcom_rng_generate() synchronizes with itself but not with qcom_hwrng_read(). This results in potential repetition of output from the RNG, output of non-random values, etc. Fortunately, there's actually no point in hardware RNG drivers implementing the crypto_rng interface. It's not actually used by anything besides the "rng" algorithm type of AF_ALG, which in turn is not actually used in practice. Other crypto_rng hardware drivers are likewise being phased out, leaving just the hwrng support. Thus, remove it to simplify the code and avoid conflict (and confusion) with the hwrng interface which is the one that actually matters. Note that while this means the driver stops supporting "qcom,prng" and "qcom,prng-ee", it didn't do anything useful on SoCs with those anyway. Fixes: f29cd5bb64c2 ("crypto: qcom-rng - Add hw_random interface support") Cc: stable@vger.kernel.org Signed-off-by: Eric Biggers --- drivers/crypto/Kconfig | 1 - drivers/crypto/qcom-rng.c | 175 ++------------------------------------ 2 files changed, 9 insertions(+), 167 deletions(-) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 3449b3c9c6ad..a12cd677467b 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -658,11 +658,10 @@ config CRYPTO_DEV_QCE_SW_MAX_LEN =20 config CRYPTO_DEV_QCOM_RNG tristate "Qualcomm Random Number Generator Driver" depends on ARCH_QCOM || COMPILE_TEST depends on HW_RANDOM - select CRYPTO_RNG help This driver provides support for the Random Number Generator hardware found on Qualcomm SoCs. =20 To compile this driver as a module, choose M here. The diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c index b7f3b9695dac..48b605687b28 100644 --- a/drivers/crypto/qcom-rng.c +++ b/drivers/crypto/qcom-rng.c @@ -1,14 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2017-18 Linaro Limited // // Based on msm-rng.c and downstream driver =20 -#include -#include #include -#include #include #include #include #include #include @@ -30,28 +27,15 @@ #define WORD_SZ 4 =20 #define QCOM_TRNG_QUALITY 1024 =20 struct qcom_rng { - struct mutex lock; void __iomem *base; struct clk *clk; struct hwrng hwrng; - struct qcom_rng_match_data *match_data; }; =20 -struct qcom_rng_ctx { - struct qcom_rng *rng; -}; - -struct qcom_rng_match_data { - bool skip_init; - bool hwrng_support; -}; - -static struct qcom_rng *qcom_rng_dev; - static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max) { unsigned int currsize =3D 0; u32 val; int ret; @@ -77,41 +61,10 @@ static int qcom_rng_read(struct qcom_rng *rng, u8 *data= , unsigned int max) } while (currsize < max); =20 return currsize; } =20 -static int qcom_rng_generate(struct crypto_rng *tfm, - const u8 *src, unsigned int slen, - u8 *dstn, unsigned int dlen) -{ - struct qcom_rng_ctx *ctx =3D crypto_rng_ctx(tfm); - struct qcom_rng *rng =3D ctx->rng; - int ret; - - ret =3D clk_prepare_enable(rng->clk); - if (ret) - return ret; - - mutex_lock(&rng->lock); - - ret =3D qcom_rng_read(rng, dstn, dlen); - - mutex_unlock(&rng->lock); - clk_disable_unprepare(rng->clk); - - if (ret >=3D 0) - ret =3D 0; - - return ret; -} - -static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed, - unsigned int slen) -{ - return 0; -} - static int qcom_hwrng_init(struct hwrng *hwrng) { struct qcom_rng *qrng =3D container_of(hwrng, struct qcom_rng, hwrng); =20 return clk_prepare_enable(qrng->clk); @@ -129,159 +82,49 @@ static void qcom_hwrng_cleanup(struct hwrng *hwrng) struct qcom_rng *qrng =3D container_of(hwrng, struct qcom_rng, hwrng); =20 clk_disable_unprepare(qrng->clk); } =20 -static int qcom_rng_enable(struct qcom_rng *rng) -{ - u32 val; - int ret; - - ret =3D clk_prepare_enable(rng->clk); - if (ret) - return ret; - - /* Enable PRNG only if it is not already enabled */ - val =3D readl_relaxed(rng->base + PRNG_CONFIG); - if (val & PRNG_CONFIG_HW_ENABLE) - goto already_enabled; - - val =3D readl_relaxed(rng->base + PRNG_LFSR_CFG); - val &=3D ~PRNG_LFSR_CFG_MASK; - val |=3D PRNG_LFSR_CFG_CLOCKS; - writel(val, rng->base + PRNG_LFSR_CFG); - - val =3D readl_relaxed(rng->base + PRNG_CONFIG); - val |=3D PRNG_CONFIG_HW_ENABLE; - writel(val, rng->base + PRNG_CONFIG); - -already_enabled: - clk_disable_unprepare(rng->clk); - - return 0; -} - -static int qcom_rng_init(struct crypto_tfm *tfm) -{ - struct qcom_rng_ctx *ctx =3D crypto_tfm_ctx(tfm); - - ctx->rng =3D qcom_rng_dev; - - if (!ctx->rng->match_data->skip_init) - return qcom_rng_enable(ctx->rng); - - return 0; -} - -static struct rng_alg qcom_rng_alg =3D { - .generate =3D qcom_rng_generate, - .seed =3D qcom_rng_seed, - .seedsize =3D 0, - .base =3D { - .cra_name =3D "stdrng", - .cra_driver_name =3D "qcom-rng", - .cra_flags =3D CRYPTO_ALG_TYPE_RNG, - .cra_priority =3D 300, - .cra_ctxsize =3D sizeof(struct qcom_rng_ctx), - .cra_module =3D THIS_MODULE, - .cra_init =3D qcom_rng_init, - } -}; - static int qcom_rng_probe(struct platform_device *pdev) { struct qcom_rng *rng; int ret; =20 rng =3D devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL); if (!rng) return -ENOMEM; =20 - platform_set_drvdata(pdev, rng); - mutex_init(&rng->lock); - rng->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rng->base)) return PTR_ERR(rng->base); =20 rng->clk =3D devm_clk_get_optional(&pdev->dev, "core"); if (IS_ERR(rng->clk)) return PTR_ERR(rng->clk); =20 - rng->match_data =3D (struct qcom_rng_match_data *)device_get_match_data(&= pdev->dev); - - qcom_rng_dev =3D rng; - ret =3D crypto_register_rng(&qcom_rng_alg); - if (ret) { - dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret); - qcom_rng_dev =3D NULL; - return ret; - } - - if (rng->match_data->hwrng_support) { - rng->hwrng.name =3D "qcom_hwrng"; - rng->hwrng.init =3D qcom_hwrng_init; - rng->hwrng.read =3D qcom_hwrng_read; - rng->hwrng.cleanup =3D qcom_hwrng_cleanup; - rng->hwrng.quality =3D QCOM_TRNG_QUALITY; - ret =3D devm_hwrng_register(&pdev->dev, &rng->hwrng); - if (ret) { - dev_err(&pdev->dev, "Register hwrng failed: %d\n", ret); - qcom_rng_dev =3D NULL; - goto fail; - } - } - - return ret; -fail: - crypto_unregister_rng(&qcom_rng_alg); + rng->hwrng.name =3D "qcom_hwrng"; + rng->hwrng.init =3D qcom_hwrng_init; + rng->hwrng.read =3D qcom_hwrng_read; + rng->hwrng.cleanup =3D qcom_hwrng_cleanup; + rng->hwrng.quality =3D QCOM_TRNG_QUALITY; + ret =3D devm_hwrng_register(&pdev->dev, &rng->hwrng); + if (ret) + dev_err(&pdev->dev, "Register hwrng failed: %d\n", ret); return ret; } =20 -static void qcom_rng_remove(struct platform_device *pdev) -{ - crypto_unregister_rng(&qcom_rng_alg); - - qcom_rng_dev =3D NULL; -} - -static struct qcom_rng_match_data qcom_prng_match_data =3D { - .skip_init =3D false, - .hwrng_support =3D false, -}; - -static struct qcom_rng_match_data qcom_prng_ee_match_data =3D { - .skip_init =3D true, - .hwrng_support =3D false, -}; - -static struct qcom_rng_match_data qcom_trng_match_data =3D { - .skip_init =3D true, - .hwrng_support =3D true, -}; - -static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = =3D { - { .id =3D "QCOM8160", .driver_data =3D (kernel_ulong_t)&qcom_prng_ee_matc= h_data }, - {} -}; -MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match); - static const struct of_device_id __maybe_unused qcom_rng_of_match[] =3D { - { .compatible =3D "qcom,prng", .data =3D &qcom_prng_match_data }, - { .compatible =3D "qcom,prng-ee", .data =3D &qcom_prng_ee_match_data }, - { .compatible =3D "qcom,trng", .data =3D &qcom_trng_match_data }, + { .compatible =3D "qcom,trng" }, {} }; MODULE_DEVICE_TABLE(of, qcom_rng_of_match); =20 static struct platform_driver qcom_rng_driver =3D { .probe =3D qcom_rng_probe, - .remove =3D qcom_rng_remove, .driver =3D { .name =3D KBUILD_MODNAME, .of_match_table =3D qcom_rng_of_match, - .acpi_match_table =3D ACPI_PTR(qcom_rng_acpi_match), } }; module_platform_driver(qcom_rng_driver); =20 MODULE_ALIAS("platform:" KBUILD_MODNAME); --=20 2.54.0 From nobody Mon Jun 8 09:48:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F1A531328C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EpwC6X5v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 27EA01F00893; Sat, 30 May 2026 02:07:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780106831; bh=qdtTSgA6DYo+KmlVoGMUlpkScoVkmuPZGR+IizbuYXA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=EpwC6X5vEHguH1H+mxYda1gJYq34enkYv1ucdzTxpMe7h3ny5Tlj29w/rpnweeo2T 9s0ey4TblvjFwMeMDavfXQx+GVG6RriA0ijOyIQb/+eHLwmU1kyRugXSVNjfMqsrw/ aS+zGao2fSo9wYnsDEuZWDoxpdVd+L0xg8lT/B1+9qENtDgt5KkBQDCoPGRgLtkEDF L8jRylcFAP3kdOeqGdd5kSO1asl6OYdkxDUixOY+/Klh9Z3vB5fon+rmyulPsAQINC 7O+T8NZdO4Zpr+beKXKo/15daJwjYzOEYa1jRGimqiQJ7tK1RSuw1R+7XUswr8Bp0D lD7JEaGcsvK/A== From: Eric Biggers To: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Om Prakash Singh , Bjorn Andersson , Neil Armstrong , linux-arm-msm@vger.kernel.org, Olivia Mackall , Eric Biggers Subject: [PATCH 4/4] hwrng: qcom - Move qcom-rng.c into drivers/char/hw_random/ Date: Fri, 29 May 2026 19:03:32 -0700 Message-ID: <20260530020332.143058-5-ebiggers@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260530020332.143058-1-ebiggers@kernel.org> References: <20260530020332.143058-1-ebiggers@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since this file just implements a hwrng driver, move it into drivers/char/hw_random/. Rename the kconfig option accordingly as well. Signed-off-by: Eric Biggers --- arch/arm/configs/multi_v7_defconfig | 2 +- arch/arm/configs/qcom_defconfig | 2 +- arch/arm64/configs/defconfig | 2 +- drivers/char/hw_random/Kconfig | 11 +++++++++++ drivers/char/hw_random/Makefile | 1 + drivers/{crypto =3D> char/hw_random}/qcom-rng.c | 0 drivers/crypto/Kconfig | 11 ----------- drivers/crypto/Makefile | 1 - drivers/gpu/drm/ci/arm64.config | 2 +- 9 files changed, 16 insertions(+), 16 deletions(-) rename drivers/{crypto =3D> char/hw_random}/qcom-rng.c (100%) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v= 7_defconfig index bcc9aabc1202..a3c612a9d423 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -404,10 +404,11 @@ CONFIG_SERIAL_DEV_BUS=3Dy CONFIG_VIRTIO_CONSOLE=3Dy CONFIG_ASPEED_KCS_IPMI_BMC=3Dm CONFIG_ASPEED_BT_IPMI_BMC=3Dm CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_ST=3Dy +CONFIG_HW_RANDOM_QCOM=3Dm CONFIG_TCG_TPM=3Dm CONFIG_TCG_TIS_I2C_INFINEON=3Dm CONFIG_I2C_CHARDEV=3Dy CONFIG_I2C_ARB_GPIO_CHALLENGE=3Dm CONFIG_I2C_MUX_GPIO=3Dy @@ -1334,11 +1335,10 @@ CONFIG_CRYPTO_DEV_S5P=3Dm CONFIG_CRYPTO_DEV_ATMEL_AES=3Dm CONFIG_CRYPTO_DEV_ATMEL_TDES=3Dm CONFIG_CRYPTO_DEV_ATMEL_SHA=3Dm CONFIG_CRYPTO_DEV_MARVELL_CESA=3Dm CONFIG_CRYPTO_DEV_QCE=3Dm -CONFIG_CRYPTO_DEV_QCOM_RNG=3Dm CONFIG_CRYPTO_DEV_ROCKCHIP=3Dm CONFIG_CRYPTO_DEV_STM32_HASH=3Dm CONFIG_CRYPTO_DEV_STM32_CRYP=3Dm CONFIG_CMA_SIZE_MBYTES=3D64 CONFIG_PRINTK_TIME=3Dy diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defcon= fig index 29a1dea500f0..d57554971c03 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -115,10 +115,11 @@ CONFIG_SERIO_LIBPS2=3Dy # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_MSM=3Dy CONFIG_SERIAL_MSM_CONSOLE=3Dy CONFIG_SERIAL_DEV_BUS=3Dy CONFIG_HW_RANDOM=3Dy +CONFIG_HW_RANDOM_QCOM=3Dm CONFIG_I2C=3Dy CONFIG_I2C_CHARDEV=3Dy CONFIG_I2C_QUP=3Dy CONFIG_SPI=3Dy CONFIG_SPI_QUP=3Dy @@ -309,11 +310,10 @@ CONFIG_CRYPTO_USER=3Dm CONFIG_CRYPTO_USER_API=3Dm CONFIG_CRYPTO_USER_API_HASH=3Dm CONFIG_CRYPTO_USER_API_SKCIPHER=3Dm CONFIG_CRYPTO_USER_API_RNG=3Dm CONFIG_CRYPTO_USER_API_AEAD=3Dm -CONFIG_CRYPTO_DEV_QCOM_RNG=3Dm CONFIG_DMA_CMA=3Dy CONFIG_CMA_SIZE_MBYTES=3D64 CONFIG_PRINTK_TIME=3Dy CONFIG_DYNAMIC_DEBUG=3Dy CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=3Dy diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d905a0777f93..bb930cce7233 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -548,10 +548,11 @@ CONFIG_VIRTIO_CONSOLE=3Dy CONFIG_IPMI_HANDLER=3Dm CONFIG_IPMI_DEVICE_INTERFACE=3Dm CONFIG_IPMI_SI=3Dm CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_VIRTIO=3Dy +CONFIG_HW_RANDOM_QCOM=3Dm CONFIG_TCG_TPM=3Dy CONFIG_TCG_TIS=3Dm CONFIG_TCG_TIS_SPI=3Dm CONFIG_TCG_TIS_SPI_CR50=3Dy CONFIG_TCG_TIS_I2C_CR50=3Dm @@ -1951,11 +1952,10 @@ CONFIG_CRYPTO_AES_ARM64_BS=3Dm CONFIG_CRYPTO_AES_ARM64_CE_CCM=3Dy CONFIG_CRYPTO_DEV_SUN8I_CE=3Dm CONFIG_CRYPTO_DEV_FSL_CAAM=3Dm CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=3Dm CONFIG_CRYPTO_DEV_QCE=3Dm -CONFIG_CRYPTO_DEV_QCOM_RNG=3Dm CONFIG_CRYPTO_DEV_TEGRA=3Dm CONFIG_CRYPTO_DEV_XILINX_TRNG=3Dm CONFIG_CRYPTO_DEV_ZYNQMP_AES=3Dm CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=3Dm CONFIG_CRYPTO_DEV_CCREE=3Dm diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 492a2a61a65b..7102e03dcf0a 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -613,10 +613,21 @@ config HW_RANDOM_ROCKCHIP To compile this driver as a module, choose M here: the module will be called rockchip-rng. =20 If unsure, say Y. =20 +config HW_RANDOM_QCOM + tristate "Qualcomm True Random Number Generator Driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on HW_RANDOM + help + This driver provides support for the True Random Number + Generator hardware found on some Qualcomm SoCs. + + To compile this driver as a module, choose M here. The + module will be called qcom-rng. If unsure, say N. + endif # HW_RANDOM =20 config UML_RANDOM depends on UML select HW_RANDOM diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makef= ile index b9132b3f5d21..605ba8df5a8f 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -50,5 +50,6 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) +=3D xiphera-trng.o obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) +=3D arm_smccc_trng.o obj-$(CONFIG_HW_RANDOM_CN10K) +=3D cn10k-rng.o obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) +=3D mpfs-rng.o obj-$(CONFIG_HW_RANDOM_ROCKCHIP) +=3D rockchip-rng.o obj-$(CONFIG_HW_RANDOM_JH7110) +=3D jh7110-trng.o +obj-$(CONFIG_HW_RANDOM_QCOM) +=3D qcom-rng.o diff --git a/drivers/crypto/qcom-rng.c b/drivers/char/hw_random/qcom-rng.c similarity index 100% rename from drivers/crypto/qcom-rng.c rename to drivers/char/hw_random/qcom-rng.c diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index a12cd677467b..07f0fa3341fc 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -654,21 +654,10 @@ config CRYPTO_DEV_QCE_SW_MAX_LEN =20 Note that 192-bit keys are not supported by the hardware and are always processed by the software fallback, and all DES requests are done by the hardware. =20 -config CRYPTO_DEV_QCOM_RNG - tristate "Qualcomm Random Number Generator Driver" - depends on ARCH_QCOM || COMPILE_TEST - depends on HW_RANDOM - help - This driver provides support for the Random Number - Generator hardware found on Qualcomm SoCs. - - To compile this driver as a module, choose M here. The - module will be called qcom-rng. If unsure, say N. - config CRYPTO_DEV_IMGTEC_HASH tristate "Imagination Technologies hardware hash accelerator" depends on MIPS || COMPILE_TEST select CRYPTO_MD5 select CRYPTO_SHA1 diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 283bbc650b5b..a5f3d388f4d0 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -26,11 +26,10 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) +=3D omap-des.o obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) +=3D omap-sham.o obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) +=3D padlock-aes.o obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) +=3D padlock-sha.o obj-$(CONFIG_CRYPTO_DEV_PPC4XX) +=3D amcc/ obj-$(CONFIG_CRYPTO_DEV_QCE) +=3D qce/ -obj-$(CONFIG_CRYPTO_DEV_QCOM_RNG) +=3D qcom-rng.o obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) +=3D rockchip/ obj-$(CONFIG_CRYPTO_DEV_S5P) +=3D s5p-sss.o obj-$(CONFIG_CRYPTO_DEV_SA2UL) +=3D sa2ul.o obj-$(CONFIG_CRYPTO_DEV_SAHARA) +=3D sahara.o obj-$(CONFIG_CRYPTO_DEV_SL3516) +=3D gemini/ diff --git a/drivers/gpu/drm/ci/arm64.config b/drivers/gpu/drm/ci/arm64.con= fig index 563a69669a7b..c46125c1f80f 100644 --- a/drivers/gpu/drm/ci/arm64.config +++ b/drivers/gpu/drm/ci/arm64.config @@ -76,11 +76,10 @@ CONFIG_INTERCONNECT_QCOM_SDM845=3Dy CONFIG_INTERCONNECT_QCOM_MSM8916=3Dy CONFIG_INTERCONNECT_QCOM_MSM8996=3Dy CONFIG_INTERCONNECT_QCOM_OSM_L3=3Dy CONFIG_INTERCONNECT_QCOM_SC7180=3Dy CONFIG_INTERCONNECT_QCOM_SM8350=3Dy -CONFIG_CRYPTO_DEV_QCOM_RNG=3Dy CONFIG_SC_DISPCC_7180=3Dy CONFIG_SC_GPUCC_7180=3Dy CONFIG_SM_GPUCC_8350=3Dy CONFIG_QCOM_SPMI_ADC5=3Dy CONFIG_QCOM_SPMI_VADC=3Dy @@ -187,10 +186,11 @@ CONFIG_PWM_MEDIATEK=3Dy CONFIG_DRM_MEDIATEK_HDMI=3Dy CONFIG_GNSS=3Dy CONFIG_GNSS_MTK_SERIAL=3Dy CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_MTK=3Dy +CONFIG_HW_RANDOM_QCOM=3Dy CONFIG_MTK_DEVAPC=3Dy CONFIG_PWM_MTK_DISP=3Dy CONFIG_MTK_CMDQ=3Dy CONFIG_REGULATOR_DA9211=3Dy CONFIG_DRM_ANALOGIX_ANX7625=3Dy --=20 2.54.0