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[2a01:cb09:e035:4cc8:78d0:97:5365:75e1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909cabfd6esm55150315e9.15.2026.05.29.08.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 08:55:57 -0700 (PDT) From: MidG971 To: Tomeu Vizoso , Oded Gabbay Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Midgy BALON Subject: [PATCH v2 1/4] accel: rocket: Add support for Rockchip RK3568 Date: Fri, 29 May 2026 17:58:21 +0200 Message-Id: <20260529155824.3099831-2-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260529155824.3099831-1-midgy971@gmail.com> References: <20260529155824.3099831-1-midgy971@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Midgy BALON The RK3568 has a single NVDLA-derived NPU core (0.8 TOPS), the same IP family as the three-core RK3588 NPU already supported by the Rocket driver. To accommodate both SoCs: - Introduce a per-SoC rocket_soc_data structure carrying dma_bits and an optional noc_init callback, plumbed through of_device_get_match_data(). - rocket_device_init() now scans for both rk3568 and rk3588 RKNN cores and picks the narrower DMA width (32-bit) when an RK3568 core is present. - Add rk3568_soc_data and rk3568_noc_init() handling the three RK3568- specific initialisation steps that must run after the power domain is on and clocks are enabled: 1. PVTPLL initialisation: The NPU uses a PVTPLL ring oscillator managed by TF-A via SCMI for rates above 400 MHz. A two-step clk_set_rate() sequence (600 MHz then 1 GHz) forces two SCMI calls to TF-A even if the kernel clock framework would skip an unchanged rate. The PVTPLL must be running before the NPU NOC bus will acknowledge a de-idle request. 2. Explicit NPU power-on (PWR_GATE_SFTCON): The RK3568_PD_NPU power domain is marked always_on in pm-domains.c, so the generic power domain framework power_on() callback is a no-op. The NPU hardware can remain power-gated at boot. Writing bit 1 =3D 0 to PWR_GATE_SFTCON (PMU offset 0xa0) explicitly powers on the NPU hardware before the de-idle request is issued. 3. NOC bus de-idle: Disable NPU NOC auto-idle (NOC_AUTO_CON0 bit 2), request de-idle (BUS_IDLE_SFTCON0 bit 2 =3D 0), then poll BUS_IDLE_ST (PMU offset 0x60) until bit 2 clears (bus active). The RK3568 DMA address space is limited to 32 bits, as the NPU AXI bus and IOMMU page walker cannot address memory above 4 GB. All PMU accesses follow the RK3568 write-mask protocol: upper 16 bits are the write-enable mask for the lower 16 bits. Signed-off-by: Midgy BALON --- drivers/accel/rocket/rocket_core.c | 18 ++++++- drivers/accel/rocket/rocket_core.h | 16 +++++++ drivers/accel/rocket/rocket_device.c | 25 ++++++++-- drivers/accel/rocket/rocket_drv.c | 71 +++++++++++++++++++++++++++- 4 files changed, 125 insertions(+), 5 deletions(-) diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rock= et_core.c index abe7719c1..7e2f3524a 100644 --- a/drivers/accel/rocket/rocket_core.c +++ b/drivers/accel/rocket/rocket_core.c @@ -21,6 +21,12 @@ int rocket_core_init(struct rocket_core *core) u32 version; int err =3D 0; =20 + core->soc_data =3D of_device_get_match_data(dev); + if (!core->soc_data) + return dev_err_probe(dev, -EINVAL, + "no per-SoC match data for core %d\n", + core->index); + core->resets[0].id =3D "srst_a"; core->resets[1].id =3D "srst_h"; err =3D devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core= ->resets), @@ -52,7 +58,8 @@ int rocket_core_init(struct rocket_core *core) =20 dma_set_max_seg_size(dev, UINT_MAX); =20 - err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); + err =3D dma_set_mask_and_coherent(dev, + DMA_BIT_MASK(core->soc_data->dma_bits)); if (err) return err; =20 @@ -80,6 +87,15 @@ int rocket_core_init(struct rocket_core *core) return err; } =20 + if (core->soc_data->noc_init) { + err =3D core->soc_data->noc_init(core); + if (err) { + pm_runtime_put_sync(dev); + rocket_job_fini(core); + return err; + } + } + version =3D rocket_pc_readl(core, VERSION); version +=3D rocket_pc_readl(core, VERSION_NUM) & 0xffff; =20 diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rock= et_core.h index f6d738285..742e14a29 100644 --- a/drivers/accel/rocket/rocket_core.h +++ b/drivers/accel/rocket/rocket_core.h @@ -12,6 +12,21 @@ =20 #include "rocket_registers.h" =20 +struct rocket_core; + +/** + * struct rocket_soc_data - per-SoC configuration data + * @dma_bits: Physical address width reachable by the NPU's AXI bus. + * RK3568: 32 (32-bit AXI), RK3588: 40. + * @noc_init: optional callback to de-idle the NPU NOC bus at core init. + * Required on RK3568 where the NOC must be explicitly un-idled + * before the NPU can be accessed. + */ +struct rocket_soc_data { + unsigned int dma_bits; + int (*noc_init)(struct rocket_core *core); +}; + #define rocket_pc_readl(core, reg) \ readl((core)->pc_iomem + (REG_PC_##reg)) #define rocket_pc_writel(core, reg, value) \ @@ -31,6 +46,7 @@ struct rocket_core { struct device *dev; struct rocket_device *rdev; unsigned int index; + const struct rocket_soc_data *soc_data; =20 int irq; void __iomem *pc_iomem; diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/ro= cket_device.c index 46e6ee1e7..0ed8251c8 100644 --- a/drivers/accel/rocket/rocket_device.c +++ b/drivers/accel/rocket/rocket_device.c @@ -27,6 +27,9 @@ struct rocket_device *rocket_device_init(struct platform_= device *pdev, ddev =3D &rdev->ddev; dev_set_drvdata(dev, rdev); =20 + for_each_compatible_node(core_node, NULL, "rockchip,rk3568-rknn-core") + if (of_device_is_available(core_node)) + num_cores++; for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core") if (of_device_is_available(core_node)) num_cores++; @@ -37,9 +40,25 @@ struct rocket_device *rocket_device_init(struct platform= _device *pdev, =20 dma_set_max_seg_size(dev, UINT_MAX); =20 - err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); - if (err) - return ERR_PTR(err); + /* Use the DMA width of the first available RKNN core. RK3568 cores + * are 32-bit; RK3588 are 40-bit. If both are present we pick the + * narrower mask. + */ + { + struct device_node *n; + unsigned int dma_bits =3D 40; + + for_each_compatible_node(n, NULL, "rockchip,rk3568-rknn-core") + if (of_device_is_available(n)) { + dma_bits =3D 32; + of_node_put(n); + break; + } + + err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_bits)); + if (err) + return ERR_PTR(err); + } =20 err =3D devm_mutex_init(dev, &rdev->sched_lock); if (err) diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocke= t_drv.c index 5c0b63f0a..f8e153fc2 100644 --- a/drivers/accel/rocket/rocket_drv.c +++ b/drivers/accel/rocket/rocket_drv.c @@ -9,9 +9,11 @@ #include #include #include +#include #include #include #include +#include =20 #include "rocket_drv.h" #include "rocket_gem.h" @@ -199,8 +201,75 @@ static void rocket_remove(struct platform_device *pdev) } } =20 +/* + * RK3568 NOC de-idle: the NPU bus must be explicitly un-idled before the + * NPU hardware can be accessed. The RK3568 PMU provides BUS_IDLE_SFTCON0 + * (offset 0x50) and NOC_AUTO_CON0 (offset 0x70) for this purpose. Refer + * to the RK3568 TRM section "PMU" for the write-mask protocol used by + * these registers (bits [31:16] are write-enable for bits [15:0]). + * + * rocket_clk_names[] in rocket_core.c defines: "aclk"[0], "hclk"[1], + * "npu"[2], "pclk"[3]. Index 2 is the SCMI-managed NPU clock. + */ +#define ROCKET_CLK_NPU_IDX 2 + +static int rk3568_noc_init(struct rocket_core *core) +{ + struct regmap *pmu; + unsigned int val; + int ret; + + /* + * RK3568: PVTPLL (the NPU's high-speed clock, managed by TF-A via + * SCMI) must be running before the NPU NOC bus will de-idle. Force + * two SCMI calls now that the NPU power domain is on and clocks are + * enabled. The intermediate 600 MHz step ensures a real SCMI call + * even when the kernel clock framework would otherwise skip an + * "unchanged rate" request. + */ + clk_set_rate(core->clks[ROCKET_CLK_NPU_IDX].clk, 600000000UL); + clk_set_rate(core->clks[ROCKET_CLK_NPU_IDX].clk, 1000000000UL); + + pmu =3D syscon_regmap_lookup_by_phandle(core->dev->of_node, "rockchip,pmu= "); + if (IS_ERR(pmu)) + return dev_err_probe(core->dev, PTR_ERR(pmu), + "failed to get PMU regmap\n"); + + /* Disable NPU NOC auto-idle so the bus stays awake */ + regmap_write(pmu, 0x70, BIT(2 + 16)); + + /* + * Request NPU power domain power-on (PWR_GATE_SFTCON bit 1 =3D 0). + * genpd for RK3568_PD_NPU is always_on so its power_on() is a no-op; + * explicitly power on the hardware here so the bus de-idle ACK arrives. + */ + regmap_write(pmu, 0xa0, BIT(1 + 16)); + + /* Request NPU bus de-idle (bit 2 =3D 0 =E2=86=92 active) */ + regmap_write(pmu, 0x50, BIT(2 + 16)); + + /* Wait for NPU bus to become active (BUS_IDLE_ST bit 2 =3D 0) */ + ret =3D regmap_read_poll_timeout(pmu, 0x60, val, !(val & BIT(2)), 10, 100= 0); + if (ret) + dev_err(core->dev, + "timeout waiting for NPU bus de-idle (BUS_IDLE_ST=3D0x%08x)\n", + val); + + return ret; +} + +static const struct rocket_soc_data rk3568_soc_data =3D { + .dma_bits =3D 32, + .noc_init =3D rk3568_noc_init, +}; + +static const struct rocket_soc_data rk3588_soc_data =3D { + .dma_bits =3D 40, +}; + static const struct of_device_id dt_match[] =3D { - { .compatible =3D "rockchip,rk3588-rknn-core" }, + { .compatible =3D "rockchip,rk3568-rknn-core", .data =3D &rk3568_soc_data= }, + { .compatible =3D "rockchip,rk3588-rknn-core", .data =3D &rk3588_soc_data= }, {} }; MODULE_DEVICE_TABLE(of, dt_match); --=20 2.39.5 From nobody Mon Jun 8 10:56:39 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D28A83F44CB for ; Fri, 29 May 2026 15:56:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[2a01:cb09:e035:4cc8:78d0:97:5365:75e1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909cabfd6esm55150315e9.15.2026.05.29.08.56.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 08:56:05 -0700 (PDT) From: MidG971 To: Tomeu Vizoso , Oded Gabbay Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Midgy BALON Subject: [PATCH v2 2/4] dt-bindings: npu: rockchip,rk3588-rknn-core: Add RK3568 support Date: Fri, 29 May 2026 17:58:22 +0200 Message-Id: <20260529155824.3099831-3-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260529155824.3099831-1-midgy971@gmail.com> References: <20260529155824.3099831-1-midgy971@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Midgy BALON Add rockchip,rk3568-rknn-core to the compatible enum, document the new rockchip,pmu phandle that RK3568 needs for the NPU NOC bus de-idle sequence, and make sram-supply only required on RK3588 (RK3568 has no NPU SRAM rail). The driver supports both RK3568 and RK3588 RKNN cores; the binding now documents both. The rockchip,pmu phandle is consumed by the driver to issue PMU register writes (BUS_IDLE_SFTCON0, NOC_AUTO_CON0, PWR_GATE_SFTCON, BUS_IDLE_ST) on RK3568 only. Signed-off-by: Midgy BALON --- .../npu/rockchip,rk3588-rknn-core.yaml | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-cor= e.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.ya= ml index caca2a490..6582a0c5c 100644 --- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml @@ -21,6 +21,7 @@ properties: =20 compatible: enum: + - rockchip,rk3568-rknn-core - rockchip,rk3588-rknn-core =20 reg: @@ -50,6 +51,13 @@ properties: =20 npu-supply: true =20 + rockchip,pmu: + : /schemas/types.yaml#/definitions/phandle + description: + Phandle to the Rockchip PMU syscon node. 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[2a01:cb09:e035:4cc8:78d0:97:5365:75e1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909cabfd6esm55150315e9.15.2026.05.29.08.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 08:56:12 -0700 (PDT) From: MidG971 To: Tomeu Vizoso , Oded Gabbay Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Midgy BALON Subject: [PATCH v2 3/4] arm64: dts: rockchip: rk356x: Add NPU and its IOMMU Date: Fri, 29 May 2026 17:58:23 +0200 Message-Id: <20260529155824.3099831-4-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260529155824.3099831-1-midgy971@gmail.com> References: <20260529155824.3099831-1-midgy971@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Midgy BALON Add the RKNN core 0 and its IOMMU to the RK3568 SoC dtsi, mirroring the RK3588 pattern in rk3588-base.dtsi but with rk3568-specific clocks, resets, power domain, and a rockchip,pmu phandle required for the NPU NOC bus de-idle sequence. Both nodes remain disabled by default; boards enable them as needed. Signed-off-by: Midgy BALON --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 8893b7b6c..2c2a57ea3 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -929,6 +929,37 @@ qos_rga_wr: qos@fe158300 { reg =3D <0x0 0xfe158300 0x0 0x20>; }; =20 + rknn_core_0: npu@fde40000 { + compatible =3D "rockchip,rk3568-rknn-core"; + reg =3D <0x0 0xfde40000 0x0 0x1000>, + <0x0 0xfde41000 0x0 0x1000>, + <0x0 0xfde43000 0x0 0x1000>; + reg-names =3D "pc", "cna", "core"; + interrupts =3D ; + clocks =3D <&cru ACLK_NPU>, <&cru HCLK_NPU>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_PRE>; + clock-names =3D "aclk", "hclk", "npu", "pclk"; + assigned-clocks =3D <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates =3D <200000000>; + resets =3D <&cru SRST_A_NPU>, <&cru SRST_H_NPU>; + reset-names =3D "srst_a", "srst_h"; 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Fri, 29 May 2026 08:56:17 -0700 (PDT) Received: from debian.tailb81abf.ts.net (2a01cb09e0354cc878d00097536575e1.ipv6.abo.wanadoo.fr. [2a01:cb09:e035:4cc8:78d0:97:5365:75e1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909cabfd6esm55150315e9.15.2026.05.29.08.56.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 08:56:17 -0700 (PDT) From: MidG971 To: Tomeu Vizoso , Oded Gabbay Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Midgy BALON Subject: [PATCH v2 4/4] arm64: dts: rockchip: rk3568-rock-3b: Enable NPU Date: Fri, 29 May 2026 17:58:24 +0200 Message-Id: <20260529155824.3099831-5-midgy971@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260529155824.3099831-1-midgy971@gmail.com> References: <20260529155824.3099831-1-midgy971@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Midgy BALON Enable the RKNN core 0 and its IOMMU on the Radxa ROCK 3B by overriding their status. The Rocket accel driver binds via the rockchip,rk3568-rknn-core compatible. The NPU is powered from vdd_npu (regulator already defined for OPP table). The IOMMU node is also enabled so the rocket driver can manage its own paging domain for user-mode submissions. Signed-off-by: Midgy BALON --- arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/b= oot/dts/rockchip/rk3568-rock-3b.dts index 3d0c1ccfa..d54229123 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -779,3 +779,12 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint =3D <&hdmi_in_vp0>; }; }; + +&rknn_core_0 { + npu-supply =3D <&vdd_npu>; + status =3D "okay"; +}; + +&rknn_mmu_0 { + status =3D "okay"; +}; --=20 2.39.5