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Fri, 29 May 2026 07:47:17 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.43.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909d6eb470sm38694785e9.10.2026.05.29.07.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 07:47:16 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, francesco.utel@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Alexandre Torgue , Amelie Delaunay , Christophe Parant , Conor Dooley , Himanshu Bhavani , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 01/15] dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board Date: Fri, 29 May 2026 16:46:15 +0200 Message-ID: <20260529144707.3931919-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> References: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA-STM32MP257-RMM board based on the Engicam MicroGEA-STM32MP257 SoM (System-on-Module). The use of an enum for a single element is justified by the future addition of other boards based on the same SoM. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- Changes in v2: - Add Acked-by of Conor Dooley for patch 0/1 "dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board" Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Docum= entation/devicetree/bindings/arm/stm32/stm32.yaml index c6af3a46364f..c5ce81e3ce45 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -203,6 +203,13 @@ properties: - st,stm32mp257f-ev1 - const: st,stm32mp257 =20 + - description: Engicam MicroGEA STM32MP257 SoM based Boards + items: + - enum: + - engicam,microgea-stm32mp257-rmm + - const: engicam,microgea-stm32mp257 + - const: st,stm32mp257 + - description: ST STM32MP235 based Boards items: - enum: --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2F6D3F58C9 for ; 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charset="utf-8" The SDMMC2 controller supports SD cards, eMMC memories and SDIO devices. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp251.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 673fbc5632e6..5e46024d2215 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1667,6 +1667,21 @@ sdmmc1: mmc@48220000 { status =3D "disabled"; }; =20 + sdmmc2: mmc@48230000 { + compatible =3D "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid =3D <0x00353180>; + reg =3D <0x48230000 0x400>, <0x44230800 0x8>; + interrupts =3D ; + clocks =3D <&rcc CK_KER_SDMMC2>; + clock-names =3D "apb_pclk"; + resets =3D <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency =3D <120000000>; + access-controllers =3D <&rifsc 77>; + status =3D "disabled"; + }; + ethernet1: ethernet@482c0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482c0000 0x4000>; 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charset="utf-8" The controller is compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. Signed-off-by: Dario Binacchi --- Changes in v2: - Add resets property to dts CAN node. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp253.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/s= t/stm32mp253.dtsi index eeceb086252b..7e82f01fdc10 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -43,6 +43,22 @@ &optee { }; =20 &rifsc { + m_can1: can@402d0000 { + compatible =3D "bosch,m_can"; + reg =3D <0x402d0000 0x400>, <0x40310000 0xd50>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + clocks =3D <&rcc CK_BUS_FDCAN>, <&rcc CK_KER_FDCAN>; + clock-names =3D "hclk", "cclk"; + resets =3D <&rcc FDCAN_R>; + bosch,mram-cfg =3D <0x0 0 0 32 0 0 2 2>; + access-controllers =3D <&rifsc 56>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + ethernet2: ethernet@482d0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482d0000 0x4000>; --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 951873F8715 for ; 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charset="utf-8" Add the i2c1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 456ece7f8ebc..db485b9ed904 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -203,6 +203,25 @@ pins { }; }; =20 + /omit-if-no-ref/ + i2c1_pins_a: i2c1-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 274DC3F9272 for ; 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charset="utf-8" Add the LTDC pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index db485b9ed904..05bd07a0a561 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -260,6 +260,77 @@ pins { }; }; =20 + /omit-if-no-ref/ + ltdc_pins_a: ltdc-0 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_a: ltdc-sleep-0 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6FB2436371 for ; Fri, 29 May 2026 14:47:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add the can1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 05bd07a0a561..4be01a6574c7 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -331,6 +331,28 @@ pins { }; }; =20 + /omit-if-no-ref/ + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + slew-rate =3D <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + m_can1_sleep_pins_a: m-can1-sleep-0 { + pins { + pinmux =3D , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB51F43901A for ; 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charset="utf-8" Add the pwm2 and pwm4 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 4be01a6574c7..eab8ebe71660 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -433,6 +433,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm2_pins_a: pwm2-0 { + pins { + pinmux =3D ; /* TIM2_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm2_sleep_pins_a: pwm2-sleep-0 { + pins { + pinmux =3D ; /* TIM2_CH1 */ + }; + }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { @@ -450,6 +467,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm4_pins_a: pwm4-0 { + pins { + pinmux =3D ; /* TIM4_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux =3D ; /* TIM4_CH1 */ + }; + }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 937FD43C076 for ; Fri, 29 May 2026 14:47:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780066052; cv=none; b=P9Zte4WVJS0G7dNEN9t53gowgsk3iQIdz+y9UlECu6eXZrH0oWhBSVTPU7xA4M5lNe1p5XTooenSwZOrg8UultjSVzIi6VbJMhmerCJBhQbl/M9r2Nx1VU6CRuCYAlU6NQl/+MW9fxfpB0jkTFpkm075xhG1VZ9OtsOgLKcXtes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780066052; c=relaxed/simple; bh=smK0LMyu8EXiOot7ocNTu7szAih1Fd4nfquSIb6ZAtE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" Add the sai1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index eab8ebe71660..ab1e62cf2bfc 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -520,6 +520,51 @@ pins { }; }; =20 + /omit-if-no-ref/ + sai1a_pins_a: sai1a-0 { + pins1 { + pinmux =3D , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + ; /* SAI1_SCK_A */ + bias-disable; + drive-push-pull; + slew-rate =3D <1>; + }; + pins2 { + pinmux =3D ; /* SAI1_MCLK_A */ + bias-disable; + drive-push-pull; + slew-rate =3D <2>; + }; + }; + + /omit-if-no-ref/ + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux =3D , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + , /* SAI1_SCK_A */ + ; /* SAI1_MCLK_A */ + }; + }; + + /omit-if-no-ref/ + sai1b_pins_a: sai1b-0 { + pins { + pinmux =3D ; /* SAI1_SD_B */ + bias-disable; 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charset="utf-8" Add the sdmmc2 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index ab1e62cf2bfc..62f898a55d45 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -622,6 +622,86 @@ pins { }; }; =20 + /omit-if-no-ref/ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux =3D ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux =3D , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1969D43CEFE for ; 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charset="utf-8" Add the spi1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 62f898a55d45..46c5197dcd63 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -702,6 +702,30 @@ pins { }; }; =20 + /omit-if-no-ref/ + spi1_pins_a: spi1-0 { + pins1 { + pinmux =3D , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + drive-push-pull; + bias-disable; + slew-rate =3D <1>; + }; + pins2 { + pinmux =3D ; /* SPI1_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi1_sleep_pins_a: spi1-sleep-0 { + pins1 { + pinmux =3D , /* SPI1_SCK */ + , /* SPI1_MOSI */ + ; /* SPI1_MISO */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB44D43D515 for ; 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charset="utf-8" Add the usart1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 46c5197dcd63..a72c458b2c6e 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -766,6 +766,39 @@ pins { }; }; =20 + /omit-if-no-ref/ + usart1_pins_b: usart1-1 { + pins1 { + pinmux =3D ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + pins2 { + pinmux =3D ; /* USART1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux =3D ; /* USART1_TX */ + }; + pins2 { + pinmux =3D ; /* USART1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux =3D , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { --=20 2.43.0 From nobody Mon Jun 8 11:02:05 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C57F63D75B6 for ; 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Fri, 29 May 2026 07:47:37 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.43.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909d6eb470sm38694785e9.10.2026.05.29.07.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 07:47:36 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, francesco.utel@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 12/15] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM Date: Fri, 29 May 2026 16:46:26 +0200 Message-ID: <20260529144707.3931919-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> References: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA-STM32MP257 SoM with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM The SoM also provides an Ethernet MAC, but Ethernet support is not enabled at this stage due to a known silicon limitation documented in [1]. This corresponds to section 2.21.2 ("ETH1 RMII mode could have CRC errors"), where CRC errors may occur in ETH1 RMII direct mode when directly connected to I/Os. The workaround requires use of the Ethernet switch (ETHSW), which introduces additional DT bindings and topology complexity. This is intended to be addressed in a separate patch series. [1] https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-devi= ce-errata-stmicroelectronics.pd Signed-off-by: Dario Binacchi --- (no changes since v1) .../dts/st/stm32mp257-engicam-microgea.dtsi | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch= /arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi new file mode 100644 index 000000000000..67be66cd1930 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model =3D "Engicam MicroGEA STM32MP257 SoM"; + compatible =3D "engicam,microgea-stm32mp257", "st,stm32mp257"; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + scmi_vddcore: regulator@b { + reg =3D ; + regulator-name =3D "vddcore"; + }; + scmi_v1v8: regulator@e { + reg =3D ; + regulator-name =3D "v1v8"; + }; + scmi_v3v3: regulator@10 { + reg =3D ; + regulator-name =3D "v3v3"; + }; + scmi_vdd3v3_usb: regulator@14 { + reg =3D ; + regulator-name =3D "vdd3v3_usb"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 =3D <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 =3D <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width =3D <8>; + vmmc-supply =3D <&scmi_v3v3>; + vqmmc-supply =3D <&scmi_vddio2>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status =3D "okay"; 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Fri, 29 May 2026 07:47:39 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.43.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909d6eb470sm38694785e9.10.2026.05.29.07.47.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 07:47:38 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, francesco.utel@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 13/15] arm64: dts: st: support Engicam MicroGEA-STM32MP257-RMM board Date: Fri, 29 May 2026 16:46:27 +0200 Message-ID: <20260529144707.3931919-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> References: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support for Engicam MicroGEA-STM32MP257-RMM board with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM - CAN - LEDs - LCD panel with touchscreen - Micro SD card connector - Audio codec - Buzzer Signed-off-by: Dario Binacchi --- Changes in v2: - Drop the clocks property from the sai1 node in stm32mp257-engicam-microge= a-rmm.dts to avoid overriding the peripheral bus clock reference defined in the base SoC device tree. Suggested by Sashiko. - Reference the existing labeled nodes directly at the root level using &sai1a and &sai1b in stm32mp257-engicam-microgea-rmm.dts instead of redefining the entire node structure and redeclaring the labels. Suggeste= d by Sashiko. - Drop the #clock-cells property from sai1a and remove the reference to sai= 1a from the clocks array in sai1b, relying strictly on the st,sync property to ha= ndle internal synchronization. arch/arm64/boot/dts/st/Makefile | 1 + .../st/stm32mp257-engicam-microgea-rmm.dts | 319 ++++++++++++++++++ 2 files changed, 320 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.= dts diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makef= ile index 63908113ae36..386eca593c54 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -2,5 +2,6 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32mp215f-dk.dtb \ stm32mp235f-dk.dtb \ + stm32mp257-engicam-microgea-rmm.dtb \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts b/a= rch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts new file mode 100644 index 000000000000..0212c03aae1a --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include +#include + +#include "stm32mp257-engicam-microgea.dtsi" + +/ { + model =3D "Engicam MicroGEA STM32MP257D RMM Board"; + compatible =3D "engicam,microgea-stm32mp257-rmm", + "engicam,microgea-stm32mp257", "st,stm32mp257"; + + aliases { + mmc0 =3D &sdmmc1; + mmc1 =3D &sdmmc2; + serial0 =3D &usart2; + serial1 =3D &usart1; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm2 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer { + compatible =3D "simple-framebuffer"; + clocks =3D <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>; + lcd-supply =3D <®_3v3>; + status =3D "disabled"; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&gpioh 2 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + + led-1 { + gpios =3D <&gpioh 6 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + }; + + mclk: clock-mclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpiog 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "audio-graph-card"; + label =3D "STM32MP25-RMM"; + widgets =3D "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + routing =3D "Headphone Jack", "HP_OUT", + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + dais =3D <&sai1a_port &sai1b_port>; + status =3D "okay"; + }; +}; + +&arm_wdt { + timeout-sec =3D <32>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c1_pins_a>; + pinctrl-1 =3D <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + touchscreen@38 { + compatible =3D "edt,edt-ft5306"; + reg =3D <0x38>; + interrupt-parent =3D <&gpiob>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpiod 1 GPIO_ACTIVE_LOW>; + touchscreen-size-x =3D <1280>; + touchscreen-size-y =3D <800>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c2_pins_a>; + pinctrl-1 =3D <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + #sound-dai-cells =3D <0>; + clocks =3D <&mclk>; + + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + + sgtl5000_port: port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&sai1a_endpoint>; + frame-master =3D <&sgtl5000_tx_endpoint>; + bitclock-master =3D <&sgtl5000_tx_endpoint>; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&sai1b_endpoint>; + frame-master =3D <&sgtl5000_rx_endpoint>; + bitclock-master =3D <&sgtl5000_rx_endpoint>; + }; + }; + }; +}; + +<dc { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <<dc_pins_a>; + pinctrl-1 =3D <<dc_sleep_pins_a>; + status =3D "okay"; + + port { + ltdc_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; +}; + +&m_can1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&m_can1_pins_a>; + pinctrl-1 =3D <&m_can1_sleep_pins_a>; + status =3D "okay"; +}; + +&sai1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sai1a_pins_a>, <&sai1b_pins_a>; + pinctrl-1 =3D <&sai1a_sleep_pins_a>, <&sai1b_sleep_pins_a>; + status =3D "okay"; +}; + +&sai1a { + dma-names =3D "tx"; + status =3D "okay"; + + sai1a_port: port { + sai1a_endpoint: endpoint { + remote-endpoint =3D <&sgtl5000_tx_endpoint>; + dai-format =3D "i2s"; + mclk-fs =3D <512>; + }; + }; +}; + +&sai1b { + dma-names =3D "rx"; + st,sync =3D <&sai1a 2>; + clocks =3D <&rcc CK_KER_SAI1>; + clock-names =3D "sai_ck"; + status =3D "okay"; + + sai1b_port: port { + sai1b_endpoint: endpoint { + remote-endpoint =3D <&sgtl5000_rx_endpoint>; + dai-format =3D "i2s"; + mclk-fs =3D <512>; + }; + }; +}; + +/* MicroSD */ +&sdmmc1 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc1_b4_pins_a>; + pinctrl-1 =3D <&sdmmc1_b4_od_pins_a>; + pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + disable-wp; + st,neg-edge; + bus-width =3D <4>; + vmmc-supply =3D <&scmi_v3v3>; + vqmmc-supply =3D <&scmi_vddio1>; + no-1-8-v; + status =3D "okay"; +}; + +&spi1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi1_pins_a>; + pinctrl-1 =3D <&spi1_sleep_pins_a>; + #address-cells =3D <1>; + #size-cells =3D <0>; + cs-gpios =3D <&gpioh 8 GPIO_ACTIVE_HIGH>, <&gpioh 3 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + display: display@0 { + compatible =3D "rocktech,rk050hr345-ct106a", "ilitek,ili9806e"; + reg =3D <0>; + vdd-supply =3D <®_3v3>; + spi-max-frequency =3D <10000000>; + reset-gpios =3D <&gpiob 6 GPIO_ACTIVE_LOW>; + backlight =3D <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint =3D <<dc_out>; + }; + }; + }; +}; + +&timers2 { + status =3D "okay"; + + pwm2: pwm { + pinctrl-0 =3D <&pwm2_pins_a>; + pinctrl-1 =3D <&pwm2_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; +}; + +&timers4 { + status =3D "okay"; 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Fri, 29 May 2026 07:47:41 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.43.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909d6eb470sm38694785e9.10.2026.05.29.07.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 07:47:40 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, francesco.utel@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Arnd Bergmann , Bjorn Andersson , Dmitry Baryshkov , Eric Biggers , Geert Uytterhoeven , Krzysztof Kozlowski , Luca Weiss , Michal Simek , Sven Peter Subject: [PATCH v2 14/15] arm64: defconfig: cleanup the defconfig Date: Fri, 29 May 2026 16:46:28 +0200 Message-ID: <20260529144707.3931919-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> References: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Cleanup defconfig by doing: make defconfig make savedefconfig cp defconfig arch/arm64/configs/defconfig No functional change. The goal here is to cleanup defconfig file to make easier and cleaner the addition of new entries. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/configs/defconfig | 289 +++++++++++++---------------------- 1 file changed, 107 insertions(+), 182 deletions(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d905a0777f93..89730d2ec954 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,7 +32,6 @@ CONFIG_KALLSYMS_ALL=3Dy CONFIG_PROFILING=3Dy CONFIG_KEXEC=3Dy CONFIG_KEXEC_FILE=3Dy -CONFIG_CRASH_DUMP=3Dy CONFIG_ARCH_ACTIONS=3Dy CONFIG_ARCH_AIROHA=3Dy CONFIG_ARCH_SUNXI=3Dy @@ -50,7 +49,6 @@ CONFIG_ARCH_BLAIZE=3Dy CONFIG_ARCH_BST=3Dy CONFIG_ARCH_CIX=3Dy CONFIG_ARCH_EXYNOS=3Dy -CONFIG_ARCH_SPARX5=3Dy CONFIG_ARCH_K3=3Dy CONFIG_ARCH_LG1K=3Dy CONFIG_ARCH_HISI=3Dy @@ -58,6 +56,7 @@ CONFIG_ARCH_KEEMBAY=3Dy CONFIG_ARCH_MEDIATEK=3Dy CONFIG_ARCH_MESON=3Dy CONFIG_ARCH_MICROCHIP=3Dy +CONFIG_ARCH_SPARX5=3Dy CONFIG_ARCH_MVEBU=3Dy CONFIG_ARCH_NXP=3Dy CONFIG_ARCH_LAYERSCAPE=3Dy @@ -99,7 +98,6 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=3Dy CONFIG_CPU_FREQ_GOV_ONDEMAND=3Dy CONFIG_CPU_FREQ_GOV_CONSERVATIVE=3Dm CONFIG_CPUFREQ_DT=3Dy -CONFIG_ACPI_CPPC_CPUFREQ=3Dm CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=3Dm CONFIG_ARM_APPLE_SOC_CPUFREQ=3Dm CONFIG_ARM_ARMADA_37XX_CPUFREQ=3Dy @@ -112,6 +110,7 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=3Dm CONFIG_ARM_SCMI_CPUFREQ=3Dy CONFIG_ARM_TEGRA186_CPUFREQ=3Dy CONFIG_QORIQ_CPUFREQ=3Dy +CONFIG_ACPI_CPPC_CPUFREQ=3Dm CONFIG_ACPI=3Dy CONFIG_ACPI_HOTPLUG_MEMORY=3Dy CONFIG_ACPI_HMAT=3Dy @@ -122,10 +121,9 @@ CONFIG_ACPI_APEI_MEMORY_FAILURE=3Dy CONFIG_ACPI_APEI_EINJ=3Dy CONFIG_VIRTUALIZATION=3Dy CONFIG_KVM=3Dy -CONFIG_JUMP_LABEL=3Dy CONFIG_MODULES=3Dy CONFIG_MODULE_UNLOAD=3Dy -CONFIG_IOSCHED_BFQ=3Dy +CONFIG_BLK_INLINE_ENCRYPTION=3Dy # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_COMPAT_BRK is not set CONFIG_MEMORY_HOTPLUG=3Dy @@ -135,36 +133,22 @@ CONFIG_MEMORY_FAILURE=3Dy CONFIG_TRANSPARENT_HUGEPAGE=3Dy CONFIG_NET=3Dy CONFIG_PACKET=3Dy -CONFIG_UNIX=3Dy -CONFIG_INET=3Dy CONFIG_IP_MULTICAST=3Dy CONFIG_IP_PNP=3Dy CONFIG_IP_PNP_DHCP=3Dy CONFIG_IP_PNP_BOOTP=3Dy -CONFIG_IPV6=3Dy CONFIG_NETFILTER=3Dy CONFIG_BRIDGE_NETFILTER=3Dm CONFIG_NF_CONNTRACK=3Dm CONFIG_NF_CONNTRACK_EVENTS=3Dy CONFIG_NETFILTER_XT_MARK=3Dm -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=3Dm CONFIG_NETFILTER_XT_TARGET_LOG=3Dm CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=3Dm CONFIG_NETFILTER_XT_MATCH_CONNTRACK=3Dm CONFIG_NETFILTER_XT_MATCH_IPVS=3Dm CONFIG_IP_VS=3Dm CONFIG_IP_NF_IPTABLES=3Dm -CONFIG_IP_NF_FILTER=3Dm -CONFIG_IP_NF_TARGET_REJECT=3Dm -CONFIG_IP_NF_NAT=3Dm -CONFIG_IP_NF_TARGET_MASQUERADE=3Dm -CONFIG_IP_NF_MANGLE=3Dm CONFIG_IP6_NF_IPTABLES=3Dm -CONFIG_IP6_NF_FILTER=3Dm -CONFIG_IP6_NF_TARGET_REJECT=3Dm -CONFIG_IP6_NF_MANGLE=3Dm -CONFIG_IP6_NF_NAT=3Dm -CONFIG_IP6_NF_TARGET_MASQUERADE=3Dm CONFIG_BRIDGE=3Dm CONFIG_BRIDGE_VLAN_FILTERING=3Dy CONFIG_NET_DSA=3Dm @@ -182,8 +166,8 @@ CONFIG_NET_CLS_FLOWER=3Dm CONFIG_NET_CLS_ACT=3Dy CONFIG_NET_ACT_GACT=3Dm CONFIG_NET_ACT_MIRRED=3Dm -CONFIG_HSR=3Dm CONFIG_NET_ACT_GATE=3Dm +CONFIG_HSR=3Dm CONFIG_QRTR_SMD=3Dm CONFIG_QRTR_TUN=3Dm CONFIG_CAN=3Dm @@ -205,7 +189,6 @@ CONFIG_BT_QCOMSMD=3Dm CONFIG_BT_NXPUART=3Dm CONFIG_CFG80211=3Dm CONFIG_MAC80211=3Dm -CONFIG_MAC80211_LEDS=3Dy CONFIG_RFKILL=3Dm CONFIG_RFKILL_GPIO=3Dm CONFIG_NET_9P=3Dy @@ -259,14 +242,13 @@ CONFIG_PCIE_LAYERSCAPE_GEN4=3Dy CONFIG_PCI_ENDPOINT=3Dy CONFIG_PCI_ENDPOINT_CONFIGFS=3Dy CONFIG_PCI_EPF_TEST=3Dm -CONFIG_PCI_PWRCTRL_GENERIC=3Dm CONFIG_DEVTMPFS=3Dy CONFIG_DEVTMPFS_MOUNT=3Dy CONFIG_FW_LOADER_USER_HELPER=3Dy CONFIG_HISILICON_LPC=3Dy +CONFIG_IMX_AIPSTZ=3Dm CONFIG_TEGRA_ACONNECT=3Dm CONFIG_MHI_BUS_PCI_GENERIC=3Dm -CONFIG_ARM_SCMI_PROTOCOL=3Dy CONFIG_ARM_SCPI_PROTOCOL=3Dy CONFIG_RASPBERRYPI_FIRMWARE=3Dy CONFIG_INTEL_STRATIX10_SERVICE=3Dy @@ -276,7 +258,6 @@ CONFIG_GOOGLE_FIRMWARE=3Dy CONFIG_GOOGLE_CBMEM=3Dm CONFIG_GOOGLE_COREBOOT_TABLE=3Dm CONFIG_EFI_CAPSULE_LOADER=3Dy -CONFIG_IMX_AIPSTZ=3Dm CONFIG_IMX_SCU=3Dy CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE=3Dy CONFIG_QCOM_QSEECOM=3Dy @@ -303,11 +284,12 @@ CONFIG_MTD_NAND_MARVELL=3Dy CONFIG_MTD_NAND_BRCMNAND=3Dm CONFIG_MTD_NAND_FSL_IFC=3Dy CONFIG_MTD_NAND_QCOM=3Dy -CONFIG_MTD_SPI_NOR=3Dy CONFIG_MTD_SPI_NAND=3Dm +CONFIG_MTD_SPI_NOR=3Dy CONFIG_MTD_UBI=3Dm CONFIG_MTD_HYPERBUS=3Dm CONFIG_HBMC_AM654=3Dm +CONFIG_OF_OVERLAY=3Dy CONFIG_BLK_DEV_LOOP=3Dy CONFIG_BLK_DEV_NBD=3Dm CONFIG_VIRTIO_BLK=3Dy @@ -321,6 +303,7 @@ CONFIG_XILINX_SDFEC=3Dm CONFIG_EEPROM_AT24=3Dm CONFIG_EEPROM_AT25=3Dm CONFIG_UACCE=3Dm +CONFIG_MISC_RP1=3Dm # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=3Dy CONFIG_SCSI_SAS_ATA=3Dy @@ -339,7 +322,6 @@ CONFIG_AHCI_XGENE=3Dy CONFIG_AHCI_QORIQ=3Dy CONFIG_SATA_SIL24=3Dy CONFIG_SATA_RCAR=3Dy -CONFIG_PATA_PLATFORM=3Dy CONFIG_PATA_OF_PLATFORM=3Dy CONFIG_MD=3Dy CONFIG_BLK_DEV_MD=3Dm @@ -423,8 +405,8 @@ CONFIG_REALTEK_PHY=3Dy CONFIG_ROCKCHIP_PHY=3Dy CONFIG_DP83867_PHY=3Dy CONFIG_DP83869_PHY=3Dm -CONFIG_DP83TG720_PHY=3Dm CONFIG_DP83TD510_PHY=3Dy +CONFIG_DP83TG720_PHY=3Dm CONFIG_VITESSE_PHY=3Dy CONFIG_XILINX_GMII2RGMII=3Dm CONFIG_CAN_FLEXCAN=3Dm @@ -563,7 +545,6 @@ CONFIG_I2C_MUX_PINCTRL=3Dm CONFIG_I2C_BCM2835=3Dm CONFIG_I2C_CADENCE=3Dm CONFIG_I2C_DESIGNWARE_CORE=3Dy -CONFIG_I2C_DESIGNWARE_PLATFORM=3Dy CONFIG_I2C_GPIO=3Dm CONFIG_I2C_IMX=3Dy CONFIG_I2C_IMX_LPI2C=3Dy @@ -630,8 +611,6 @@ CONFIG_SPMI=3Dy CONFIG_SPMI_APPLE=3Dm CONFIG_SPMI_MTK_PMIF=3Dm CONFIG_PINCTRL_APPLE_GPIO=3Dm -CONFIG_PINCTRL_BRCMSTB=3Dy -CONFIG_PINCTRL_BCM2712=3Dy CONFIG_PINCTRL_DA9062=3Dm CONFIG_PINCTRL_MAX77620=3Dy CONFIG_PINCTRL_RK805=3Dm @@ -640,17 +619,10 @@ CONFIG_PINCTRL_SX150X=3Dm CONFIG_PINCTRL_OWL=3Dy CONFIG_PINCTRL_S700=3Dy CONFIG_PINCTRL_S900=3Dy -CONFIG_PINCTRL_IMX8MM=3Dy -CONFIG_PINCTRL_IMX8MN=3Dy -CONFIG_PINCTRL_IMX8MP=3Dy -CONFIG_PINCTRL_IMX8MQ=3Dy -CONFIG_PINCTRL_IMX8QM=3Dy -CONFIG_PINCTRL_IMX8QXP=3Dy -CONFIG_PINCTRL_IMX8DXL=3Dy -CONFIG_PINCTRL_IMX8ULP=3Dy -CONFIG_PINCTRL_IMX91=3Dy -CONFIG_PINCTRL_IMX93=3Dy +CONFIG_PINCTRL_BRCMSTB=3Dy +CONFIG_PINCTRL_BCM2712=3Dy CONFIG_PINCTRL_IMX_SCMI=3Dy +CONFIG_PINCTRL_IMX91=3Dy CONFIG_PINCTRL_MSM=3Dy CONFIG_PINCTRL_ELIZA=3Dy CONFIG_PINCTRL_GLYMUR=3Dy @@ -674,7 +646,6 @@ CONFIG_PINCTRL_QCS615=3Dy CONFIG_PINCTRL_QCS8300=3Dy CONFIG_PINCTRL_QDF2XXX=3Dy CONFIG_PINCTRL_QDU1000=3Dy -CONFIG_PINCTRL_RP1=3Dm CONFIG_PINCTRL_SA8775P=3Dy CONFIG_PINCTRL_SC7180=3Dy CONFIG_PINCTRL_SC7280=3Dy @@ -719,9 +690,9 @@ CONFIG_GPIO_PL061=3Dy CONFIG_GPIO_RCAR=3Dy CONFIG_GPIO_SYSCON=3Dy CONFIG_GPIO_UNIPHIER=3Dy +CONFIG_GPIO_VF610=3Dy CONFIG_GPIO_VISCONTI=3Dy CONFIG_GPIO_WCD934X=3Dm -CONFIG_GPIO_VF610=3Dy CONFIG_GPIO_XGENE=3Dy CONFIG_GPIO_XGENE_SB=3Dy CONFIG_GPIO_XILINX=3Dm @@ -729,9 +700,9 @@ CONFIG_GPIO_ZYNQ=3Dm CONFIG_GPIO_MAX732X=3Dy CONFIG_GPIO_PCA953X=3Dy CONFIG_GPIO_PCA953X_IRQ=3Dy -CONFIG_GPIO_ADP5585=3Dm CONFIG_GPIO_PCF857X=3Dm CONFIG_GPIO_TPIC2810=3Dm +CONFIG_GPIO_ADP5585=3Dm CONFIG_GPIO_BD9571MWV=3Dm CONFIG_GPIO_MACSMC=3Dm CONFIG_GPIO_MAX77620=3Dy @@ -770,7 +741,6 @@ CONFIG_SENSORS_AMC6821=3Dm CONFIG_SENSORS_INA2XX=3Dm CONFIG_SENSORS_INA3221=3Dm CONFIG_SENSORS_TMP102=3Dm -CONFIG_MISC_RP1=3Dm CONFIG_THERMAL_GOV_POWER_ALLOCATOR=3Dy CONFIG_CPU_THERMAL=3Dy CONFIG_DEVFREQ_THERMAL=3Dy @@ -781,11 +751,6 @@ CONFIG_K3_THERMAL=3Dm CONFIG_QORIQ_THERMAL=3Dm CONFIG_SUN8I_THERMAL=3Dy CONFIG_ROCKCHIP_THERMAL=3Dm -CONFIG_RCAR_THERMAL=3Dy -CONFIG_RCAR_GEN3_THERMAL=3Dy -CONFIG_RZG2L_THERMAL=3Dy -CONFIG_RZG3E_THERMAL=3Dy -CONFIG_RZG3S_THERMAL=3Dm CONFIG_ARMADA_THERMAL=3Dy CONFIG_MTK_THERMAL=3Dm CONFIG_MTK_LVTS_THERMAL=3Dm @@ -793,6 +758,11 @@ CONFIG_BCM2711_THERMAL=3Dm CONFIG_BCM2835_THERMAL=3Dm CONFIG_BRCMSTB_THERMAL=3Dm CONFIG_EXYNOS_THERMAL=3Dy +CONFIG_RCAR_THERMAL=3Dy +CONFIG_RCAR_GEN3_THERMAL=3Dy +CONFIG_RZG2L_THERMAL=3Dy +CONFIG_RZG3E_THERMAL=3Dy +CONFIG_RZG3S_THERMAL=3Dm CONFIG_TEGRA_SOCTHERM=3Dm CONFIG_TEGRA_BPMP_THERMAL=3Dm CONFIG_GENERIC_ADC_THERMAL=3Dm @@ -918,10 +888,10 @@ CONFIG_SDR_PLATFORM_DRIVERS=3Dy CONFIG_V4L_MEM2MEM_DRIVERS=3Dy CONFIG_VIDEO_AMPHION_VPU=3Dm CONFIG_VIDEO_CADENCE_CSI2RX=3Dm -CONFIG_VIDEO_MEDIATEK_JPEG=3Dm -CONFIG_VIDEO_MEDIATEK_VCODEC=3Dm CONFIG_VIDEO_WAVE_VPU=3Dm CONFIG_VIDEO_E5010_JPEG_ENC=3Dm +CONFIG_VIDEO_MEDIATEK_JPEG=3Dm +CONFIG_VIDEO_MEDIATEK_VCODEC=3Dm CONFIG_VIDEO_MEDIATEK_MDP3=3Dm CONFIG_VIDEO_IMX7_CSI=3Dm CONFIG_VIDEO_IMX_MIPI_CSIS=3Dm @@ -931,8 +901,8 @@ CONFIG_VIDEO_IMX8_JPEG=3Dm CONFIG_VIDEO_QCOM_CAMSS=3Dm CONFIG_VIDEO_QCOM_IRIS=3Dm CONFIG_VIDEO_QCOM_VENUS=3Dm -CONFIG_VIDEO_RCAR_ISP=3Dm CONFIG_VIDEO_RCAR_CSI2=3Dm +CONFIG_VIDEO_RCAR_ISP=3Dm CONFIG_VIDEO_RCAR_VIN=3Dm CONFIG_VIDEO_RZG2L_CSI2=3Dm CONFIG_VIDEO_RZG2L_CRU=3Dm @@ -940,8 +910,8 @@ CONFIG_VIDEO_RENESAS_FCP=3Dm CONFIG_VIDEO_RENESAS_FDP1=3Dm CONFIG_VIDEO_RENESAS_VSP1=3Dm CONFIG_VIDEO_RCAR_DRIF=3Dm -CONFIG_VIDEO_ROCKCHIP_CIF=3Dm CONFIG_VIDEO_ROCKCHIP_RGA=3Dm +CONFIG_VIDEO_ROCKCHIP_CIF=3Dm CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=3Dm CONFIG_VIDEO_SAMSUNG_S5P_JPEG=3Dm CONFIG_VIDEO_SAMSUNG_S5P_MFC=3Dm @@ -956,64 +926,11 @@ CONFIG_VIDEO_OV5640=3Dm CONFIG_VIDEO_OV5645=3Dm CONFIG_VIDEO_S5KJN1=3Dm CONFIG_DRM=3Dm -CONFIG_DRM_I2C_NXP_TDA998X=3Dm CONFIG_DRM_HDLCD=3Dm CONFIG_DRM_MALI_DISPLAY=3Dm CONFIG_DRM_KOMEDA=3Dm -CONFIG_DRM_NOUVEAU=3Dm -CONFIG_DRM_EXYNOS=3Dm -CONFIG_DRM_EXYNOS5433_DECON=3Dy -CONFIG_DRM_EXYNOS7_DECON=3Dy -CONFIG_DRM_EXYNOS_DSI=3Dy -# CONFIG_DRM_EXYNOS_DP is not set -CONFIG_DRM_EXYNOS_HDMI=3Dy -CONFIG_DRM_EXYNOS_MIC=3Dy -CONFIG_DRM_ROCKCHIP=3Dm -CONFIG_ROCKCHIP_VOP2=3Dy -CONFIG_ROCKCHIP_ANALOGIX_DP=3Dy -CONFIG_ROCKCHIP_CDN_DP=3Dy -CONFIG_ROCKCHIP_DW_DP=3Dy -CONFIG_ROCKCHIP_DW_HDMI=3Dy -CONFIG_ROCKCHIP_DW_HDMI_QP=3Dy -CONFIG_ROCKCHIP_DW_MIPI_DSI=3Dy -CONFIG_ROCKCHIP_INNO_HDMI=3Dy -CONFIG_ROCKCHIP_LVDS=3Dy -CONFIG_DRM_RCAR_DU=3Dm -CONFIG_DRM_RCAR_DW_HDMI=3Dm -CONFIG_DRM_RCAR_MIPI_DSI=3Dm -CONFIG_DRM_RZG2L_MIPI_DSI=3Dm -CONFIG_DRM_RZG2L_DU=3Dm -CONFIG_DRM_SUN4I=3Dm -CONFIG_DRM_SUN6I_DSI=3Dm -CONFIG_DRM_SUN8I_DW_HDMI=3Dm -CONFIG_DRM_SUN8I_MIXER=3Dm -CONFIG_DRM_MSM=3Dm -CONFIG_DRM_TEGRA=3Dm -CONFIG_DRM_STM=3Dm -CONFIG_DRM_STM_LVDS=3Dm -CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=3Dm -CONFIG_DRM_PANEL_LVDS=3Dm -CONFIG_DRM_PANEL_SIMPLE=3Dm -CONFIG_DRM_PANEL_SUMMIT=3Dm -CONFIG_DRM_PANEL_EDP=3Dm -CONFIG_DRM_PANEL_HIMAX_HX8279=3Dm -CONFIG_DRM_PANEL_HIMAX_HX83112A=3Dm -CONFIG_DRM_PANEL_HIMAX_HX83112B=3Dm -CONFIG_DRM_PANEL_ILITEK_ILI9882T=3Dm -CONFIG_DRM_PANEL_KHADAS_TS050=3Dm -CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=3Dm -CONFIG_DRM_PANEL_NOVATEK_NT36672A=3Dm -CONFIG_DRM_PANEL_NOVATEK_NT36672E=3Dm -CONFIG_DRM_PANEL_NOVATEK_NT37801=3Dm -CONFIG_DRM_PANEL_RAYDIUM_RM67191=3Dm -CONFIG_DRM_PANEL_RAYDIUM_RM692E5=3Dm -CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=3Dm -CONFIG_DRM_PANEL_SITRONIX_ST7703=3Dm -CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=3Dm -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=3Dm -CONFIG_DRM_PANEL_VISIONOX_VTDR6130=3Dm -CONFIG_DRM_DISPLAY_CONNECTOR=3Dm CONFIG_DRM_FSL_LDB=3Dm +CONFIG_DRM_I2C_NXP_TDA998X=3Dm CONFIG_DRM_ITE_IT6263=3Dm CONFIG_DRM_LONTIUM_LT8912B=3Dm CONFIG_DRM_LONTIUM_LT9611=3Dm @@ -1022,7 +939,6 @@ CONFIG_DRM_LONTIUM_LT8713SX=3Dm CONFIG_DRM_ITE_IT66121=3Dm CONFIG_DRM_NWL_MIPI_DSI=3Dm CONFIG_DRM_PARADE_PS8640=3Dm -CONFIG_DRM_SAMSUNG_DSIM=3Dm CONFIG_DRM_SII902X=3Dm CONFIG_DRM_SIMPLE_BRIDGE=3Dm CONFIG_DRM_THINE_THC63LVD1024=3Dm @@ -1040,38 +956,82 @@ CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=3Dm CONFIG_DRM_DW_HDMI_AHB_AUDIO=3Dm CONFIG_DRM_DW_HDMI_CEC=3Dm CONFIG_DRM_DW_HDMI_QP_CEC=3Dy -CONFIG_DRM_IMX_DCSS=3Dm -CONFIG_DRM_V3D=3Dm -CONFIG_DRM_VC4=3Dm CONFIG_DRM_ETNAVIV=3Dm +CONFIG_DRM_EXYNOS=3Dm +CONFIG_DRM_EXYNOS5433_DECON=3Dy +CONFIG_DRM_EXYNOS7_DECON=3Dy +CONFIG_DRM_EXYNOS_DSI=3Dy +# CONFIG_DRM_EXYNOS_DP is not set +CONFIG_DRM_EXYNOS_HDMI=3Dy +CONFIG_DRM_EXYNOS_MIC=3Dy CONFIG_DRM_HISI_HIBMC=3Dm CONFIG_DRM_HISI_KIRIN=3Dm +CONFIG_DRM_POWERVR=3Dm +CONFIG_DRM_IMX_DCSS=3Dm +CONFIG_DRM_LIMA=3Dm CONFIG_DRM_MEDIATEK=3Dm CONFIG_DRM_MEDIATEK_DP=3Dm CONFIG_DRM_MEDIATEK_HDMI=3Dm CONFIG_DRM_MEDIATEK_HDMI_V2=3Dm +CONFIG_DRM_MESON=3Dm +CONFIG_DRM_MSM=3Dm CONFIG_DRM_MXSFB=3Dm CONFIG_DRM_IMX_LCDIF=3Dm -CONFIG_DRM_MESON=3Dm -CONFIG_DRM_PL111=3Dm -CONFIG_DRM_LIMA=3Dm +CONFIG_DRM_NOUVEAU=3Dm +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=3Dm +CONFIG_DRM_PANEL_LVDS=3Dm +CONFIG_DRM_PANEL_HIMAX_HX8279=3Dm +CONFIG_DRM_PANEL_HIMAX_HX83112A=3Dm +CONFIG_DRM_PANEL_HIMAX_HX83112B=3Dm +CONFIG_DRM_PANEL_ILITEK_ILI9882T=3Dm +CONFIG_DRM_PANEL_KHADAS_TS050=3Dm +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=3Dm +CONFIG_DRM_PANEL_NOVATEK_NT36672A=3Dm +CONFIG_DRM_PANEL_NOVATEK_NT36672E=3Dm +CONFIG_DRM_PANEL_NOVATEK_NT37801=3Dm +CONFIG_DRM_PANEL_RAYDIUM_RM67191=3Dm +CONFIG_DRM_PANEL_RAYDIUM_RM692E5=3Dm +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=3Dm +CONFIG_DRM_PANEL_SITRONIX_ST7703=3Dm +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=3Dm +CONFIG_DRM_PANEL_EDP=3Dm +CONFIG_DRM_PANEL_SIMPLE=3Dm +CONFIG_DRM_PANEL_SUMMIT=3Dm +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=3Dm +CONFIG_DRM_PANEL_VISIONOX_VTDR6130=3Dm CONFIG_DRM_PANFROST=3Dm CONFIG_DRM_PANTHOR=3Dm +CONFIG_DRM_PL111=3Dm +CONFIG_DRM_RCAR_DU=3Dm +CONFIG_DRM_RCAR_DW_HDMI=3Dm +CONFIG_DRM_RZG2L_DU=3Dm +CONFIG_DRM_ROCKCHIP=3Dm +CONFIG_ROCKCHIP_VOP2=3Dy +CONFIG_ROCKCHIP_ANALOGIX_DP=3Dy +CONFIG_ROCKCHIP_CDN_DP=3Dy +CONFIG_ROCKCHIP_DW_DP=3Dy +CONFIG_ROCKCHIP_DW_HDMI=3Dy +CONFIG_ROCKCHIP_DW_HDMI_QP=3Dy +CONFIG_ROCKCHIP_DW_MIPI_DSI=3Dy +CONFIG_ROCKCHIP_INNO_HDMI=3Dy +CONFIG_ROCKCHIP_LVDS=3Dy +CONFIG_DRM_STM=3Dm +CONFIG_DRM_STM_LVDS=3Dm +CONFIG_DRM_SUN4I=3Dm +CONFIG_DRM_TEGRA=3Dm CONFIG_DRM_TIDSS=3Dm +CONFIG_DRM_V3D=3Dm +CONFIG_DRM_VC4=3Dm CONFIG_DRM_ZYNQMP_DPSUB=3Dm CONFIG_DRM_ZYNQMP_DPSUB_AUDIO=3Dy -CONFIG_DRM_POWERVR=3Dm CONFIG_FB=3Dy CONFIG_FB_EFI=3Dy -CONFIG_FB_MODE_HELPERS=3Dy CONFIG_BACKLIGHT_PWM=3Dm CONFIG_BACKLIGHT_APPLE_DWI=3Dm CONFIG_BACKLIGHT_QCOM_WLED=3Dm CONFIG_BACKLIGHT_LP855X=3Dm CONFIG_BACKLIGHT_GPIO=3Dm CONFIG_LOGO=3Dy -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_SOUND=3Dm CONFIG_SND=3Dm CONFIG_SND_ALOOP=3Dm @@ -1113,21 +1073,15 @@ CONFIG_SND_SOC_SC8280XP=3Dm CONFIG_SND_SOC_SC7180=3Dm CONFIG_SND_SOC_SC7280=3Dm CONFIG_SND_SOC_X1E80100=3Dm -CONFIG_SND_SOC_ROCKCHIP=3Dm +CONFIG_SND_SOC_RCAR=3Dm +CONFIG_SND_SOC_MSIOF=3Dm +CONFIG_SND_SOC_RZ=3Dm CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=3Dm CONFIG_SND_SOC_ROCKCHIP_SAI=3Dm CONFIG_SND_SOC_ROCKCHIP_SPDIF=3Dm CONFIG_SND_SOC_ROCKCHIP_RT5645=3Dm CONFIG_SND_SOC_RK3399_GRU_SOUND=3Dm -CONFIG_SND_SOC_RCAR=3Dm -CONFIG_SND_SOC_MSIOF=3Dm -CONFIG_SND_SOC_RZ=3Dm CONFIG_SND_SOC_SAMSUNG=3Dm -CONFIG_SND_SOC_SOF_TOPLEVEL=3Dy -CONFIG_SND_SOC_SOF_OF=3Dm -CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=3Dy -CONFIG_SND_SOC_SOF_MT8186=3Dm -CONFIG_SND_SOC_SOF_MT8195=3Dm CONFIG_SND_SUN8I_CODEC=3Dm CONFIG_SND_SUN8I_CODEC_ANALOG=3Dm CONFIG_SND_SUN50I_CODEC_ANALOG=3Dm @@ -1147,11 +1101,15 @@ CONFIG_SND_SOC_TEGRA210_AMX=3Dm CONFIG_SND_SOC_TEGRA210_ADX=3Dm CONFIG_SND_SOC_TEGRA210_MIXER=3Dm CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=3Dm -CONFIG_SND_SOC_DAVINCI_MCASP=3Dm CONFIG_SND_SOC_J721E_EVM=3Dm CONFIG_SND_SOC_XILINX_I2S=3Dm CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=3Dm CONFIG_SND_SOC_XILINX_SPDIF=3Dm +CONFIG_SND_SOC_SOF_TOPLEVEL=3Dy +CONFIG_SND_SOC_SOF_OF=3Dm +CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=3Dy +CONFIG_SND_SOC_SOF_MT8186=3Dm +CONFIG_SND_SOC_SOF_MT8195=3Dm CONFIG_SND_SOC_AK4613=3Dm CONFIG_SND_SOC_AK4619=3Dm CONFIG_SND_SOC_DA7213=3Dm @@ -1163,7 +1121,6 @@ CONFIG_SND_SOC_GTM601=3Dm CONFIG_SND_SOC_MAX98090=3Dm CONFIG_SND_SOC_MSM8916_WCD_ANALOG=3Dm CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=3Dm -CONFIG_SND_SOC_PCM3168A_I2C=3Dm CONFIG_SND_SOC_RK3308=3Dm CONFIG_SND_SOC_RK817=3Dm CONFIG_SND_SOC_RT5640=3Dm @@ -1189,8 +1146,6 @@ CONFIG_SND_SOC_WSA884X=3Dm CONFIG_SND_SOC_NAU8822=3Dm CONFIG_SND_SOC_LPASS_WSA_MACRO=3Dm CONFIG_SND_SOC_LPASS_VA_MACRO=3Dm -CONFIG_SND_SOC_LPASS_RX_MACRO=3Dm -CONFIG_SND_SOC_LPASS_TX_MACRO=3Dm CONFIG_SND_SIMPLE_CARD=3Dm CONFIG_SND_AUDIO_GRAPH_CARD=3Dm CONFIG_SND_AUDIO_GRAPH_CARD2=3Dm @@ -1220,12 +1175,10 @@ CONFIG_USB_CDNS_SUPPORT=3Dm CONFIG_USB_CDNS3=3Dm CONFIG_USB_CDNS3_GADGET=3Dy CONFIG_USB_CDNS3_HOST=3Dy -CONFIG_USB_CDNS3_IMX=3Dm CONFIG_USB_MTU3=3Dy CONFIG_USB_MUSB_HDRC=3Dy CONFIG_USB_MUSB_SUNXI=3Dy CONFIG_USB_DWC3=3Dy -CONFIG_OMAP_USB2=3Dm CONFIG_USB_DWC2=3Dy CONFIG_USB_CHIPIDEA=3Dy CONFIG_USB_CHIPIDEA_UDC=3Dy @@ -1311,6 +1264,7 @@ CONFIG_MMC_SDHCI_AM654=3Dy CONFIG_MMC_OWL=3Dy CONFIG_SCSI_UFSHCD=3Dy CONFIG_SCSI_UFS_BSG=3Dy +CONFIG_SCSI_UFS_CRYPTO=3Dy CONFIG_SCSI_UFSHCD_PLATFORM=3Dy CONFIG_SCSI_UFS_CDNS_PLATFORM=3Dm CONFIG_SCSI_UFS_QCOM=3Dm @@ -1320,9 +1274,6 @@ CONFIG_SCSI_UFS_RENESAS=3Dm CONFIG_SCSI_UFS_TI_J721E=3Dm CONFIG_SCSI_UFS_EXYNOS=3Dy CONFIG_SCSI_UFS_ROCKCHIP=3Dy -CONFIG_BLK_INLINE_ENCRYPTION=3Dy -CONFIG_SCSI_UFS_CRYPTO=3Dy -CONFIG_NEW_LEDS=3Dy CONFIG_LEDS_CLASS=3Dy CONFIG_LEDS_CLASS_FLASH=3Dm CONFIG_LEDS_CLASS_MULTICOLOR=3Dm @@ -1348,9 +1299,9 @@ CONFIG_RTC_CLASS=3Dy CONFIG_RTC_DRV_DS1307=3Dm CONFIG_RTC_DRV_HYM8563=3Dm CONFIG_RTC_DRV_MAX77686=3Dy +CONFIG_RTC_DRV_NVIDIA_VRS10=3Dm CONFIG_RTC_DRV_RK808=3Dm CONFIG_RTC_DRV_ISL1208=3Dm -CONFIG_RTC_DRV_PCF85063=3Dm CONFIG_RTC_DRV_PCF85363=3Dm CONFIG_RTC_DRV_PCF8563=3Dm CONFIG_RTC_DRV_M41T80=3Dm @@ -1358,10 +1309,10 @@ CONFIG_RTC_DRV_BQ32K=3Dm CONFIG_RTC_DRV_RX8581=3Dm CONFIG_RTC_DRV_RV3028=3Dm CONFIG_RTC_DRV_RV8803=3Dm -CONFIG_RTC_DRV_S32G=3Dm CONFIG_RTC_DRV_S5M=3Dy CONFIG_RTC_DRV_DS3232=3Dy CONFIG_RTC_DRV_PCF2127=3Dm +CONFIG_RTC_DRV_PCF85063=3Dm CONFIG_RTC_DRV_DA9063=3Dm CONFIG_RTC_DRV_EFI=3Dy CONFIG_RTC_DRV_ZYNQMP=3Dm @@ -1380,8 +1331,8 @@ CONFIG_RTC_DRV_MT6397=3Dm CONFIG_RTC_DRV_XGENE=3Dy CONFIG_RTC_DRV_TI_K3=3Dm CONFIG_RTC_DRV_RENESAS_RTCA3=3Dm -CONFIG_RTC_DRV_NVIDIA_VRS10=3Dm CONFIG_RTC_DRV_MACSMC=3Dm +CONFIG_RTC_DRV_S32G=3Dm CONFIG_DMADEVICES=3Dy CONFIG_APPLE_ADMAC=3Dm CONFIG_DMA_BCM2835=3Dy @@ -1432,19 +1383,17 @@ CONFIG_CROS_EC_RPMSG=3Dm CONFIG_CROS_EC_SPI=3Dy CONFIG_CROS_KBD_LED_BACKLIGHT=3Dm CONFIG_CROS_EC_CHARDEV=3Dm -CONFIG_COMMON_CLK_APPLE_NCO=3Dm CONFIG_EC_ACER_ASPIRE1=3Dm CONFIG_EC_HUAWEI_GAOKUN=3Dm CONFIG_EC_LENOVO_YOGA_C630=3Dm CONFIG_EC_LENOVO_THINKPAD_T14S=3Dm +CONFIG_COMMON_CLK_APPLE_NCO=3Dm CONFIG_COMMON_CLK_RK808=3Dy -CONFIG_COMMON_CLK_SCMI=3Dy CONFIG_COMMON_CLK_SCPI=3Dy CONFIG_COMMON_CLK_CS2000_CP=3Dy CONFIG_COMMON_CLK_FSL_SAI=3Dy CONFIG_COMMON_CLK_S2MPS11=3Dy CONFIG_COMMON_CLK_PWM=3Dy -CONFIG_COMMON_CLK_RP1=3Dm CONFIG_COMMON_CLK_RS9_PCIE=3Dy CONFIG_COMMON_CLK_VC3=3Dy CONFIG_COMMON_CLK_VC5=3Dy @@ -1459,18 +1408,6 @@ CONFIG_CLK_IMX8ULP=3Dy CONFIG_CLK_IMX93=3Dy CONFIG_CLK_IMX95_BLK_CTL=3Dy CONFIG_TI_SCI_CLK=3Dy -CONFIG_COMMON_CLK_MT8192_AUDSYS=3Dy -CONFIG_COMMON_CLK_MT8192_CAMSYS=3Dy -CONFIG_COMMON_CLK_MT8192_IMGSYS=3Dy -CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=3Dy -CONFIG_COMMON_CLK_MT8192_IPESYS=3Dy -CONFIG_COMMON_CLK_MT8192_MDPSYS=3Dy -CONFIG_COMMON_CLK_MT8192_MFGCFG=3Dy -CONFIG_COMMON_CLK_MT8192_MMSYS=3Dy -CONFIG_COMMON_CLK_MT8192_MSDC=3Dy -CONFIG_COMMON_CLK_MT8192_SCP_ADSP=3Dy -CONFIG_COMMON_CLK_MT8192_VDECSYS=3Dy -CONFIG_COMMON_CLK_MT8192_VENCSYS=3Dy CONFIG_COMMON_CLK_QCOM=3Dy CONFIG_CLK_ELIZA_DISPCC=3Dm CONFIG_CLK_ELIZA_GCC=3Dy @@ -1497,7 +1434,6 @@ CONFIG_QCOM_CLK_APCC_MSM8996=3Dy CONFIG_QCOM_CLK_SMD_RPM=3Dy CONFIG_QCOM_CLK_RPMH=3Dy CONFIG_IPQ_APSS_6018=3Dy -CONFIG_IPQ_APSS_5018=3Dy CONFIG_IPQ_CMN_PLL=3Dm CONFIG_IPQ_GCC_5018=3Dy CONFIG_IPQ_GCC_5210=3Dy @@ -1521,17 +1457,16 @@ CONFIG_QCM_DISPCC_2290=3Dm CONFIG_QCS_DISPCC_615=3Dm CONFIG_QCS_CAMCC_615=3Dm CONFIG_QCS_GCC_404=3Dy -CONFIG_QCS_GCC_615=3Dy -CONFIG_QCS_GCC_8300=3Dy -CONFIG_SC_CAMCC_7280=3Dm CONFIG_SA_CAMCC_8775P=3Dm +CONFIG_QCS_GCC_8300=3Dy +CONFIG_QCS_GCC_615=3Dy CONFIG_QCS_GPUCC_615=3Dm CONFIG_QCS_VIDEOCC_615=3Dm -CONFIG_QDU_GCC_1000=3Dy +CONFIG_SC_CAMCC_7280=3Dm CONFIG_SC_CAMCC_8280XP=3Dm +CONFIG_SA_DISPCC_8775P=3Dm CONFIG_SC_DISPCC_7280=3Dm CONFIG_SC_DISPCC_8280XP=3Dm -CONFIG_SA_DISPCC_8775P=3Dm CONFIG_SA_GCC_8775P=3Dy CONFIG_SA_GPUCC_8775P=3Dm CONFIG_SC_GCC_7180=3Dy @@ -1544,6 +1479,7 @@ CONFIG_SC_LPASSCC_8280XP=3Dm CONFIG_SC_LPASS_CORECC_7280=3Dm CONFIG_SC_VIDEOCC_7280=3Dm CONFIG_SDM_CAMCC_845=3Dm +CONFIG_QDU_GCC_1000=3Dy CONFIG_SDM_GPUCC_845=3Dy CONFIG_SDM_VIDEOCC_845=3Dy CONFIG_SDM_DISPCC_845=3Dy @@ -1608,22 +1544,22 @@ CONFIG_RENESAS_OSTM=3Dy CONFIG_ARM_MHU=3Dy CONFIG_EXYNOS_MBOX=3Dm CONFIG_IMX_MBOX=3Dy -CONFIG_OMAP2PLUS_MBOX=3Dm CONFIG_PLATFORM_MHU=3Dy +CONFIG_OMAP2PLUS_MBOX=3Dm CONFIG_BCM2835_MBOX=3Dy CONFIG_QCOM_APCS_IPC=3Dy +CONFIG_TEGRA_HSP_MBOX=3Dy CONFIG_MTK_ADSP_MBOX=3Dm CONFIG_QCOM_CPUCP_MBOX=3Dm -CONFIG_TEGRA_HSP_MBOX=3Dy CONFIG_QCOM_IPCC=3Dy CONFIG_CIX_MBOX=3Dy -CONFIG_ROCKCHIP_IOMMU=3Dy -CONFIG_TEGRA_IOMMU_SMMU=3Dy CONFIG_ARM_SMMU=3Dy CONFIG_ARM_SMMU_V3=3Dy -CONFIG_MTK_IOMMU=3Dy CONFIG_QCOM_IOMMU=3Dy +CONFIG_ROCKCHIP_IOMMU=3Dy +CONFIG_TEGRA_IOMMU_SMMU=3Dy CONFIG_APPLE_DART=3Dm +CONFIG_MTK_IOMMU=3Dy CONFIG_REMOTEPROC=3Dy CONFIG_IMX_REMOTEPROC=3Dy CONFIG_MTK_SCP=3Dm @@ -1680,7 +1616,6 @@ CONFIG_IMX_SCU_PD=3Dy CONFIG_QCOM_CPR=3Dy CONFIG_QCOM_RPMHPD=3Dy CONFIG_QCOM_RPMPD=3Dy -CONFIG_ROCKCHIP_PM_DOMAINS=3Dy CONFIG_TI_SCI_PM_DOMAINS=3Dy CONFIG_ARM_IMX_BUS_DEVFREQ=3Dy CONFIG_ARM_IMX8M_DDRC_DEVFREQ=3Dm @@ -1727,9 +1662,9 @@ CONFIG_PWM_BCM2835=3Dm CONFIG_PWM_BRCMSTB=3Dm CONFIG_PWM_CROS_EC=3Dm CONFIG_PWM_IMX27=3Dm +CONFIG_PWM_MEDIATEK=3Dm CONFIG_PWM_MESON=3Dm CONFIG_PWM_MTK_DISP=3Dm -CONFIG_PWM_MEDIATEK=3Dm CONFIG_PWM_RENESAS_RCAR=3Dm CONFIG_PWM_RENESAS_RZG2L_GPT=3Dm CONFIG_PWM_RENESAS_RZ_MTU3=3Dm @@ -1757,10 +1692,10 @@ CONFIG_RESET_QCOM_PDC=3Dm CONFIG_RESET_RZG2L_USBPHY_CTRL=3Dy CONFIG_RESET_RZV2H_USB2PHY=3Dm CONFIG_RESET_TI_SCI=3Dy -CONFIG_PHY_SNPS_EUSB2=3Dm -CONFIG_PHY_XGENE=3Dy CONFIG_PHY_CAN_TRANSCEIVER=3Dm CONFIG_PHY_NXP_PTN3222=3Dm +CONFIG_PHY_SNPS_EUSB2=3Dm +CONFIG_PHY_XGENE=3Dy CONFIG_PHY_SUN4I_USB=3Dy CONFIG_PHY_CADENCE_TORRENT=3Dm CONFIG_PHY_CADENCE_DPHY=3Dm @@ -1811,6 +1746,7 @@ CONFIG_PHY_UNIPHIER_USB3=3Dy CONFIG_PHY_TEGRA_XUSB=3Dy CONFIG_PHY_AM654_SERDES=3Dm CONFIG_PHY_J721E_WIZ=3Dm +CONFIG_OMAP_USB2=3Dm CONFIG_PHY_XILINX_ZYNQMP=3Dm CONFIG_ARM_CCI_PMU=3Dm CONFIG_ARM_CCN=3Dm @@ -1854,7 +1790,6 @@ CONFIG_ALTERA_FREEZE_BRIDGE=3Dm CONFIG_XILINX_PR_DECOUPLER=3Dm CONFIG_FPGA_REGION=3Dm CONFIG_OF_FPGA_REGION=3Dm -CONFIG_OF_OVERLAY=3Dy CONFIG_FPGA_MGR_ZYNQMP_FPGA=3Dm CONFIG_FPGA_MGR_VERSAL_FPGA=3Dm CONFIG_TEE=3Dy @@ -1862,10 +1797,7 @@ CONFIG_OPTEE=3Dy CONFIG_QCOMTEE=3Dm CONFIG_MUX_GPIO=3Dm CONFIG_MUX_MMIO=3Dy -CONFIG_SLIMBUS=3Dm -CONFIG_SLIM_QCOM_CTRL=3Dm CONFIG_SLIM_QCOM_NGD_CTRL=3Dm -CONFIG_INTERCONNECT=3Dy CONFIG_INTERCONNECT_IMX=3Dy CONFIG_INTERCONNECT_IMX8MM=3Dm CONFIG_INTERCONNECT_IMX8MN=3Dm @@ -1903,9 +1835,9 @@ CONFIG_INTERCONNECT_QCOM_SM8650=3Dy CONFIG_INTERCONNECT_QCOM_SM8750=3Dy CONFIG_INTERCONNECT_QCOM_X1E80100=3Dy CONFIG_COUNTER=3Dm -CONFIG_TI_EQEP=3Dm CONFIG_RZ_MTU3_CNT=3Dm CONFIG_STM32_TIMER_CNT=3Dm +CONFIG_TI_EQEP=3Dm CONFIG_HTE=3Dy CONFIG_HTE_TEGRA194=3Dy CONFIG_HTE_TEGRA194_TEST=3Dm @@ -1924,14 +1856,12 @@ CONFIG_OVERLAY_FS=3Dm CONFIG_VFAT_FS=3Dy CONFIG_TMPFS_POSIX_ACL=3Dy CONFIG_HUGETLBFS=3Dy -CONFIG_CONFIGFS_FS=3Dy CONFIG_EFIVAR_FS=3Dy CONFIG_UBIFS_FS=3Dm CONFIG_SQUASHFS=3Dy CONFIG_PSTORE_RAM=3Dm CONFIG_NFS_FS=3Dy CONFIG_NFS_V4=3Dy -CONFIG_NFS_V4_1=3Dy CONFIG_NFS_V4_2=3Dy CONFIG_ROOT_NFS=3Dy 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with ESMTPSA id 5b1f17b1804b1-4909d6eb470sm38694785e9.10.2026.05.29.07.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 07:47:42 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, francesco.utel@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Bjorn Andersson , Dmitry Baryshkov , Eric Biggers , Geert Uytterhoeven , Konrad Dybcio , Krzysztof Kozlowski , Luca Weiss , Michal Simek , Sven Peter Subject: [PATCH v2 15/15] arm64: defconfig: enable configs for Engicam MicroGEA-STM32MP257-RMM Date: Fri, 29 May 2026 16:46:29 +0200 Message-ID: <20260529144707.3931919-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> References: <20260529144707.3931919-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable I2C (touchscreen and audio codec), SPI (display configuration), DRM panel and SAI (audio) configurations required to support the Engicam MicroGEA-STM32MP257-RMM board Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 89730d2ec954..bc298812f299 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -563,6 +563,7 @@ CONFIG_I2C_RK3X=3Dy CONFIG_I2C_RZV2M=3Dm CONFIG_I2C_S3C2410=3Dy CONFIG_I2C_SH_MOBILE=3Dy +CONFIG_I2C_STM32F7=3Dy CONFIG_I2C_TEGRA=3Dy CONFIG_I2C_UNIPHIER_F=3Dy CONFIG_I2C_XILINX=3Dm @@ -600,6 +601,7 @@ CONFIG_SPI_QUP=3Dy CONFIG_SPI_QCOM_GENI=3Dm CONFIG_SPI_S3C64XX=3Dy CONFIG_SPI_SH_MSIOF=3Dm +CONFIG_SPI_STM32=3Dy CONFIG_SPI_STM32_OSPI=3Dm CONFIG_SPI_SUN6I=3Dy CONFIG_SPI_TEGRA210_QUAD=3Dm @@ -983,6 +985,7 @@ CONFIG_DRM_PANEL_LVDS=3Dm CONFIG_DRM_PANEL_HIMAX_HX8279=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112A=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112B=3Dm +CONFIG_DRM_PANEL_ILITEK_ILI9806E_SPI=3Dm CONFIG_DRM_PANEL_ILITEK_ILI9882T=3Dm CONFIG_DRM_PANEL_KHADAS_TS050=3Dm CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=3Dm @@ -1082,6 +1085,7 @@ CONFIG_SND_SOC_ROCKCHIP_SPDIF=3Dm CONFIG_SND_SOC_ROCKCHIP_RT5645=3Dm CONFIG_SND_SOC_RK3399_GRU_SOUND=3Dm CONFIG_SND_SOC_SAMSUNG=3Dm +CONFIG_SND_SOC_STM32_SAI=3Dm CONFIG_SND_SUN8I_CODEC=3Dm CONFIG_SND_SUN8I_CODEC_ANALOG=3Dm CONFIG_SND_SUN50I_CODEC_ANALOG=3Dm --=20 2.43.0