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Fri, 29 May 2026 07:08:34 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH v2 1/2] iommu/arm-smmu-v3: Detect Tegra264 erratum Date: Fri, 29 May 2026 14:08:29 +0000 Message-ID: <20260529140830.629738-2-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260529140830.629738-1-amhetre@nvidia.com> References: <20260529140830.629738-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E5F:EE_|IA1PR12MB7496:EE_ X-MS-Office365-Filtering-Correlation-Id: ee50be12-2690-4b48-a2a2-08debd8bd652 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|56012099006|3023799007|11063799006|22082099003|18002099003; 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charset="utf-8" Tegra264 SMMU is affected by erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is guaranteed to evict the entry. ATC_INV is not affected and must not be doubled. The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot be detected from hardware register. Tegra264 boots from device tree only and has no ACPI/IORT support, so detection is through device tree only. Add the ARM_SMMU_OPT_TLBI_TWICE option and set it on instances matching the existing "nvidia,tegra264-smmu" compatible. No callers consume the option yet, next patch wires the workaround into the CMDQ issue paths. Signed-off-by: Ashish Mhetre Reviewed-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 +++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9be589d14a3b..88296c0a5337 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5229,8 +5229,10 @@ static int arm_smmu_device_dt_probe(struct platform_= device *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |=3D ARM_SMMU_FEAT_COHERENCY; =20 - if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) { tegra_cmdqv_dt_probe(dev->of_node, smmu); + smmu->options |=3D ARM_SMMU_OPT_TLBI_TWICE; + } =20 return ret; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 16353596e08a..08d1abaf31ae 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -928,6 +928,14 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) +/* + * Tegra264 erratum: a TLB entry can survive an invalidation that races + * with concurrent traffic targeting the same entry. The software + * workaround is to issue every CFGI/TLBI command twice, each followed + * by CMD_SYNC. The second issue is guaranteed to evict the entry. + * ATC_INV commands are not affected and must not be doubled. + */ +#define ARM_SMMU_OPT_TLBI_TWICE (1 << 5) u32 options; =20 struct arm_smmu_cmdq cmdq; --=20 2.50.1 From nobody Mon Jun 8 11:01:53 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010030.outbound.protection.outlook.com [52.101.56.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D4843E5EDC; Fri, 29 May 2026 14:09:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.30 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780063752; cv=fail; b=WhO5b3O55pa6lBYFKkboCTsJRiplxpkaXrPkJMMw5VLosfUnkJn9LIiGwymTzNik+I3iAG4fw6p8UgHRk0NOFTv512r3ksx/Ygxf6l1C8BQtz6twW0wQeL97z67MsNNstetgEZbNDTR5Wcell7To33GTSgv1/3P1P5RtyhKIgdc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Apply the workaround for Tegra264 erratum by issuing every CFGI/TLBI command twice on affected SMMU instances, with CMD_SYNC after each. The erratum requires this exact sequencing: TLBI/CFGI ... CMD_SYNC TLBI/CFGI ... CMD_SYNC To get this sequence with minimal surgery, hook the workaround into arm_smmu_cmdq_issue_cmdlist(). Rename the original function to __arm_smmu_cmdq_issue_cmdlist() and add a thin wrapper that, on affected SMMUs and when @sync is true, re-issues the same cmdlist a second time. A new arm_smmu_cmd_needs_tlbi_twice() helper classifies which opcodes need the doubling: CFGI_* and TLBI_*. For batches that exceed CMDQ_BATCH_ENTRIES commands, arm_smmu_cmdq_batch_add_cmd_p() normally flushes the full buffer with sync=3Dfalse, deferring the SYNC to the eventual batch_submit(). On affected SMMUs this would leave the first chunk's commands issued only once, since the WAR hook in arm_smmu_cmdq_issue_cmdlist() only fires on synced submissions. Force a SYNC on the capacity rollover when the buffer carries CFGI/TLBI commands so every flushed chunk is correctly doubled. Signed-off-by: Ashish Mhetre Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 66 +++++++++++++++++++-- 1 file changed, 61 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 88296c0a5337..38d45f175a2c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -698,10 +698,10 @@ static void arm_smmu_cmdq_write_entries(struct arm_sm= mu_cmdq *cmdq, * insert their own list of commands then all of the commands from one * CPU will appear before any of the commands from the other CPU. */ -int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq, - struct arm_smmu_cmd *cmds, int n, - bool sync) +static int __arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmd *cmds, int n, + bool sync) { struct arm_smmu_cmd cmd_sync; u32 prod; @@ -820,6 +820,52 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device= *smmu, return ret; } =20 +/* + * Returns true if @opcode is a CFGI_* or TLBI_* command, i.e. one of the + * invalidations covered by Tegra264 erratum (see ARM_SMMU_OPT_TLBI_TWICE). + */ +static bool arm_smmu_cmd_needs_tlbi_twice(u8 opcode) +{ + switch (opcode) { + case CMDQ_OP_CFGI_STE: + case CMDQ_OP_CFGI_ALL: + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + case CMDQ_OP_TLBI_NH_ALL: + case CMDQ_OP_TLBI_NH_ASID: + case CMDQ_OP_TLBI_NH_VA: + case CMDQ_OP_TLBI_NH_VAA: + case CMDQ_OP_TLBI_EL2_ALL: + case CMDQ_OP_TLBI_EL2_ASID: + case CMDQ_OP_TLBI_EL2_VA: + case CMDQ_OP_TLBI_S12_VMALL: + case CMDQ_OP_TLBI_S2_IPA: + case CMDQ_OP_TLBI_NSNH_ALL: + return true; + default: + return false; + } +} + +int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmd *cmds, int n, + bool sync) +{ + int ret =3D __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); + + /* + * The driver's batch invariants keep a single submission's + * opcode class uniform, so checking the first command is enough. + */ + if (!ret && sync && (smmu->options & ARM_SMMU_OPT_TLBI_TWICE) && + arm_smmu_cmd_needs_tlbi_twice(FIELD_GET(CMDQ_0_OP, + cmds[0].data[0]))) + ret =3D __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); + + return ret; +} + static int arm_smmu_cmdq_issue_cmd_p(struct arm_smmu_device *smmu, struct arm_smmu_cmd *cmd, bool sync) { @@ -863,8 +909,18 @@ static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_s= mmu_device *smmu, } =20 if (cmds->num =3D=3D CMDQ_BATCH_ENTRIES) { + /* + * Force a SYNC only when the batch carries commands that + * have to be doubled (see ARM_SMMU_OPT_TLBI_TWICE). + * The batch holds a uniform opcode class, so checking + * the first command is sufficient. + */ + bool need_sync =3D (smmu->options & ARM_SMMU_OPT_TLBI_TWICE) && + arm_smmu_cmd_needs_tlbi_twice(FIELD_GET(CMDQ_0_OP, + cmds->cmds[0].data[0])); + arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, - cmds->num, false); + cmds->num, need_sync); arm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd); } =20 --=20 2.50.1