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Fri, 29 May 2026 07:57:18 +0000 (GMT) Received: from li-7bb28a4c-2dab-11b2-a85c-887b5c60d769.ibm.com.com (unknown [9.124.221.69]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 29 May 2026 07:57:17 +0000 (GMT) From: Shrikanth Hegde To: maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, peterz@infradead.org, mingo@kernel.org Cc: sshegde@linux.ibm.com, christophe.leroy@csgroup.eu, linux-kernel@vger.kernel.org, venkat88@linux.ibm.com, yu.c.chen@intel.com, tim.c.chen@linux.intel.com, kprateek.nayak@amd.com, srikar@linux.ibm.com, riteshh@linux.ibm.com, stable@vger.kernel.org, "Ritesh Harjani (IBM)" Subject: [PATCH] sched/topology: Provide arch_llc_mask for cache aware scheduling Date: Fri, 29 May 2026 13:27:12 +0530 Message-ID: <20260529075712.1181039-1-sshegde@linux.ibm.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=QLJYgALL c=1 sm=1 tr=0 ts=6a1946e7 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=QyXUC8HyAAAA:8 a=pGLkceISAAAA:8 a=-47l-NziEOCSl2LEx70A:9 X-Proofpoint-GUID: N9MsWTTA2OgFAQqDSN6GN4uceCGzPAFW X-Proofpoint-ORIG-GUID: jd94O_QPmPdm8m04htMDSwhRKUKv57KN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDA3MyBTYWx0ZWRfX7HaOgpR6LV/x o5XA8jIi7/LfDrSOpVhXiCAJ86QD5bof1TYXJwr13tgn0DxunZC1YAwL8eaBXipcPd88Ujy3VAo 9p854gXdmKuQYqABi76ayel/cUh7Ges5N425GFmamjae80z4TyvILcIufMIlP/TmvX1sl2+1NHV xFXLTqzoRoHBB+TE28XfVd21sMFWg6ZXWfjE6JnkqfzFf0zqHXzjB+M6ISccb18iEpXmj8Sjhpc LeieH3kHbkq6ZfgWQkUlUXcMKvne6gi/ooNHXg0kaMPvu2Ylq/6TRQKXTsBG5uwiSRIIu0NMjzl eO9SVcBd8kkmJWFmIlRppRZpezcoSADoU0YLgTqqiM16zr6CvaluLhkfFDzucCWmaLv3dFod8OO pQPHApAQR0sG7e9x+rh1bD3GlDuxJceWF1rjil8Nh8Nqq1kgcz48eoQ6//z4Pi7sNB7JdqAnN0C uxPE2BBxElVshbNK0Tw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-29_02,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 clxscore=1011 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290073 Content-Type: text/plain; charset="utf-8" Venkat Reported a boot kernel panic next-20260522. Git bisect pointed to b5ea300a17e3 ("sched/cache: Make LLC id continuous") Stacktrace points to llc_mask being null. NIP [c000000000e58504] _find_first_bit+0x44/0x130 LR [c000000000e58500] _find_first_bit+0x40/0x130 Call Trace: build_sched_domains+0xad8/0xe50 sched_init_smp+0xa8/0x164 kernel_init_freeable+0x250/0x370 ret_from_kernel_user_thread+0x14/0x1c On powerpc, cpu_coregroup_mask is available only when the underlying hardware support coregroup. In shared LPAR, QEMU guest or power9 etc coregroup isn't supported. In such cases llc_mask was being referenced when it was null leading to panic. On powerpc, LLC is at SMT core level. So assumption that coregroup(MC) domain point to LLC is wrong. Provide a way for archs to say where its LLC is if it not at MC domain.=20 Based on tip/master at 5c89783224e9 ("Merge branch into tip/master: 'x86/td= x'") Cc: stable@vger.kernel.org Fixes: b5ea300a17e3 ("sched/cache: Make LLC id continuous") Reported-by: Venkat Rao Bagalkote Closes: https://lore.kernel.org/all/51154de7-3700-4cb4-82f2-1b3a8fa427f7@li= nux.ibm.com/ Reviewed-by: Chen Yu Tested-by: Venkat Rao Bagalkote =20 Tested-by: Ritesh Harjani (IBM) Co-developed-by: Chen, Yu C Signed-off-by: Shrikanth Hegde Reviewed-by: Srikar Dronamraju --- arch/powerpc/include/asm/topology.h | 6 ++++++ kernel/sched/topology.c | 13 +++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm= /topology.h index 66ed5fe1b718..e3de0f3d8b86 100644 --- a/arch/powerpc/include/asm/topology.h +++ b/arch/powerpc/include/asm/topology.h @@ -135,6 +135,12 @@ struct cpumask *cpu_coregroup_mask(int cpu); const struct cpumask *cpu_die_mask(int cpu); int cpu_die_id(int cpu); =20 +/* Points to where the LLC is. On power9 this will point at CACHE + * domain, On others it will point to SMT domain. In all cases + * cpu_l2_cache_mask points to where LLC is + */ +#define arch_llc_mask(cpu) cpu_l2_cache_mask(cpu) + #ifdef CONFIG_PPC64 #include =20 diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index df2ceb54c970..622e2e01974c 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -2063,12 +2063,21 @@ const struct cpumask *tl_mc_mask(struct sched_domai= n_topology_level *tl, int cpu return cpu_coregroup_mask(cpu); } =20 -#define llc_mask(cpu) cpu_coregroup_mask(cpu) +/* + * Majority of architectures have LLC at MC domain level with exception + * such as powerpc. Provide a way for arch to specify where its LLC is + * if it falls in exception category + */ +# ifndef arch_llc_mask +#define arch_llc_mask(cpu) cpu_coregroup_mask(cpu) +# endif =20 #else -#define llc_mask(cpu) cpumask_of(cpu) +#define arch_llc_mask(cpu) cpumask_of(cpu) #endif =20 +#define llc_mask(cpu) arch_llc_mask(cpu) + const struct cpumask *tl_pkg_mask(struct sched_domain_topology_level *tl, = int cpu) { return cpu_node_mask(cpu); --=20 2.47.3