From nobody Mon Jun 8 13:31:36 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D28771C84BC; Fri, 29 May 2026 06:32:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780036329; cv=none; b=sdIN5z9N9mFs9BeqBdpnY1w++Ue0koWwV/1LQ2vobWT1W3VGU//dA+MTRCsZU0/jiJXrMtMsIatQNz2vbMjuSWXfZwXKTdvqVBdR6diFEdpFdx2VqC3WHWm8ZkXN/QrrG0/DVJYkQtCtTc9h1a/9/G+O0e07TIo6SbsgvhdXIX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780036329; c=relaxed/simple; bh=Fn6marTZoXy4GsLFj3sUdyTZXbWZvs/hVtEybn7BURA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=COU8XoLhFKyEbnrfT+eRtQ0tKMhTCaoyu1JSvBBfGXeSKZlapmnBcMshggARJULRXy2niUq/90g6ce6QU2qiAI35j08Hpwf9K7g9/xh2PqnP54DtVBMN7DGQV8JaAl/EZjEiFNMIPTsFEpCqQeJP2rogbDB9mypsgbtE9pLeyLc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4gRYRJ3mRbzKHMNN; Fri, 29 May 2026 14:31:40 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.128]) by mail.maildlp.com (Postfix) with ESMTP id EF2AA4056D; Fri, 29 May 2026 14:31:57 +0800 (CST) Received: from huaweicloud.com (unknown [10.50.87.109]) by APP4 (Coremail) with SMTP id gCh0CgAHz1rHMhlqg24kEA--.34476S4; Fri, 29 May 2026 14:31:54 +0800 (CST) From: Zeng Heng To: vladimir.murzin@arm.com, xuwei5@huawei.com, wangyushan12@huawei.com, maz@kernel.org, skhan@linuxfoundation.org, miko.lenczewski@arm.com, lucaswei@google.com, broonie@kernel.org, thuth@redhat.com, ryan.roberts@arm.com, tongtiangen@huawei.com, oupton@kernel.org, kuninori.morimoto.gx@renesas.com, mark.rutland@arm.com, will@kernel.org, corbet@lwn.net, catalin.marinas@arm.com, kevin.brodsky@arm.com, lpieralisi@kernel.org, yangyicong@hisilicon.com, james.clark@linaro.org, yeoreum.yun@arm.com Cc: linux-doc@vger.kernel.org, wangkefeng.wang@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] arm64: kernel: Unify CNP disable workaround into ARM64_WORKAROUND_DISABLE_CNP Date: Fri, 29 May 2026 14:31:32 +0800 Message-ID: <20260529063132.766491-1-zengheng@huaweicloud.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: gCh0CgAHz1rHMhlqg24kEA--.34476S4 X-Coremail-Antispam: 1UD129KBjvJXoW3WF47tr4ruw43Jry7Aw4kXrb_yoW3Ww1Upr 13Jr4xJr1UWF15XryUJw4UJr15Aan3Jw1Yqr1UK340qr1ayrWUAr4UX34xJFW0qrykWr48 GF1q9r15JF1jyrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUv2b4IE77IF4wAFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6r1S6rWUM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x 0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG 6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFV Cjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0E n4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I 0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8 ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAF wI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa 7IU04xRDUUUUU== X-CM-SenderInfo: p2hqwxhhqjqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" From: Zeng Heng HiSilicon HIP09 implements TLB entry matching behavior that deviates from the ARM architecture specification when the CnP (Common not Private) bit is set in TTBRx_ELx. When TTBRx.CNP=3D1, TLB entries may be incorrectly shared between CPU cores, leading to TLB conflicts and stale mappings. This breaks coherency and can result in incorrect translations. Add the hardware erratum workaround (Hisilicon erratum 162100125) to disable CNP on affected HIP09 cores. Merge the existing NVIDIA Carmel and the HiSilicon HIP09 CNP errata workarounds into a single generic capability ARM64_WORKAROUND_DISABLE_CNP. Both NVIDIA Carmel and HiSilicon HIP09 have hardware errata where CNP (Common Not Private) behavior differs from the ARM specification, causing incorrect TLB entry sharing between cores. The existing NVIDIA_CARMEL_CNP_ERRATUM and the newly added HISILICON_ERRATUM_162100125 are now both handled by the unified ARM64_WORKAROUND_DISABLE_CNP. Co-developed-by: Tong Tiangen Signed-off-by: Tong Tiangen Signed-off-by: Zeng Heng --- v1: https://lore.kernel.org/all/20260526015720.206854-1-zengheng@huaweiclou= d.com/ Changes in v2: - Unify CNP disable workaround into ARM64_WORKAROUND_DISABLE_CNP --- Documentation/arch/arm64/silicon-errata.rst | 4 +++- arch/arm64/Kconfig | 17 ++++++++++++----- arch/arm64/include/asm/cpucaps.h | 4 ++-- arch/arm64/kernel/cpu_errata.c | 17 ++++++++++++----- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/tools/cpucaps | 2 +- 6 files changed, 31 insertions(+), 15 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 211119ce7adc..b4565e1a726d 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -254,7 +254,7 @@ stable kernels. | Marvell | ARM-MMU-500 | #582743 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ -| NVIDIA | Carmel Core | N/A | NVIDIA_CARMEL_CNP_E= RRATUM | +| NVIDIA | Carmel Core | N/A | ARM64_WORKAROUND_DI= SABLE_CNP| +----------------+-----------------+-----------------+--------------------= ---------+ | NVIDIA | T241 GICv3/4.x | T241-FABRIC-4 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ @@ -284,6 +284,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | Hisilicon | Hip09 | #162100801 | HISILICON_ERRATUM_1= 62100801 | +----------------+-----------------+-----------------+--------------------= ---------+ +| Hisilicon | Hip09 | #162100125 | ARM64_WORKAROUND_DI= SABLE_CNP| ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM= _1003 | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fe60738e5943..dc0bd32ea2d1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1315,13 +1315,20 @@ config QCOM_FALKOR_ERRATUM_E1041 If unsure, say Y. -config NVIDIA_CARMEL_CNP_ERRATUM - bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM co= res" +config ARM64_WORKAROUND_DISABLE_CNP + bool "Disable CNP on affected CPUs" default y help - If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not - invalidate shared TLB entries installed by a different core, as it would - on standard ARM cores. + This option disables the CNP (Common Not Private) feature on CPUs + that have hardware errata affecting CNP behavior. + + On NVIDIA Carmel cores, CNP behaves differently than on standard ARM + cores: non-shareable TLBIs on a core may not invalidate shared TLB + entries installed by a different core. + + On Hisilicon HIP09 cores, TLB entries may be incorrectly shared + between cores when TTBRx.CNP=3D1, leading to TLB conflicts and + stale mappings. If unsure, say Y. diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpuc= aps.h index d0d3cdd5763c..25c61cda901c 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -58,8 +58,8 @@ cpucap_is_possible(const unsigned int cap) return IS_ENABLED(CONFIG_ARM64_ERRATUM_2658417); case ARM64_WORKAROUND_CAVIUM_23154: return IS_ENABLED(CONFIG_CAVIUM_ERRATUM_23154); - case ARM64_WORKAROUND_NVIDIA_CARMEL_CNP: - return IS_ENABLED(CONFIG_NVIDIA_CARMEL_CNP_ERRATUM); + case ARM64_WORKAROUND_DISABLE_CNP: + return IS_ENABLED(CONFIG_ARM64_WORKAROUND_DISABLE_CNP); case ARM64_WORKAROUND_REPEAT_TLBI: return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI); case ARM64_WORKAROUND_SPECULATIVE_SSBS: diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 5377e4c2eba2..675cd059165c 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -394,6 +394,14 @@ static const struct arm64_cpu_capabilities qcom_erratu= m_1003_list[] =3D { }; #endif +#ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP +static const struct midr_range cnp_erratum_cpus[] =3D { + MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), + MIDR_ALL_VERSIONS(MIDR_HISI_HIP09), + {}, +}; +#endif + #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE static const struct midr_range workaround_clean_cache[] =3D { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ @@ -801,12 +809,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = =3D { 1, 0), }, #endif -#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM +#ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP { - /* NVIDIA Carmel */ - .desc =3D "NVIDIA Carmel CNP erratum", - .capability =3D ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, - ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), + .desc =3D "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125", + .capability =3D ARM64_WORKAROUND_DISABLE_CNP, + ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus), }, #endif #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6d53bb15cf7b..20c5f24f74a9 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1785,7 +1785,7 @@ has_useable_cnp(const struct arm64_cpu_capabilities *= entry, int scope) if (is_kdump_kernel()) return false; - if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) + if (cpus_have_cap(ARM64_WORKAROUND_DISABLE_CNP)) return false; return has_cpuid_feature(entry, scope); diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 811c2479e82d..9b85a84f6fd4 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -120,7 +120,7 @@ WORKAROUND_CAVIUM_TX2_219_PRFM WORKAROUND_CAVIUM_TX2_219_TVM WORKAROUND_CLEAN_CACHE WORKAROUND_DEVICE_LOAD_ACQUIRE -WORKAROUND_NVIDIA_CARMEL_CNP +WORKAROUND_DISABLE_CNP WORKAROUND_PMUV3_IMPDEF_TRAPS WORKAROUND_QCOM_FALKOR_E1003 WORKAROUND_QCOM_ORYON_CNTVOFF -- 2.43.0