From nobody Mon Jun 8 11:05:16 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5237F3E51F5 for ; Fri, 29 May 2026 16:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780070789; cv=none; b=hSVOAp3ZFvQ4wQJMVJstkoMZ1qulkSNNWkMygWRUh6dH8G6CBG41m9+ai2IsAtCR8spFbQAZ1G4t+jMKsPGju7yoz14PcBB8okEn1lGqDBJyLxracQ0D8SoBCn7fRbqXViQDH8AO9eoVPMR/vFfQhn2vzbY1ZuQ/mQ6VEFcUvvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780070789; c=relaxed/simple; bh=uRMC11vG6EELb4BTLDYbfsqc/TUx32koWGHqFzNO83Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CkB0Kd4sRWwshcNmNf8lpqv0DmFQDgBvXOJVv5umUgp4ytL+7XAbawo0UcIqxehrfnXj0BB8wpFo8VEcu+vb60CqbcXBuSskonkL049b9pTK5JqXwCCKXq0YXWCr2Cng7tVH+4MxR+La8U9BSd8eywcvVBj3rvqckYIoNT57qsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=QjDA+en6; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="QjDA+en6" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 7B2E8C6245E; Fri, 29 May 2026 16:06:24 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id BDD7F601FA; Fri, 29 May 2026 16:06:23 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DB19A10888CD2; Fri, 29 May 2026 18:06:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1780070782; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ANhyfw1+Ubu5zOF6PsA+222RbP0JldLgyuO+B5iaEzg=; b=QjDA+en6dgn3wGlF8KDf6ahtr0EUqv4M3N9iwSZTRx42eDdq+DyOrY3cxz/FhUbVRXXMhv 0Y6h6VLlvwEf517lBI0BFoJwFGOEWTuikZKBIZRBDz57OoH2g4JC8URfUZ+NUIeDex+Uyz ndAXSjwhnG9Zc9SpZCENC++hEc0P2D8wYP9JWgNDs7RnPEr4Mujjpd/RVYlSG3Z0RX2odM KyRCRqgextZ10y38Xwpv0J2doW12b3DqTF6VwxWg0kmhWNYIQxwA5QBWZ4tVU8LsarZrsb 23PwLmnDe7apia3i6pZIQmt9Ot53OpcV4AKwrpcMTyQjk7G6PR+lOluFsqiTnw== From: Miquel Raynal Date: Fri, 29 May 2026 18:05:46 +0200 Subject: [PATCH 1/5] mtd: spi-nor: Refactor Read Status/Write Status support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-1-f3ae18502d5a@bootlin.com> References: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> In-Reply-To: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea Cc: Steam Lin , Hsin-Yi Wang , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 SPI NOR has a lot of history. Additions over additions, the subtleties of the JESD216 specification, their implementations by the manufacturers and the hardware mistakes have generated a gigantic maze, let's try to understand what is really needed. The specification explains the QE (Quad Enable) bitfield as describing where the bit to enable the Quad capability is, but also how to set it. Unfortunately, the specification is not precise about what opcodes are supported exactly in all the cases. There is an introduction that basically states: - Opcode 0x05 reads SR1, and then SR2 if another byte is read - Opcode 0x35 allows to read SR2 - Opcode 0x01 writes SR1, and then SR2 if another byte is written Then the bitfield, among indicating the location of the QE bit, may indicate: - Reading SR1 and SR2 in one operation is not possible (loops over the content of SR1) - Reading SR2 directly is possible - Writing SR1 smashes SR2 One problem with the current implementation, is that it only focuses on the QE bit. A quad_enable function was created for each case, even though in practice, the logic was always the same: read, modify, write, read back and verify. One problem comes when other features need to play with the status registers, like software block protection or OTP: you never know how to properly handle the QE bit, nor where it is, nor how to read/write the Status registers. This lead to approximations/guessing (in swp.c, otp.c and obviously in legacy controller drivers like atmel.c) but also to the implementation of a gazillon of helpers for reading/writing/checking the status registers. In addition, I believe some design decisions had a negative impact over the years. - All possible situations had to be flagged by the core. This is likely wrong, because we no longer know why we need specific quirks. It was ineherent to the state of the SPI NOR core before the great cleanup that had happened the past few years. I believe this creates confusion in the core today, and we should push this to vendor fixups instead. As an example, in 2023 Hsin-Yi was facing an issue because his chip was setting the wrong QER value, leading to RDCR being prevented, thus falling into a condition blindly setting a random QE bit (I strongy believe it is done like that for wrong reasons). His chip actually had RDCR support! The correct fix should have been to mark the capability in a device fixup instead of handling this in the core. Link: https://lore.kernel.org/lkml/CAJMQK-hR0eaO0b4Vd0U8_KAndLyZapqdHjVLA= oe42rWi9rdLkA@mail.gmail.com/ - SFDP parsing is over cautious. I believe BFPT_DWORD15_QER_SR2_BIT1_NO_RD is abusive (nothing states that RDCR is not supported), and BFPT_DWORD15_QER_SR2_BIT1 is also out of specification when forcing 16-bit Status writes. - SNOR_F_HAS_16BIT_SR is only imposing 16bit Status writes, whereas reads can still be 8-bit wides and even sometimes can only be 8-bit wide. - The usage of helpers verifying the writes was also spread for IMHO no really good reason. Why shouldn't we trust spi operations when it comes to Status Registers? We do not read back our page reads, so why status registers should be treated with so much care, if it's not because we are unsure of what is being done? My proposal includes a check when it comes to the QE bit (done once) but we don't need these checks otherwise. If the QE bit was written properly, there are high chances that the other register accesses will just be fine, no? Asde from my main quest, I also observed no good reason to ask the read/write status register callers to use nor->bouncebuf while the low-level helpers could do it themselves (we are talking about one or two bytes being copied). So after these observations, my proposal is the following: - Create private low level helpers that just read or write a status register. They are flexible, we can give the opcode (which varies based on the SFDP QER field) and the length (1 or 2). - Create public generic accessors which will be used to read/write sr1 and/or sr2. This is where all the cleverness shall be. The helpers use the available opcodes for a given chip in order to fullfill the request. - Provide a single generic ->quad_enable() hook which generically does all the steps mentioned above (read, modify, write, read back and verify). - Create a list of opcodes for all 6 possible situations: {read, write} {sr1, sr2, sr1 and sr2}. These opcodes are filled/cleared based on the QER field. An opcode set to 0 indicates the absence of support (there is no 0x00 opcode in SPI NOR). I tried my best to analyze the current behavior and to mimic it as much as possible, but this is a risky cleanup. However, if we go for this, it will be *much* easier in the future to handle all kind of chip variations. We won't be limited to a couple of flags anymore, but rather we'll be able to just disable a read or write capability using a single line. Signed-off-by: Miquel Raynal --- This is a really hard to review patch, it is big, full of changes everywhere, but I cannot really split it further. The commit log is really important, it tries to explain the steps I went through when trying to refactor the whole QE/SR handling for which I received feedback from Michael, Tudor and Sashiko. Ideally we could expect test coverage of each case: - BFPT_DWORD15_QER_NONE: Probably not needed - BFPT_DWORD15_QER_SR2_BIT1_BUGGY: Expected from Hsin-Yi - BFPT_DWORD15_QER_SR2_BIT1_NO_RD: Tested with a chip re-enabling RDCR in a fixup - BFPT_DWORD15_QER_SR1_BIT6: TBD - BFPT_DWORD15_QER_SR2_BIT7: TBD - BFPT_DWORD15_QER_SR2_BIT1: TBD - BFPT_DWORD15_QER_SR2_BIT1_1B: Done. There will probably be breakages on older chips. These cannot be guessed because they are not properly listed in manufacturer fixups (yet). If we want a cleanup/simplification, we will have to cope with this risk. I hope the diff stats will motivate people to have a look and report their testing. I will also eagerly monitor Sashiko's output which will probably be very useful to catch niche weird cases where these changes might break. --- drivers/mtd/spi-nor/atmel.c | 50 +-- drivers/mtd/spi-nor/core.c | 702 +++++++++++------------------------= ---- drivers/mtd/spi-nor/core.h | 54 ++- drivers/mtd/spi-nor/debugfs.c | 1 - drivers/mtd/spi-nor/gigadevice.c | 6 +- drivers/mtd/spi-nor/issi.c | 3 +- drivers/mtd/spi-nor/macronix.c | 12 +- drivers/mtd/spi-nor/otp.c | 16 +- drivers/mtd/spi-nor/sfdp.c | 37 ++- drivers/mtd/spi-nor/spansion.c | 16 +- drivers/mtd/spi-nor/sst.c | 5 +- drivers/mtd/spi-nor/swp.c | 58 +--- drivers/mtd/spi-nor/winbond.c | 4 +- include/linux/mtd/spi-nor.h | 4 - 14 files changed, 326 insertions(+), 642 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c index 82c592f0a1e1..124ceb795f56 100644 --- a/drivers/mtd/spi-nor/atmel.c +++ b/drivers/mtd/spi-nor/atmel.c @@ -23,18 +23,28 @@ static int at25fs_nor_lock(struct spi_nor *nor, loff_t = ofs, u64 len) =20 static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { + /* Write 0x00 to the status register to disable write protection */ + u8 sr =3D 0; int ret; =20 /* We only support unlocking the whole flash array */ if (ofs || len !=3D nor->params->size) return -EINVAL; =20 - /* Write 0x00 to the status register to disable write protection */ - ret =3D spi_nor_write_sr_and_check(nor, 0); + ret =3D spi_nor_write_srs(nor, &sr, NULL); if (ret) - dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n"); + return ret; =20 - return ret; + ret =3D spi_nor_read_srs(nor, &sr, NULL); + if (ret) + return ret; + + if (sr) { + dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n"); + return -EIO; + } + + return 0; } =20 static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len) @@ -69,6 +79,7 @@ static const struct spi_nor_fixups at25fs_nor_fixups =3D { * Return: 0 on success, -error otherwise. */ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs, + u64 len, bool is_protect) { int ret; @@ -78,19 +89,24 @@ static int atmel_nor_set_global_protection(struct spi_n= or *nor, loff_t ofs, if (ofs || len !=3D nor->params->size) return -EINVAL; =20 - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + ret =3D spi_nor_read_srs(nor, &sr, NULL); if (ret) return ret; =20 - sr =3D nor->bouncebuf[0]; - /* SRWD bit needs to be cleared, otherwise the protection doesn't change = */ if (sr & SR_SRWD) { sr &=3D ~SR_SRWD; - ret =3D spi_nor_write_sr_and_check(nor, sr); - if (ret) { - dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n"); + ret =3D spi_nor_write_srs(nor, &sr, NULL); + if (ret) return ret; + + ret =3D spi_nor_read_srs(nor, &sr, NULL); + if (ret) + return ret; + + if (sr & SR_SRWD) { + dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n"); + return -EIO; } } =20 @@ -108,14 +124,7 @@ static int atmel_nor_set_global_protection(struct spi_= nor *nor, loff_t ofs, sr &=3D ~ATMEL_SR_GLOBAL_PROTECT_MASK; } =20 - nor->bouncebuf[0] =3D sr; - - /* - * We cannot use the spi_nor_write_sr_and_check() because this command - * isn't really setting any bits, instead it is an pseudo command for - * "Global Unprotect" or "Global Protect" - */ - return spi_nor_write_sr(nor, nor->bouncebuf, 1); + return spi_nor_write_srs(nor, &sr, NULL); } =20 static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, u64 l= en) @@ -131,16 +140,17 @@ static int atmel_nor_global_unprotect(struct spi_nor = *nor, loff_t ofs, u64 len) static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs, u64 len) { + u8 sr; int ret; =20 if (ofs >=3D nor->params->size || (ofs + len) > nor->params->size) return -EINVAL; =20 - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + ret =3D spi_nor_read_srs(nor, &sr, NULL); if (ret) return ret; =20 - return ((nor->bouncebuf[0] & ATMEL_SR_GLOBAL_PROTECT_MASK) =3D=3D ATMEL_S= R_GLOBAL_PROTECT_MASK); + return ((sr & ATMEL_SR_GLOBAL_PROTECT_MASK) =3D=3D ATMEL_SR_GLOBAL_PROTEC= T_MASK); } =20 static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = =3D { diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b25d1a870a22..ca66661a7f44 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -443,75 +443,6 @@ int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 = ndummy, u8 *id, return ret; } =20 -/** - * spi_nor_read_sr() - Read the Status Register. - * @nor: pointer to 'struct spi_nor'. - * @sr: pointer to a DMA-able buffer where the value of the - * Status Register will be written. Should be at least 2 byte= s. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_RDSR_OP(sr); - - if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { - op.addr.nbytes =3D nor->params->rdsr_addr_nbytes; - op.dummy.nbytes =3D nor->params->rdsr_dummy; - /* - * We don't want to read only one byte in DTR mode. So, - * read 2 and then discard the second byte. - */ - op.data.nbytes =3D 2; - } - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, - 1); - } - - if (ret) - dev_dbg(nor->dev, "error %d reading SR\n", ret); - - return ret; -} - -/** - * spi_nor_read_cr() - Read the Configuration Register using the - * SPINOR_OP_RDCR (35h) command. - * @nor: pointer to 'struct spi_nor' - * @cr: pointer to a DMA-able buffer where the value of the - * Configuration Register will be written. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_RDCR_OP(cr); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr, - 1); - } - - if (ret) - dev_dbg(nor->dev, "error %d reading CR\n", ret); - - return ret; -} - /** * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by @@ -617,12 +548,13 @@ int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *= nor, bool enable) int spi_nor_sr_ready(struct spi_nor *nor) { int ret; + u8 sr; =20 - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + ret =3D spi_nor_read_srs(nor, &sr, NULL); if (ret) return ret; =20 - return !(nor->bouncebuf[0] & SR_WIP); + return !(sr & SR_WIP); } =20 /** @@ -784,345 +716,210 @@ int spi_nor_global_block_unlock(struct spi_nor *nor) } =20 /** - * spi_nor_write_sr() - Write the Status Register. + * spi_nor_read_srs_ll() - Low-level Status Registers read. * @nor: pointer to 'struct spi_nor'. - * @sr: pointer to DMA-able buffer to write to the Status Register. - * @len: number of bytes to write to the Status Register. + * @opcode: opcode for the status register read operation. + * @sr: pointer to buffer for storing the contnet of the status registers. + * @len: number of status registers to read. * * Return: 0 on success, -errno otherwise. */ -int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) +static int spi_nor_read_srs_ll(struct spi_nor *nor, u8 opcode, u8 *sr2, + unsigned int len) { - int ret; + int ret, i; =20 - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; + for (i =3D 0; i < len; i++) + nor->bouncebuf[i] =3D 0; =20 if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_WRSR_OP(sr, len); + struct spi_mem_op op =3D SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, len); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 ret =3D spi_mem_exec_op(nor->spimem, &op); } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr, - len); + ret =3D spi_nor_controller_ops_read_reg(nor, opcode, nor->bouncebuf, len= ); } =20 - if (ret) { - dev_dbg(nor->dev, "error %d writing SR\n", ret); - return ret; - } - - return spi_nor_wait_till_ready(nor); -} - -/** - * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1= and - * ensure that the byte written match the received value. - * @nor: pointer to a 'struct spi_nor'. - * @sr1: byte value to be written to the Status Register. - * - * Return: 0 on success, -errno otherwise. - */ -static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) -{ - int ret; - - nor->bouncebuf[0] =3D sr1; - - ret =3D spi_nor_write_sr(nor, nor->bouncebuf, 1); - if (ret) - return ret; - - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); - if (ret) - return ret; - - if (nor->bouncebuf[0] !=3D sr1) { - dev_dbg(nor->dev, "SR1: read back test failed\n"); - return -EIO; - } - - return 0; -} - -/** - * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the - * Status Register 2 in one shot. Ensure that the byte written in the Stat= us - * Register 1 match the received value, and that the 16-bit Write did not - * affect what was already in the Status Register 2. - * @nor: pointer to a 'struct spi_nor'. - * @sr1: byte value to be written to the Status Register 1. - * - * Return: 0 on success, -errno otherwise. - */ -static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) -{ - int ret; - u8 *sr_cr =3D nor->bouncebuf; - u8 cr_written; - - /* Make sure we don't overwrite the contents of Status Register 2. */ - if (!(nor->flags & SNOR_F_NO_READ_CR)) { - ret =3D spi_nor_read_cr(nor, &sr_cr[1]); - if (ret) - return ret; - } else if ((spi_nor_get_protocol_width(nor->read_proto) =3D=3D 4 || - spi_nor_get_protocol_width(nor->write_proto) =3D=3D 4) && - nor->params->quad_enable) { - /* - * If the Status Register 2 Read command (35h) is not - * supported, we should at least be sure we don't - * change the value of the SR2 Quad Enable bit. - * - * When the Quad Enable method is set and the buswidth is 4, we - * can safely assume that the value of the QE bit is one, as a - * consequence of the nor->params->quad_enable() call. - * - * According to the JESD216 revB standard, BFPT DWORDS[15], - * bits 22:20, the 16-bit Write Status (01h) command is - * available just for the cases in which the QE bit is - * described in SR2 at BIT(1). - */ - sr_cr[1] =3D SR2_QUAD_EN_BIT1; - } else { - sr_cr[1] =3D 0; - } - - sr_cr[0] =3D sr1; - - ret =3D spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; - - ret =3D spi_nor_read_sr(nor, sr_cr); - if (ret) - return ret; - - if (sr1 !=3D sr_cr[0]) { - dev_dbg(nor->dev, "SR: Read back test failed\n"); - return -EIO; - } - - if (nor->flags & SNOR_F_NO_READ_CR) - return 0; - - cr_written =3D sr_cr[1]; - - ret =3D spi_nor_read_cr(nor, &sr_cr[1]); - if (ret) - return ret; - - if (cr_written !=3D sr_cr[1]) { - dev_dbg(nor->dev, "CR: read back test failed\n"); - return -EIO; - } - - return 0; -} - -/** - * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the - * Configuration Register in one shot. Ensure that the byte written in the - * Configuration Register match the received value, and that the 16-bit Wr= ite - * did not affect what was already in the Status Register 1. - * @nor: pointer to a 'struct spi_nor'. - * @cr: byte value to be written to the Configuration Register. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) -{ - int ret; - u8 *sr_cr =3D nor->bouncebuf; - u8 sr_written; - - /* Keep the current value of the Status Register 1. */ - ret =3D spi_nor_read_sr(nor, sr_cr); - if (ret) - return ret; - - sr_cr[1] =3D cr; - - ret =3D spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; - - sr_written =3D sr_cr[0]; - - ret =3D spi_nor_read_sr(nor, sr_cr); - if (ret) - return ret; - - if (sr_written !=3D sr_cr[0]) { - dev_dbg(nor->dev, "SR: Read back test failed\n"); - return -EIO; - } - - if (nor->flags & SNOR_F_NO_READ_CR) - return 0; - - ret =3D spi_nor_read_cr(nor, &sr_cr[1]); - if (ret) - return ret; - - if (cr !=3D sr_cr[1]) { - dev_dbg(nor->dev, "CR: read back test failed\n"); - return -EIO; - } - - return 0; -} - -/** - * spi_nor_write_16bit_sr_cr_and_check() - Write the Status Register 1 and= the - * Configuration Register in one shot. Ensure that the bytes written in bo= th - * registers match the received value. - * @nor: pointer to a 'struct spi_nor'. - * @regs: two-byte array with values to be written to the status and - * configuration registers. - * - * Return: 0 on success, -errno otherwise. - */ -static int spi_nor_write_16bit_sr_cr_and_check(struct spi_nor *nor, const = u8 *regs) -{ - u8 written_regs[2]; - int ret; - - written_regs[0] =3D regs[0]; - written_regs[1] =3D regs[1]; - nor->bouncebuf[0] =3D regs[0]; - nor->bouncebuf[1] =3D regs[1]; - - ret =3D spi_nor_write_sr(nor, nor->bouncebuf, 2); - if (ret) - return ret; - - ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[0]); - if (ret) - return ret; - - if (written_regs[0] !=3D nor->bouncebuf[0]) { - dev_dbg(nor->dev, "SR: Read back test failed\n"); - return -EIO; - } - - if (nor->flags & SNOR_F_NO_READ_CR) - return 0; - - ret =3D spi_nor_read_cr(nor, &nor->bouncebuf[1]); - if (ret) - return ret; - - if (written_regs[1] !=3D nor->bouncebuf[1]) { - dev_dbg(nor->dev, "CR: read back test failed\n"); - return -EIO; - } - - return 0; -} - -/** - * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure t= hat - * the byte written match the received value without affecting other bits = in the - * Status Register 1 and 2. - * @nor: pointer to a 'struct spi_nor'. - * @sr1: byte value to be written to the Status Register. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) -{ - if (nor->flags & SNOR_F_HAS_16BIT_SR) - return spi_nor_write_16bit_sr_and_check(nor, sr1); - - return spi_nor_write_sr1_and_check(nor, sr1); -} - -/** - * spi_nor_write_sr_cr_and_check() - Write the Status Register 1 and ensur= e that - * the byte written match the received value. Same for the Control Registe= r if - * available. - * @nor: pointer to a 'struct spi_nor'. - * @regs: byte array to be written to the registers. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs) -{ - if (nor->flags & SNOR_F_HAS_16BIT_SR) - return spi_nor_write_16bit_sr_cr_and_check(nor, regs); - - return spi_nor_write_sr1_and_check(nor, regs[0]); -} - -/** - * spi_nor_write_sr2() - Write the Status Register 2 using the - * SPINOR_OP_WRSR2 (3eh) command. - * @nor: pointer to 'struct spi_nor'. - * @sr2: pointer to DMA-able buffer to write to the Status Register 2. - * - * Return: 0 on success, -errno otherwise. - */ -static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) -{ - int ret; - - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_WRSR2_OP(sr2); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2, - sr2, 1); - } - - if (ret) { - dev_dbg(nor->dev, "error %d writing SR2\n", ret); - return ret; - } - - return spi_nor_wait_till_ready(nor); -} - -/** - * spi_nor_read_sr2() - Read the Status Register 2 using the - * SPINOR_OP_RDSR2 (3fh) command. - * @nor: pointer to 'struct spi_nor'. - * @sr2: pointer to DMA-able buffer where the value of the - * Status Register 2 will be written. - * - * Return: 0 on success, -errno otherwise. - */ -static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) -{ - int ret; - - if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_RDSR2_OP(sr2); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2, - 1); - } + memcpy(sr2, nor->bouncebuf, len); =20 if (ret) - dev_dbg(nor->dev, "error %d reading SR2\n", ret); + dev_dbg(nor->dev, "Error %d reading Status Registers\n", ret); =20 return ret; } =20 +/** + * spi_nor_write_srs_ll() - Low-level Status Registers write. + * @nor: pointer to 'struct spi_nor'. + * @opcode: opcode for the status register write operation. + * @srs: pointer to status registers buffer to write. + * @len: number of status registers to write. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_srs_ll(struct spi_nor *nor, u8 opcode, const u8 *= srs, + unsigned int len) +{ + int ret, i; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + + for (i =3D 0; i < len; i++) + nor->bouncebuf[i] =3D srs[i]; + + if (nor->spimem) { + struct spi_mem_op op =3D SPI_NOR_WRSR_OP(opcode, + nor->bouncebuf, len); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D spi_nor_controller_ops_write_reg(nor, opcode, + nor->bouncebuf, len); + } + + if (ret) { + dev_dbg(nor->dev, "Error %d writing Status Registers\n", ret); + return ret; + } + + return spi_nor_wait_till_ready(nor); +} + +int spi_nor_read_srs(struct spi_nor *nor, u8 *sr1, u8 *sr2) +{ + struct spi_nor_flash_parameter *params =3D nor->params; + int ret; + + if (params->read_srs_opcode && + ((sr1 && !params->read_sr1_opcode) || (sr2 && !params->read_sr2_opcod= e))) { + u8 srs[2] =3D {}; + + ret =3D spi_nor_read_srs_ll(nor, params->read_srs_opcode, srs, 2); + if (ret) + return ret; + + if (sr1) + *sr1 =3D srs[0]; + + if (sr2) + *sr2 =3D srs[1]; + + return 0; + } + + if (sr1) { + ret =3D spi_nor_read_srs_ll(nor, params->read_sr1_opcode, sr1, 1); + if (ret) + return ret; + } + + if (sr2) { + if (params->read_sr2_opcode) { + ret =3D spi_nor_read_srs_ll(nor, params->read_sr2_opcode, sr2, 1); + if (ret) + return ret; + } else { + /* Make sure the QE bit is persistently kept */ + if (spi_nor_get_protocol_width(nor->read_proto) =3D=3D 4 || + spi_nor_get_protocol_width(nor->write_proto) =3D=3D 4) + *sr2 =3D params->qe_mask[1]; + } + } + + return 0; +} + +int spi_nor_write_srs(struct spi_nor *nor, const u8 *sr1, const u8 *sr2) +{ + struct spi_nor_flash_parameter *params =3D nor->params; + int ret; + + if (nor->flags & SNOR_F_HAS_16BIT_SR) { + u8 srs[2]; + + if (!sr1 || !sr2) { + ret =3D spi_nor_read_srs_ll(nor, params->read_srs_opcode, srs, 2); + if (ret) + return ret; + } + + if (sr1) + srs[0] =3D *sr1; + if (sr2) + srs[1] =3D *sr2; + + return spi_nor_write_srs_ll(nor, params->write_srs_opcode, srs, 2); + } + + if (sr1) { + ret =3D spi_nor_write_srs_ll(nor, params->write_sr1_opcode, sr1, 1); + if (ret) + return ret; + } + + if (sr2 && params->read_sr2_opcode) { + ret =3D spi_nor_write_srs_ll(nor, params->write_sr2_opcode, sr2, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * spi_nor_generic_quad_enable() - Read the status registers, + * apply the QE bit mask, + * write the status registers, + * read them back and check the content. + * + * @nor: pointer to 'struct spi_nor' + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_generic_quad_enable(struct spi_nor *nor) +{ + u8 *qe_mask =3D nor->params->qe_mask; + u8 srs[2] =3D {}, tmp[2] =3D {}; + int ret; + + if (!qe_mask[0] && !qe_mask[1]) + return 0; + + ret =3D spi_nor_read_srs(nor, &srs[0], &srs[1]); + if (ret) + return ret; + + if (srs[0] & qe_mask[0] || srs[1] & qe_mask[1]) + return 0; + + srs[0] |=3D qe_mask[0]; + srs[1] |=3D qe_mask[1]; + + if (nor->flags & SNOR_F_HAS_16BIT_SR) + ret =3D spi_nor_write_srs(nor, &srs[0], &srs[1]); + else + ret =3D spi_nor_write_srs(nor, + qe_mask[0] ? &srs[0] : NULL, + qe_mask[1] ? &srs[1] : NULL); + if (ret) + return ret; + + ret =3D spi_nor_read_srs(nor, &tmp[0], &tmp[1]); + if (ret) + return ret; + + if (srs[0] !=3D tmp[0] || srs[1] !=3D tmp[1]) + return -EINVAL; + + return 0; +} + /** * spi_nor_erase_die() - Erase the entire die. * @nor: pointer to 'struct spi_nor'. @@ -1904,106 +1701,6 @@ static int spi_nor_erase(struct mtd_info *mtd, stru= ct erase_info *instr) return ret; } =20 -/** - * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Stat= us - * Register 1. - * @nor: pointer to a 'struct spi_nor' - * - * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI mem= ories. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) -{ - int ret; - - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); - if (ret) - return ret; - - if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) - return 0; - - nor->bouncebuf[0] |=3D SR1_QUAD_EN_BIT6; - - return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); -} - -/** - * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Stat= us - * Register 2. - * @nor: pointer to a 'struct spi_nor'. - * - * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI mem= ories. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) -{ - int ret; - - if (nor->flags & SNOR_F_NO_READ_CR) - return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); - - ret =3D spi_nor_read_cr(nor, nor->bouncebuf); - if (ret) - return ret; - - if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) - return 0; - - nor->bouncebuf[0] |=3D SR2_QUAD_EN_BIT1; - - return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); -} - -/** - * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. - * @nor: pointer to a 'struct spi_nor' - * - * Set the Quad Enable (QE) bit in the Status Register 2. - * - * This is one of the procedures to set the QE bit described in the SFDP - * (JESD216 rev B) specification but no manufacturer using this procedure = has - * been identified yet, hence the name of the function. - * - * Return: 0 on success, -errno otherwise. - */ -int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) -{ - u8 *sr2 =3D nor->bouncebuf; - int ret; - u8 sr2_written; - - /* Check current Quad Enable bit value. */ - ret =3D spi_nor_read_sr2(nor, sr2); - if (ret) - return ret; - if (*sr2 & SR2_QUAD_EN_BIT7) - return 0; - - /* Update the Quad Enable bit. */ - *sr2 |=3D SR2_QUAD_EN_BIT7; - - ret =3D spi_nor_write_sr2(nor, sr2); - if (ret) - return ret; - - sr2_written =3D *sr2; - - /* Read back and check it. */ - ret =3D spi_nor_read_sr2(nor, sr2); - if (ret) - return ret; - - if (*sr2 !=3D sr2_written) { - dev_dbg(nor->dev, "SR2: Read back test failed\n"); - return -EIO; - } - - return 0; -} - static const struct spi_nor_manufacturer *manufacturers[] =3D { &spi_nor_atmel, &spi_nor_eon, @@ -2494,6 +2191,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32= *hwcaps) { struct spi_nor_flash_parameter *params =3D nor->params; unsigned int cap; + u8 opcode; =20 /* X-X-X modes are not supported yet, mask them all. */ *hwcaps &=3D ~SNOR_HWCAPS_X_X_X; @@ -2525,14 +2223,14 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u= 32 *hwcaps) *hwcaps &=3D ~BIT(cap); } =20 - /* Some SPI controllers might not support CR read opcode. */ - if (!(nor->flags & SNOR_F_NO_READ_CR)) { - struct spi_mem_op op =3D SPI_NOR_RDCR_OP(nor->bouncebuf); - + /* Some SPI controllers might not support reading SR2 */ + opcode =3D nor->params->read_sr2_opcode; + if (opcode) { + struct spi_mem_op op =3D SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, 1); spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 if (!spi_mem_supports_op(nor->spimem, &op)) - nor->flags |=3D SNOR_F_NO_READ_CR; + nor->params->read_sr2_opcode =3D 0; } } =20 @@ -3106,11 +2804,14 @@ static void spi_nor_init_default_params(struct spi_= nor *nor) const struct flash_info *info =3D nor->info; struct device_node *np =3D spi_nor_get_flash_node(nor); =20 - params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; - params->otp.org =3D info->otp; - - /* Default to 16-bit Write Status (01h) Command */ + /* Default to 16-bit Read/Write Status commands */ nor->flags |=3D SNOR_F_HAS_16BIT_SR; + params->read_srs_opcode =3D SPINOR_OP_RDSR; + params->write_srs_opcode =3D SPINOR_OP_WRSR; + params->quad_enable =3D spi_nor_generic_quad_enable; + params->qe_mask[1] =3D BIT(1); + + params->otp.org =3D info->otp; =20 /* Set SPI NOR sizes. */ params->writesize =3D 1; @@ -3258,8 +2959,11 @@ static int spi_nor_quad_enable(struct spi_nor *nor) return 0; =20 if (!(spi_nor_get_protocol_width(nor->read_proto) =3D=3D 4 || - spi_nor_get_protocol_width(nor->write_proto) =3D=3D 4)) + spi_nor_get_protocol_width(nor->write_proto) =3D=3D 4)) { + nor->params->qe_mask[0] =3D 0; + nor->params->qe_mask[1] =3D 0; return 0; + } =20 return nor->params->quad_enable(nor); } diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index ba2d1a862c9d..d4aff914caf5 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -37,36 +37,18 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) =20 -#define SPI_NOR_RDSR_OP(buf) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \ +#define SPI_NOR_RDSR_OP(opcode, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_DATA_IN(1, buf, 0)) + SPI_MEM_OP_DATA_IN(len, buf, 0)) =20 -#define SPI_NOR_WRSR_OP(buf, len) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \ +#define SPI_NOR_WRSR_OP(opcode, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 0)) =20 -#define SPI_NOR_RDSR2_OP(buf) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_DATA_OUT(1, buf, 0)) - -#define SPI_NOR_WRSR2_OP(buf) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_DATA_OUT(1, buf, 0)) - -#define SPI_NOR_RDCR_OP(buf) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_DATA_IN(1, buf, 0)) - #define SPI_NOR_EN4B_EX4B_OP(enable) \ SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \ SPI_MEM_OP_NO_ADDR, \ @@ -130,7 +112,6 @@ enum spi_nor_option_flags { SNOR_F_HAS_4BAIT =3D BIT(4), SNOR_F_HAS_LOCK =3D BIT(5), SNOR_F_HAS_16BIT_SR =3D BIT(6), - SNOR_F_NO_READ_CR =3D BIT(7), SNOR_F_HAS_SR_TB_BIT6 =3D BIT(8), SNOR_F_HAS_4BIT_BP =3D BIT(9), SNOR_F_HAS_SR_BP3_BIT6 =3D BIT(10), @@ -375,6 +356,13 @@ struct spi_nor_otp { * @otp: SPI NOR OTP info. * @set_octal_dtr: enables or disables SPI NOR octal DTR mode. * @quad_enable: enables SPI NOR quad mode. + * @qe_mask: two bytes mask used to set/clear the QE bit + * @read_srs_opcode: opcode used to read SR1 and SR2 in one operation + * @read_sr1_opcode: opcode used to read SR1 alone + * @read_sr2_opcode: opcode used to read SR2 alone + * @write_srs_opcode: opcode used to write SR1 and SR2 in one operation + * @write_sr1_opcode: opcode used to write SR1 alone + * @write_sr2_opcode: opcode used to write SR2 alone * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. * @ready: (optional) flashes might use a different mechanism * than reading the status register to indicate they @@ -405,6 +393,13 @@ struct spi_nor_flash_parameter { =20 int (*set_octal_dtr)(struct spi_nor *nor, bool enable); int (*quad_enable)(struct spi_nor *nor); + u8 qe_mask[2]; + u8 read_srs_opcode; + u8 read_sr1_opcode; + u8 read_sr2_opcode; + u8 write_srs_opcode; + u8 write_sr1_opcode; + u8 write_sr2_opcode; int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); int (*ready)(struct spi_nor *nor); =20 @@ -633,18 +628,11 @@ int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_prep_and_lock(struct spi_nor *nor); void spi_nor_unlock_and_unprep(struct spi_nor *nor); -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); -int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, enum spi_nor_protocol reg_proto); -int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); int spi_nor_sr_ready(struct spi_nor *nor); -int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); -int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); -int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1); -int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr); -int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs); +int spi_nor_read_srs(struct spi_nor *nor, u8 *sr1, u8 *sr2); +int spi_nor_write_srs(struct spi_nor *nor, const u8 *sr1, const u8 *sr2); =20 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf); diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index fbefcef2d2e1..5d1c31edb417 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -19,7 +19,6 @@ static const char *const snor_f_names[] =3D { SNOR_F_NAME(HAS_4BAIT), SNOR_F_NAME(HAS_LOCK), SNOR_F_NAME(HAS_16BIT_SR), - SNOR_F_NAME(NO_READ_CR), SNOR_F_NAME(HAS_SR_TB_BIT6), SNOR_F_NAME(HAS_4BIT_BP), SNOR_F_NAME(HAS_SR_BP3_BIT6), diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadev= ice.c index ef1edd0add70..4070a692e968 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -23,8 +23,10 @@ gd25q256_post_bfpt(struct spi_nor *nor, * GD25Q256E | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR */ if (bfpt_header->major =3D=3D SFDP_JESD216_MAJOR && - bfpt_header->minor =3D=3D SFDP_JESD216_MINOR) - nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; + bfpt_header->minor =3D=3D SFDP_JESD216_MINOR) { + nor->params->qe_mask[0] =3D BIT(6); + nor->params->qe_mask[1] =3D 0; + } =20 return 0; } diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 18d9a00aa22e..04db42b5141e 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -131,7 +131,8 @@ static const struct flash_info issi_nor_parts[] =3D { =20 static void issi_nor_default_init(struct spi_nor *nor) { - nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; + nor->params->qe_mask[0] =3D BIT(6); + nor->params->qe_mask[1] =3D 0; } =20 static const struct spi_nor_fixups issi_fixups =3D { diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index e97f5cbd9aad..55612237c1ef 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -65,11 +65,12 @@ mx25l3255e_late_init_fixups(struct spi_nor *nor) =20 /* * SFDP of MX25L3255E is JESD216, which does not include the Quad - * Enable bit Requirement in BFPT. As a result, during BFPT parsing, - * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable. - * Therefore, it is necessary to correct this setting by late_init. + * Enable bit Requirement in BFPT. As a result, during BFPT parsing + * the quad_enable mask is reset. Therefore, it is necessary to + * correct this setting by late_init. */ - params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; + params->qe_mask[0] =3D BIT(6); + params->qe_mask[1] =3D 0; =20 /* * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte @@ -314,7 +315,8 @@ static int macronix_nor_set_octal_dtr(struct spi_nor *n= or, bool enable) =20 static void macronix_nor_default_init(struct spi_nor *nor) { - nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; + nor->params->qe_mask[0] =3D BIT(6); + nor->params->qe_mask[1] =3D 0; } =20 static int macronix_nor_late_init(struct spi_nor *nor) diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c index 7d0b145d78d8..64686b904e24 100644 --- a/drivers/mtd/spi-nor/otp.c +++ b/drivers/mtd/spi-nor/otp.c @@ -175,24 +175,24 @@ static int spi_nor_otp_lock_bit_cr(unsigned int regio= n) */ int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region) { - u8 *cr =3D nor->bouncebuf; int ret, lock_bit; + u8 sr2; =20 lock_bit =3D spi_nor_otp_lock_bit_cr(region); if (lock_bit < 0) return lock_bit; =20 - ret =3D spi_nor_read_cr(nor, cr); + ret =3D spi_nor_read_srs(nor, NULL, &sr2); if (ret) return ret; =20 /* no need to write the register if region is already locked */ - if (cr[0] & lock_bit) + if (sr2 & lock_bit) return 0; =20 - cr[0] |=3D lock_bit; + sr2 |=3D lock_bit; =20 - return spi_nor_write_16bit_cr_and_check(nor, cr[0]); + return spi_nor_write_srs(nor, NULL, &sr2); } =20 /** @@ -207,18 +207,18 @@ int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigne= d int region) */ int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region) { - u8 *cr =3D nor->bouncebuf; int ret, lock_bit; + u8 sr2; =20 lock_bit =3D spi_nor_otp_lock_bit_cr(region); if (lock_bit < 0) return lock_bit; =20 - ret =3D spi_nor_read_cr(nor, cr); + ret =3D spi_nor_read_srs(nor, NULL, &sr2); if (ret) return ret; =20 - return cr[0] & lock_bit; + return sr2 & lock_bit; } =20 static loff_t spi_nor_otp_region_start(const struct spi_nor *nor, unsigned= int region) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 4600983cb579..23b809cc958f 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -561,10 +561,21 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, val >>=3D BFPT_DWORD11_PAGE_SIZE_SHIFT; params->page_size =3D 1U << val; =20 + /* + * The standard declares various read and write status methods, some of + * them will be overloaded based on the QER field. + */ + params->read_srs_opcode =3D SPINOR_OP_RDSR; + params->read_sr1_opcode =3D SPINOR_OP_RDSR; + params->read_sr2_opcode =3D SPINOR_OP_RDCR; + params->write_srs_opcode =3D SPINOR_OP_WRSR; + params->write_sr1_opcode =3D SPINOR_OP_WRSR; + /* Quad Enable Requirements. */ switch (bfpt.dwords[SFDP_DWORD(15)] & BFPT_DWORD15_QER_MASK) { case BFPT_DWORD15_QER_NONE: - params->quad_enable =3D NULL; + params->qe_mask[0] =3D 0; + params->qe_mask[1] =3D 0; break; =20 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: @@ -572,23 +583,33 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, * Writing only one byte to the Status Register has the * side-effect of clearing Status Register 2. */ + params->write_sr1_opcode =3D 0; + fallthrough; case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: /* * Read Configuration Register (35h) instruction is not * supported. */ - nor->flags |=3D SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR; - params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; + params->read_sr2_opcode =3D 0; + nor->flags |=3D SNOR_F_HAS_16BIT_SR; + params->qe_mask[0] =3D 0; + params->qe_mask[1] =3D BIT(1); break; =20 case BFPT_DWORD15_QER_SR1_BIT6: nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; - params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; + params->qe_mask[0] =3D BIT(6); + params->qe_mask[1] =3D 0; break; =20 case BFPT_DWORD15_QER_SR2_BIT7: nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; - params->quad_enable =3D spi_nor_sr2_bit7_quad_enable; + params->qe_mask[0] =3D 0; + params->qe_mask[1] =3D BIT(7); + params->read_srs_opcode =3D 0; + params->read_sr2_opcode =3D SPINOR_OP_RDSR2; + params->write_srs_opcode =3D 0; + params->write_sr2_opcode =3D SPINOR_OP_WRSR2; break; =20 case BFPT_DWORD15_QER_SR2_BIT1: @@ -599,8 +620,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, * assumption of a 16-bit Write Status (01h) command. */ nor->flags |=3D SNOR_F_HAS_16BIT_SR; - - params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; + params->write_sr1_opcode =3D 0; + params->read_srs_opcode =3D 0; + params->qe_mask[0] =3D 0; + params->qe_mask[1] =3D BIT(1); break; =20 default: diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 19a0ad145599..2689ea21074c 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -399,8 +399,9 @@ static int cypress_nor_determine_addr_mode_by_sr1(struc= t spi_nor *nor, nor->bouncebuf); bool is3byte, is4byte; int ret; + u8 sr; =20 - ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[1]); + ret =3D spi_nor_read_srs(nor, &sr, NULL); if (ret) return ret; =20 @@ -408,7 +409,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struc= t spi_nor *nor, if (ret) return ret; =20 - is3byte =3D (nor->bouncebuf[0] =3D=3D nor->bouncebuf[1]); + is3byte =3D (nor->bouncebuf[0] =3D=3D sr); =20 op =3D (struct spi_mem_op) CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0, @@ -417,7 +418,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struc= t spi_nor *nor, if (ret) return ret; =20 - is4byte =3D (nor->bouncebuf[0] =3D=3D nor->bouncebuf[1]); + is4byte =3D (nor->bouncebuf[0] =3D=3D sr); =20 if (is3byte =3D=3D is4byte) return -EIO; @@ -1098,13 +1099,14 @@ static const struct flash_info spansion_nor_parts[]= =3D { static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor) { int ret; + u8 sr; =20 - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + ret =3D spi_nor_read_srs(nor, &sr, NULL); if (ret) return ret; =20 - if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { - if (nor->bouncebuf[0] & SR_E_ERR) + if (sr & (SR_E_ERR | SR_P_ERR)) { + if (sr & SR_E_ERR) dev_err(nor->dev, "Erase Error occurred\n"); else dev_err(nor->dev, "Programming Error occurred\n"); @@ -1124,7 +1126,7 @@ static int spansion_nor_sr_ready_and_clear(struct spi= _nor *nor) return -EIO; } =20 - return !(nor->bouncebuf[0] & SR_WIP); + return !(sr & SR_WIP); } =20 static int spansion_nor_late_init(struct spi_nor *nor) diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c index db02c14ba16f..15f8b2cbd497 100644 --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c @@ -21,16 +21,17 @@ static int sst26vf_nor_lock(struct spi_nor *nor, loff_t= ofs, u64 len) static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { int ret; + u8 cr; =20 /* We only support unlocking the entire flash array. */ if (ofs !=3D 0 || len !=3D nor->params->size) return -EINVAL; =20 - ret =3D spi_nor_read_cr(nor, nor->bouncebuf); + ret =3D spi_nor_read_srs(nor, NULL, &cr); if (ret) return ret; =20 - if (!(nor->bouncebuf[0] & SST26VF_CR_BPNV)) { + if (!(cr & SST26VF_CR_BPNV)) { dev_dbg(nor->dev, "Any block has been permanently locked\n"); return -EINVAL; } diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 235070b215d1..d746cb595b09 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -36,7 +36,7 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) =20 static u8 spi_nor_get_sr_cmp_mask(struct spi_nor *nor) { - if (!(nor->flags & SNOR_F_NO_READ_CR) && + if (nor->params->read_sr2_opcode && nor->flags & SNOR_F_HAS_SR2_CMP_BIT6) return SR2_CMP_BIT6; else @@ -207,17 +207,9 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u= 8 *sr) =20 =20 if (!sr) { - if (spi_nor_read_sr(nor, nor->bouncebuf)) + if (spi_nor_read_srs(nor, &sr_cr[0], &sr_cr[1])) return; =20 - sr_cr[0] =3D nor->bouncebuf[0]; - - if (!(nor->flags & SNOR_F_NO_READ_CR)) { - if (spi_nor_read_cr(nor, nor->bouncebuf)) - return; - } - - sr_cr[1] =3D nor->bouncebuf[0]; sr =3D sr_cr; } =20 @@ -273,20 +265,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_= t ofs, u64 len) int ret; u8 pow; =20 - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + ret =3D spi_nor_read_srs(nor, &status_old[0], &status_old[1]); if (ret) return ret; =20 - status_old[0] =3D nor->bouncebuf[0]; - - if (!(nor->flags & SNOR_F_NO_READ_CR)) { - ret =3D spi_nor_read_cr(nor, nor->bouncebuf); - if (ret) - return ret; - - status_old[1] =3D nor->bouncebuf[0]; - } - /* If nothing in our range is unlocked, we don't need to do anything */ if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) return 0; @@ -378,10 +360,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t= ofs, u64 len) (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old))) return -EINVAL; =20 - if (nor->flags & SNOR_F_NO_READ_CR) - ret =3D spi_nor_write_sr_and_check(nor, best_status_new[0]); - else - ret =3D spi_nor_write_sr_cr_and_check(nor, best_status_new); + ret =3D spi_nor_write_srs(nor, &best_status_new[0], &best_status_new[1]); if (ret) return ret; =20 @@ -409,20 +388,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, lof= f_t ofs, u64 len) int ret; u8 pow; =20 - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + ret =3D spi_nor_read_srs(nor, &status_old[0], &status_old[1]); if (ret) return ret; =20 - status_old[0] =3D nor->bouncebuf[0]; - - if (!(nor->flags & SNOR_F_NO_READ_CR)) { - ret =3D spi_nor_read_cr(nor, nor->bouncebuf); - if (ret) - return ret; - - status_old[1] =3D nor->bouncebuf[0]; - } - /* If nothing in our range is locked, we don't need to do anything */ if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) return 0; @@ -512,10 +481,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff= _t ofs, u64 len) (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new))) return -EINVAL; =20 - if (nor->flags & SNOR_F_NO_READ_CR) - ret =3D spi_nor_write_sr_and_check(nor, best_status_new[0]); - else - ret =3D spi_nor_write_sr_cr_and_check(nor, best_status_new); + ret =3D spi_nor_write_srs(nor, &best_status_new[0], &best_status_new[1]); if (ret) return ret; =20 @@ -536,20 +502,10 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, = loff_t ofs, u64 len) u8 sr_cr[2] =3D {}; int ret; =20 - ret =3D spi_nor_read_sr(nor, nor->bouncebuf); + ret =3D spi_nor_read_srs(nor, &sr_cr[0], &sr_cr[1]); if (ret) return ret; =20 - sr_cr[0] =3D nor->bouncebuf[0]; - - if (!(nor->flags & SNOR_F_NO_READ_CR)) { - ret =3D spi_nor_read_cr(nor, nor->bouncebuf); - if (ret) - return ret; - - sr_cr[1] =3D nor->bouncebuf[0]; - } - return spi_nor_is_locked_sr(nor, ofs, len, sr_cr); } =20 diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 60a7bb1f2ce4..f96a11531a09 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -481,13 +481,13 @@ static int winbond_nor_late_init(struct spi_nor *nor) * been to declare CR reads as unsupported, whereas the Jedec * specification doesn't clearly state that. In practice, all these * chips do support reading back the CR, which is needed for SWP support, - * so make sure that capability remains enabled (needed for SWP). + * so make sure that capability remains enabled. * In practice, only exclude the old W25X family (JEDEC ID: EF 30 xx) * which actually does not support this feature. */ if (nor->info->id->bytes[0] =3D=3D 0xef && nor->info->id->bytes[1] > 0x30) - nor->flags &=3D ~SNOR_F_NO_READ_CR; + params->read_sr2_opcode =3D SPINOR_OP_RDCR; =20 return 0; } diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 4b92494827b1..f0b5a1989881 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -113,20 +113,16 @@ #define SR_E_ERR BIT(5) #define SR_P_ERR BIT(6) =20 -#define SR1_QUAD_EN_BIT6 BIT(6) - #define SR_BP_SHIFT 2 =20 /* Enhanced Volatile Configuration Register bits */ #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ =20 /* Status Register 2 bits. */ -#define SR2_QUAD_EN_BIT1 BIT(1) #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */ #define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */ #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */ #define SR2_CMP_BIT6 BIT(6) -#define SR2_QUAD_EN_BIT7 BIT(7) =20 /* Supported SPI protocols */ #define SNOR_PROTO_INST_MASK GENMASK(23, 16) --=20 2.53.0 From nobody Mon Jun 8 11:05:16 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E5793E928F for ; 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arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="KHts23c6" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id BE3D31A373B; Fri, 29 May 2026 16:06:26 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 92ED4601FA; Fri, 29 May 2026 16:06:26 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9D8EC10888CC2; Fri, 29 May 2026 18:06:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1780070785; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=VPqlRCv4E0Skod+lFZWbdOPCHpUOODKJM6zUyPTQVIA=; b=KHts23c6B+5HRKt47AxjuLpAAr9Qwkf+iFefZV239Zv8SAaf0RkLeXLqmObYQfWMLxmfUo HQA6AmiSui9LCV50aQoXb/kIbfQhtIB5OlxTfHjksObKWo42jyxZbEX8hceBBHG+vcHDsi HYXkAI5js5z97WXO3TWluMs+w+s2/uSHdS08RtaHQdasBTajlphj1kfA2RyVmViNpLKH4V TH9wUwGYpV6WF/sDARvPjO8+sKuu+tf7NHXn3fi4is6vJnBMVUrFDAcXetvQ6c6zoLFN0R HBbXlF80Id7gEP1Xal4/f/UMwmOBFuJG/TUsPP4e0zFro2XTvJ3cT6I1yqaEJg== From: Miquel Raynal Date: Fri, 29 May 2026 18:05:47 +0200 Subject: [PATCH 2/5] mtd: spi-nor: Add support for the new JESD216 rev F QER field Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-2-f3ae18502d5a@bootlin.com> References: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> In-Reply-To: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea Cc: Steam Lin , Hsin-Yi Wang , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Revision F of the JEDEC JESD216 standard includes yet another supported setting in the QER 3-bit bitfield: 110b. This setting implies that the QE bit is bit 1 of SR2 (which is an already supported case) but this time it makes it very clear that both reading and writing to SR2 is supported, but not with the usual opcodes. The write operation uses an alternate WRSR2 opcode: 0x31 (instead of 0x3E) and both the reads and writes manipulate a single register at a time. Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/sfdp.c | 9 +++++++++ drivers/mtd/spi-nor/sfdp.h | 8 ++++++++ include/linux/mtd/spi-nor.h | 1 + 3 files changed, 18 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 23b809cc958f..04580f78b62b 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -626,6 +626,15 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, params->qe_mask[1] =3D BIT(1); break; =20 + case BFPT_DWORD15_QER_SR2_BIT1_1B: + nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; + params->qe_mask[0] =3D 0; + params->qe_mask[1] =3D BIT(1); + params->read_srs_opcode =3D 0; + params->write_srs_opcode =3D 0; + params->write_sr2_opcode =3D SPINOR_OP_WRSR2_ALT; + break; + default: dev_dbg(nor->dev, "BFPT QER reserved value used\n"); break; diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index f74a0eb339ea..7e52e00cbae0 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -12,6 +12,7 @@ #define SFDP_JESD216_MINOR 0 #define SFDP_JESD216A_MINOR 5 #define SFDP_JESD216B_MINOR 6 +#define SFDP_JESD216F_MINOR 10 =20 /* SFDP DWORDS are indexed from 1 but C arrays are indexed from 0. */ #define SFDP_DWORD(i) ((i) - 1) @@ -81,6 +82,12 @@ struct sfdp_bfpt { * instruction 35h. QE is set via Write Status instruction 01h with * two data bytes where bit 1 of the second byte is one. * [...] + * (from JESD216 rev F) + * - 110b: QE is bit 1 of status register 2. Status register 1 is read usi= ng + * Read Status instruction 05h. Status register2 is read using + * instruction 35h, and status register 3 is read using instructio= n 15h. + * QE is set via Write Status Register instruction 31h with one da= ta + * byte. */ #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ @@ -89,6 +96,7 @@ struct sfdp_bfpt { #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ +#define BFPT_DWORD15_QER_SR2_BIT1_1B (0x6UL << 20) /* Winbond */ =20 #define BFPT_DWORD16_EN4B_MASK GENMASK(31, 24) #define BFPT_DWORD16_EN4B_ALWAYS_4B BIT(30) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f0b5a1989881..3a55d76ea77d 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -25,6 +25,7 @@ #define SPINOR_OP_WRSR 0x01 /* Write status register 1 */ #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ +#define SPINOR_OP_WRSR2_ALT 0x31 /* Write status register 2 (alternative) = */ #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ --=20 2.53.0 From nobody Mon Jun 8 11:05:16 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C819E3E8321 for ; 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bh=/4N7pbG2DPT4RwGrIF7v8wVFXNwxLbu6ZPdrg9nGuyQ=; b=0U0EjnAYxyMVrKtee3vBgCAtBX0kln+iTluFVMneYotwweFAPJOlS9eD9tRrl9+hBgsh90 I7NrktNmSRbTTXnRcc0l9i7f25LL1TE9Q/OdIdhSyw4KuiHYT9Jzq2Lw06OBc87wdCCl3m AKut3NbFX3UhT4XHYhKMfKTwqzlhayEMJoBJpLjXY5f0wboIp36Je0WNB0xIg2D3wMjzxd Xnm+ztPXQW6w9SoiGt3T5a0gs5ypJ38VwPzzhbvmEPzc9yXSTP6EsnKWB5oiHLak5JwDZX ttHYOkUwUwcHQtq7Vw/CRZd+ehu/hvfHH+No0z6E+uYmUJQgQ9GLmlCx2b/L1g== From: Miquel Raynal Date: Fri, 29 May 2026 18:05:48 +0200 Subject: [PATCH 3/5] mtd: spi-nor: Move the SFDP header structure to a C header Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-3-f3ae18502d5a@bootlin.com> References: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> In-Reply-To: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea Cc: Steam Lin , Hsin-Yi Wang , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The sfdp_header structure is currently defined in sfdp.c, whereas the sfdp_parameter_header structure is defined in sfdp.h. In order to ease the reuse of this structure outside of the sfdp.c file, move this structure to the sfdp C header (.h). Signed-off-by: Miquel Raynal --- drivers/mtd/spi-nor/sfdp.c | 11 ----------- drivers/mtd/spi-nor/sfdp.h | 11 +++++++++++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 04580f78b62b..902506e8015e 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -34,17 +34,6 @@ =20 #define SFDP_SIGNATURE 0x50444653U =20 -struct sfdp_header { - u32 signature; /* Ox50444653U <=3D> "SFDP" */ - u8 minor; - u8 major; - u8 nph; /* 0-base number of parameter headers */ - u8 unused; - - /* Basic Flash Parameter Table. */ - struct sfdp_parameter_header bfpt_header; -}; - /* Fast Read settings. */ struct sfdp_bfpt_read { /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index 7e52e00cbae0..1e57ace6d83f 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -149,4 +149,15 @@ struct sfdp_parameter_header { u8 id_msb; }; =20 +struct sfdp_header { + u32 signature; /* Ox50444653U <=3D> "SFDP" */ + u8 minor; + u8 major; + u8 nph; /* 0-base number of parameter headers */ + u8 unused; + + /* Basic Flash Parameter Table. */ + struct sfdp_parameter_header bfpt_header; +}; + #endif /* __LINUX_MTD_SFDP_H */ --=20 2.53.0 From nobody Mon Jun 8 11:05:16 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F59A3ED3AE for ; Fri, 29 May 2026 16:06:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780070796; cv=none; b=ZLyv7W1F1sxRBh+eIwwIbdPC/ZbP8Vj5HALwTuh9AKANEkhFx8q+CmOTp6I/iQws+0tF/T0r6s9h2x66Wk9r9mrIEhKwcqUZ+WaJB3OGacQh29VAYnHxYPhOAydjrBgB9P5BAcSh08TvlUqQ1RkGjUANbe4nnQpV/9ipRNO1yBg= ARC-Message-Signature: i=1; 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Fri, 29 May 2026 16:06:31 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 47810601FA; Fri, 29 May 2026 16:06:31 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id AAF4910888CBC; Fri, 29 May 2026 18:06:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1780070790; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ceSN1UB7XuX/Q+HvboACVRVvRYCfpdddjqEY29VYqUI=; b=NHLTQMYW6t+JdGr2J0xM7jt8hcwIcyT5hEamJmPaRLAVkVhd6D7CMcxWAyC2kFJqBTq1Ox X8EV1gwrWsrcHuNvr/6mtycj+GdqochIWjDn1zVz1p3Pe2LcUkCedj2yyoX96CpFefY24Q HMqFZcDuT9Te8idXnQEI2M59a6ZiMBPNZzUD6ozqoq++5hnz3KAfnZ2JtUcXMUHz6Qq+vW cmKfeGRKlqdY8m7+IK/46o9tm3/fIV2LiInLtYQIhm5ti6gOQAxkoTfBJaCLkQhpzQdL8u /QK4B+g9HVb++mwFbRg2tMSIoSrbhKZ7EhNrRXFeGxRQ/MgUl/SH12EkCRgmtQ== From: Miquel Raynal Date: Fri, 29 May 2026 18:05:49 +0200 Subject: [PATCH 4/5] mtd: spi-nor: winbond: Add support for W25Q02RV-M Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-4-f3ae18502d5a@bootlin.com> References: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> In-Reply-To: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea Cc: Steam Lin , Hsin-Yi Wang , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 There is an ID collision with the chip of same density from the JV family. Both chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower). As a significant difference, RV chips identify themselves as supporting the new SFDP (rev F) field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal --- + cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id ef7022 + cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer winbond + xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 534644500a0101ff00080117800000ff84010102e00000ffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffe520fbffffffff7f44eb086b083b42bbfeffffffffff 0000ffff44eb0c200f5210d800001602a60081e214dde9e378477a757a75 f7a4d55c39f66dffe970f9a50000000000002c0c000000006655ffff0f00 0000060d44bd27ed080dffffffffff8a00fe21ffdcff + sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp fe929abb1ba38dd6a8668200051298a8140bfeb56bd6d58f56b86b074a150f12 /sys/bus/= spi/devices/spi0.0/spi-nor/sfdp + cat /sys/kernel/debug/spi-nor/spi0.0/capabilities Supported read modes by the flash 1S-1S-1S opcode 0x13 mode cycles 0 dummy cycles 0 1S-1S-2S opcode 0x3c mode cycles 0 dummy cycles 8 1S-2S-2S opcode 0xbc mode cycles 2 dummy cycles 2 1S-1S-4S opcode 0x6c mode cycles 0 dummy cycles 8 1S-4S-4S opcode 0xec mode cycles 2 dummy cycles 4 4S-4S-4S opcode 0xec mode cycles 2 dummy cycles 4 Supported page program modes by the flash 1S-1S-1S opcode 0x12 1S-1S-4S opcode 0x34 + cat /sys/kernel/debug/spi-nor/spi0.0/params name (null) id ef 70 22 00 00 00 size 256 MiB write size 1 page size 256 address nbytes 4 flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS= _4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6 opcodes read 0xec dummy cycles 6 erase 0xdc program 0x34 8D extension repeat protocols read 1S-4S-4S write 1S-1S-4S register 1S-1S-1S erase commands 21 (4.00 KiB) [1] dc (64.0 KiB) [3] c7 (256 MiB) sector map region (in hex) | erase mask | overlaid ------------------+------------+--------- 00000000-0fffffff | [ 3] | no locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0fffffff | unlocked | 4096 + dd 'if=3D/dev/urandom' 'of=3D./spi_test' 'bs=3D1M' 'count=3D2' [ 11.527038] random: crng init done 2+0 records in 2+0 records out + mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + hexdump spi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0200000 + sha256sum spi_read 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read + mtd_debug write /dev/mtd0 0 2097152 spi_test Copied 2097152 bytes from spi_test to address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + sha256sum spi_read spi_test 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test + mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + sha256sum spi_read spi_test 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test + mtd_debug info /dev/mtd0 mtd.type =3D MTD_NORFLASH mtd.flags =3D MTD_CAP_NORFLASH mtd.size =3D 268435456 (256M) mtd.erasesize =3D 65536 (64K) mtd.writesize =3D 1 mtd.oobsize =3D 0 regions =3D 0 + alias 'show_sectors=3Dgrep -A4 "locked sectors" /sys/kernel/debug/spi-nor= /spi0.0/params' + flash_lock -u /dev/mtd0 + flash_lock -i /dev/mtd0 Device: /dev/mtd0 Start: 0 Len: 0x10000000 Lock status: unlocked Return code: 0 + mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash + mtd_debug write /dev/mtd0 0 2097152 spi_test Copied 2097152 bytes from spi_test to address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + sha256sum spi_read spi_test 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0fffffff | unlocked | 4096 + flash_lock -l /dev/mtd0 + flash_lock -i /dev/mtd0 Device: /dev/mtd0 Start: 0 Len: 0x10000000 Lock status: locked Return code: 1 + mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + sha256sum spi_read spi_test 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test + dd 'if=3D/dev/urandom' 'of=3D./spi_test2' 'bs=3D1M' 'count=3D2' 2+0 records in 2+0 records out + mtd_debug write /dev/mtd0 0 2097152 spi_test2 Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read2 Copied 2097152 bytes from address 0x00000000 in flash to spi_read2 + sha256sum spi_read spi_read2 spi_test spi_test2 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read2 32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test 4b1329df073cd497567d8cb6878aa20af6af71df98cc7c445d31a69eaf0d69f1 spi_test2 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0fffffff | locked | 4096 + flash_lock -u /dev/mtd0 + cat /sys/class/mtd/mtd0/size + size=3D268435456 + cat /sys/class/mtd/mtd0/erasesize + bs=3D65536 + grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params + sed -e 's/.*unlocked | //' + nsectors=3D4096 + ss=3D65536 + bps=3D1 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 268304384 2 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0ffdffff | unlocked | 4094 0ffe0000-0fffffff | locked | 2 + flash_lock -u /dev/mtd0 268304384 1 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0ffeffff | unlocked | 4095 0fff0000-0fffffff | locked | 1 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 260046848 128 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0f7fffff | unlocked | 3968 0f800000-0fffffff | locked | 128 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 0 2 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0001ffff | locked | 2 00020000-0fffffff | unlocked | 4094 + flash_lock -u /dev/mtd0 65536 1 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0000ffff | locked | 1 00010000-0fffffff | unlocked | 4095 + all_but_one=3D4095 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 65536 4095 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0000ffff | unlocked | 1 00010000-0fffffff | locked | 4095 + flash_lock -u /dev/mtd0 65536 1 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0001ffff | unlocked | 2 00020000-0fffffff | locked | 4094 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 0 4095 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0ffeffff | locked | 4095 0fff0000-0fffffff | unlocked | 1 + flash_lock -u /dev/mtd0 268304384 1 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0ffdffff | locked | 4094 0ffe0000-0fffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 53 +++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 46 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index f96a11531a09..04ba8fd44a6a 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -128,7 +128,9 @@ static int winbond_nor_multi_die_ready(struct spi_nor *= nor) } =20 static int -winbond_nor_multi_die_post_sfdp_fixups(struct spi_nor *nor) +winbond_nor_multi_die_post_sfdp_fixups(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) { /* * SFDP supports dice numbers, but this information is only available in @@ -142,8 +144,45 @@ winbond_nor_multi_die_post_sfdp_fixups(struct spi_nor = *nor) return 0; } =20 -static const struct spi_nor_fixups winbond_nor_multi_die_fixups =3D { - .post_sfdp =3D winbond_nor_multi_die_post_sfdp_fixups, +static bool is_w25qxxrv(struct spi_nor *nor) +{ + struct sfdp_header *sfdp_h =3D (struct sfdp_header *)nor->sfdp->dwords; + + /* + * W25QxxRV chips re-use the same ID as the W25QxxJV family. + * + * Chips are very similar, W25QxxRV brings mostly performance and power + * consumption improvements. The RV family does not require the multi + * die fixup. + * + * They can be distinguished based on their SFDP minor revision: + * W25QxxJV: JESD216A, minor revision =3D=3D 05h + * W25Q512/01/02JV: JESD216B, minor revision =3D=3D 06h + * W25QxxRV: JESD216F, minor revision >=3D 0Ah + */ + return sfdp_h->minor >=3D SFDP_JESD216F_MINOR; +} + +static int w25qxxjv_rv_post_bfpt_fixups(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + int ret; + + if (!is_w25qxxrv(nor)) { + /* Only 1Gb and 2Gb variants are affected */ + if (nor->params->size =3D=3D SZ_128M || nor->params->size =3D=3D SZ_256M= ) { + ret =3D winbond_nor_multi_die_post_sfdp_fixups(nor, bfpt_header, bfpt); + if (ret) + return ret; + } + } + + return 0; +} + +static const struct spi_nor_fixups w25qxxjv_rv_fixups =3D { + .post_bfpt =3D w25qxxjv_rv_post_bfpt_fixups, }; =20 static const struct flash_info winbond_nor_parts[] =3D { @@ -230,7 +269,7 @@ static const struct flash_info winbond_nor_parts[] =3D { .id =3D SNOR_ID(0xef, 0x40, 0x21), .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, - .fixups =3D &winbond_nor_multi_die_fixups, + .fixups =3D &w25qxxjv_rv_fixups, }, { .id =3D SNOR_ID(0xef, 0x50, 0x12), .name =3D "w25q20bw", @@ -317,13 +356,13 @@ static const struct flash_info winbond_nor_parts[] = =3D { .id =3D SNOR_ID(0xef, 0x70, 0x21), .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, - .fixups =3D &winbond_nor_multi_die_fixups, + .fixups =3D &w25qxxjv_rv_fixups, }, { - /* W25Q02JV-M */ + /* W25Q02JV-M, W25Q02RV-M */ .id =3D SNOR_ID(0xef, 0x70, 0x22), .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, - .fixups =3D &winbond_nor_multi_die_fixups, + .fixups =3D &w25qxxjv_rv_fixups, }, { .id =3D SNOR_ID(0xef, 0x71, 0x19), .name =3D "w25m512jv", --=20 2.53.0 From nobody Mon Jun 8 11:05:16 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5314F3EF0D0 for ; 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bh=JxIUBrcmONwFUKDF6hmKjVyMK9wJGe97t8BD5wy5c6s=; b=KsdqT7O7Aq/uoV2EdPC132ifqF1kkR1ZfSeHeH9ngEbv2C+ukBL3/AxbvIu+dqTTpsiLCv vXSNA8YpFbIf4M56Rtiq/Y9SyCMmn27wUFH9R7WAx5LPnIlbYJbqPrytYBYtRs5/0fTw5s iAwhFZs0qxSEk0lOIcJtxI5qWHduzSTBfoc7vCFIeG9E/yKKI6coLytL/Nm1is+WpK08Lw +ERhGqf6jeZM+DbPdHXqJv3HHH0wAIBnQo6piSxpFD7Bh3uAn14kSuos8DeMnG3J/vie5D SWLoopiir4nArf21qb7tL4pKKa/tR8pypoD6ZLJFo5I9lCPBqsTnS0r1LbREQg== From: Miquel Raynal Date: Fri, 29 May 2026 18:05:50 +0200 Subject: [PATCH 5/5] mtd: spi-nor: winbond: Add support for W25Q51RV-M Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-5-f3ae18502d5a@bootlin.com> References: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> In-Reply-To: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea Cc: Steam Lin , Hsin-Yi Wang , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 There is an ID collision with the chip of same density from the JV family. Both chips are very similar in practice, it is mostly a matter of electrical differences (mostly power consumption being lower). As a significant difference, RV chips identify themselves as supporting the new SFDP (rev F) field which forces an alternate write SR2 opcode (0x31). Signed-off-by: Miquel Raynal --- + cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id ef4020 + cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer winbond + xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 534644500a0101ff00080117800000ff84010102e00000ffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffe520f3ffffffff1f44eb086b083b42bbfeffffffffff 0000ffff44eb0c200f5210d800001602a60081e214dde96376337a757a75 f7a4d55c39f66dffe970f9a50000000000002c0c0000000066ffffff0000 00000000000000000000ffffffffff0a00fe21ffdcff + sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 74d21fecc7faa297b3f77f1136b1dc53f78b2a432629e226675b6384153fd9f9 /sys/bus/= spi/devices/spi0.0/spi-nor/sfdp + cat /sys/kernel/debug/spi-nor/spi0.0/capabilities Supported read modes by the flash 1S-1S-1S opcode 0x13 mode cycles 0 dummy cycles 0 1S-1S-2S opcode 0x3c mode cycles 0 dummy cycles 8 1S-2S-2S opcode 0xbc mode cycles 2 dummy cycles 2 1S-1S-4S opcode 0x6c mode cycles 0 dummy cycles 8 1S-4S-4S opcode 0xec mode cycles 2 dummy cycles 4 4S-4S-4S opcode 0xec mode cycles 2 dummy cycles 4 Supported page program modes by the flash 1S-1S-1S opcode 0x12 1S-1S-4S opcode 0x34 + cat /sys/kernel/debug/spi-nor/spi0.0/params name (null) id ef 40 20 00 00 00 size 64.0 MiB write size 1 page size 256 address nbytes 4 flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS= _4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6 opcodes read 0xec dummy cycles 6 erase 0xdc program 0x34 8D extension repeat protocols read 1S-4S-4S write 1S-1S-4S register 1S-1S-1S erase commands 21 (4.00 KiB) [1] dc (64.0 KiB) [3] c7 (64.0 MiB) sector map region (in hex) | erase mask | overlaid ------------------+------------+--------- 00000000-03ffffff | [ 3] | no locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03ffffff | unlocked | 1024 + dd 'if=3D/dev/urandom' 'of=3D./spi_test' 'bs=3D1M' 'count=3D2' [ 25.427347] random: crng init done 2+0 records in 2+0 records out + mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + hexdump spi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0200000 + sha256sum spi_read 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read + mtd_debug write /dev/mtd0 0 2097152 spi_test Copied 2097152 bytes from spi_test to address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + sha256sum spi_read spi_test cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test + mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + sha256sum spi_read spi_test 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test + mtd_debug info /dev/mtd0 mtd.type =3D MTD_NORFLASH mtd.flags =3D MTD_CAP_NORFLASH mtd.size =3D 67108864 (64M) mtd.erasesize =3D 65536 (64K) mtd.writesize =3D 1 mtd.oobsize =3D 0 regions =3D 0 + alias 'show_sectors=3Dgrep -A4 "locked sectors" /sys/kernel/debug/spi-nor= /spi0.0/params' + flash_lock -u /dev/mtd0 + flash_lock -i /dev/mtd0 Device: /dev/mtd0 Start: 0 Len: 0x4000000 Lock status: unlocked Return code: 0 + mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash + mtd_debug write /dev/mtd0 0 2097152 spi_test Copied 2097152 bytes from spi_test to address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + sha256sum spi_read spi_test cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03ffffff | unlocked | 1024 + flash_lock -l /dev/mtd0 + flash_lock -i /dev/mtd0 Device: /dev/mtd0 Start: 0 Len: 0x4000000 Lock status: locked Return code: 1 + mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read + sha256sum spi_read spi_test cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test + dd 'if=3D/dev/urandom' 'of=3D./spi_test2' 'bs=3D1M' 'count=3D2' 2+0 records in 2+0 records out + mtd_debug write /dev/mtd0 0 2097152 spi_test2 Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash + mtd_debug read /dev/mtd0 0 2097152 spi_read2 Copied 2097152 bytes from address 0x00000000 in flash to spi_read2 + sha256sum spi_read spi_read2 spi_test spi_test2 cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read2 cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test f506020804f91fb750e8250e091fb2f732319221a645ed575e1b6ed3553d584c spi_test2 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03ffffff | locked | 1024 + flash_lock -u /dev/mtd0 + cat /sys/class/mtd/mtd0/size + size=3D67108864 + cat /sys/class/mtd/mtd0/erasesize + bs=3D65536 + grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params + sed -e 's/.*unlocked | //' + nsectors=3D1024 + ss=3D65536 + bps=3D1 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 66977792 2 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03fdffff | unlocked | 1022 03fe0000-03ffffff | locked | 2 + flash_lock -u /dev/mtd0 66977792 1 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03feffff | unlocked | 1023 03ff0000-03ffffff | locked | 1 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 58720256 128 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-037fffff | unlocked | 896 03800000-03ffffff | locked | 128 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 0 2 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0001ffff | locked | 2 00020000-03ffffff | unlocked | 1022 + flash_lock -u /dev/mtd0 65536 1 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0000ffff | locked | 1 00010000-03ffffff | unlocked | 1023 + all_but_one=3D1023 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 65536 1023 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0000ffff | unlocked | 1 00010000-03ffffff | locked | 1023 + flash_lock -u /dev/mtd0 65536 1 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-0001ffff | unlocked | 2 00020000-03ffffff | locked | 1022 + flash_lock -u /dev/mtd0 + flash_lock -l /dev/mtd0 0 1023 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03feffff | locked | 1023 03ff0000-03ffffff | unlocked | 1 + flash_lock -u /dev/mtd0 66977792 1 + grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params locked sectors region (in hex) | status | #sectors ------------------+----------+--------- 00000000-03fdffff | locked | 1022 03fe0000-03ffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 04ba8fd44a6a..689e5822b009 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -260,7 +260,7 @@ static const struct flash_info winbond_nor_parts[] =3D { SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, .fixups =3D &w25q256_fixups, }, { - /* W25Q512JV-Q/N */ + /* W25Q512JV-Q/N, W25Q51RV-Q/N */ .id =3D SNOR_ID(0xef, 0x40, 0x20), .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, --=20 2.53.0