From nobody Mon Jun 8 11:04:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A5553E022A; Fri, 29 May 2026 15:31:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780068692; cv=none; b=ecsIuhBWPZxAjd/VPIHA/cSxdEcVd9rfyjDt09MP1RoPyLeKvnTtIakJogRtZOpj7+yYPxRl05pEu0sVKWM0ylSAEEhUapnWC2nwszw5/F4BWqaZOiGIIUt3I5/OJngDD1q9A7XvwgJbGivd6m7dx+tm12yTcTxHp/0Rt3FXTWs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780068692; c=relaxed/simple; bh=YXvNousRoGDqwqdFEWiYKe9SC5sclogXBwxPuNZK0+A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PU6+YaEsciOuO1ACgMvnmTjeBXOC6g7Yg4tj6bJZtXV/ndEssy9u0C/LBJiL0VdNQhZVfKMU1lvKmhBrTSWzmFOwcjs4V2w8tsVcs3blHbFrfyXf7as8P+U4qkHiqGEoGF08Uw71IL3wNIy4yT+0XE1GyB/WyeDtNmLIuxaT0zc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SxtO+T9L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SxtO+T9L" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0DC44C2BCB8; Fri, 29 May 2026 15:31:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780068692; bh=YXvNousRoGDqwqdFEWiYKe9SC5sclogXBwxPuNZK0+A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SxtO+T9L9YhtKBy6lwm8MY69wUzoqWiKsR2DnzlBGvEs8Ev0wMKEHp8vAx3Sk8+wc zULFulnP/A3fN8Ao6u828WtioWLxmYa4DupgccetcK9bcp0Ptc1RcBwCk4O+h3KdD/ 9mOvjuOJkDLkeCDF4Hh+rsZwTlyeHXCCXsfdIYtNVbvxT86zGx7TjZVDkc8VPnZXhC CPxxGk0yYg5jzYYzZSugzAoxqoz82ycWgDiGoDweyMlwglVjspIRIa31YVezvF16qr LgoQ5KCpH1/4LkAxi6wI/37W4VRxufzolsL8pVanrt37irrkQAdlrrisHqZ1k3/89/ Xv26fRYRaCAeA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05C67CD6E4A; Fri, 29 May 2026 15:31:32 +0000 (UTC) From: Ricardo Pardini via B4 Relay Date: Fri, 29 May 2026 17:31:24 +0200 Subject: [PATCH v2 1/2] arm64: dts: rockchip: describe PCIe Ethernet controllers on NanoPC-T6 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-rk3588-dts-rtl-eth-describe-dt-alias-v2-1-49700248143f@pardini.net> References: <20260529-rk3588-dts-rtl-eth-describe-dt-alias-v2-0-49700248143f@pardini.net> In-Reply-To: <20260529-rk3588-dts-rtl-eth-describe-dt-alias-v2-0-49700248143f@pardini.net> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Ricardo Pardini X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1935; i=ricardo@pardini.net; h=from:subject:message-id; bh=2PbNzuIjWPVmiNZE+VGSo9E5JFZNjeHgejELWlx8zA0=; b=owEBiQF2/pANAwAIATteP+Oex+3pAcsmYgBqGbFSPJENa/7M0hIsX8QZTVDKL5ybziDJ32Mcv 0CUdDRXgfOJAU8EAAEIADkWIQSsGCMM9q/qytxIiJM7Xj/jnsft6QUCahmxUhsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwwLDMACgkQO14/457H7enxQwf/f4efDbsFjixVgO0r+qirfD7qwBnLeRi +T+sYVCzBeLicYRWVses2atOVpWutNM6EPMYL9DcBsdrMuZkCRm7a2HVTQJ0Q1eqRP/qBi9RRvi pfqn6tfaduxxSvKMl1JI0/SGeYLTET2pQXF/aeQLjjl8Kr7ve6a0KDRo8l+loFH0BNWzQGcQleY oSL9DCAyMYAsTjatOIX6lhslGtVSToxmfezDpvQ9N8Ss+KF57Chv2zeAVuwQn61dlqj1KQXqsGA qKsdlfK1W2omSV0sY9Xa5mBakuqRl7zkPIT0BF9K98avb3nAXiTg461fGtw3X7DNMVLOqHrlWrg JEMpmisjdDA== X-Developer-Key: i=ricardo@pardini.net; a=openpgp; fpr=AC18230CF6AFEACADC4888933B5E3FE39EC7EDE9 X-Endpoint-Received: by B4 Relay for ricardo@pardini.net/default with auth_id=588 X-Original-From: Ricardo Pardini Reply-To: ricardo@pardini.net From: Ricardo Pardini The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125BG (r8169 family, PCI 10ec:8125) NICs, each behind its own RK3588 PCIe2x1 controller (pcie2x1l0 and pcie2x1l2). Both host bridges were already enabled by the board DT, but the Ethernet function nodes themselves were not described, leaving the kernel without DT handles on the two NICs. Describe the fixed PCI function nodes and attach ethernet0/ethernet1 aliases to them. Signed-off-by: Ricardo Pardini --- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 ++++++++++++++++++= ++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm6= 4/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 84b6b53f016ab..04c4479f08170 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -20,6 +20,8 @@ / { compatible =3D "friendlyarm,nanopc-t6", "rockchip,rk3588"; =20 aliases { + ethernet0 =3D &rtl_eth0; + ethernet1 =3D &rtl_eth1; mmc0 =3D &sdhci; mmc1 =3D &sdmmc; }; @@ -635,6 +637,20 @@ &pcie2x1l0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie2_0_rst>; status =3D "okay"; + + pcie@0,0 { + reg =3D <0x200000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + device_type =3D "pci"; + bus-range =3D <0x20 0x2f>; + + rtl_eth0: ethernet@0,0 { + compatible =3D "pci10ec,8125"; + reg =3D <0x210000 0 0 0 0>; + }; + }; }; =20 &pcie2x1l1 { @@ -651,6 +667,20 @@ &pcie2x1l2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie2_2_rst>; status =3D "okay"; + + pcie@0,0 { + reg =3D <0x400000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + device_type =3D "pci"; + bus-range =3D <0x40 0x4f>; + + rtl_eth1: ethernet@0,0 { + compatible =3D "pci10ec,8125"; + reg =3D <0x410000 0 0 0 0>; + }; + }; }; =20 &pcie30phy { --=20 2.54.0 From nobody Mon Jun 8 11:04:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A6093EFFB8; Fri, 29 May 2026 15:31:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780068692; cv=none; b=fmbSaxgHtdbwBrkPlQs3h3zv7EYws/htofa7cUFs3fWkOCplyK3L14EUh3DvUcjwknUDPcMLn8wQMifwnRL4ZfnBG1xmbljqkULUCwNWqSkwZcr6uC11b9O3LlBg+R+1GEy6DpSE+GFpACfPFMuOknAqtMUC4gTCHCqml2C2vrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780068692; c=relaxed/simple; bh=c9I9mrSZss9ipoBnXCmsbn04ME4OcIddnFHzKREDh4g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hdceUfFKiMWOHOKPC6BUl7cygBhzdYLfd2QT1ePUvQL4pc5OWQlSvBdk+JnPa5tYoxja/P7d6rGJWYuuJLoQWQOzGTJ9/5v+93IbKIczAmvOTHWKGh6Yyf+RKPqwoKPTwfd4IB903Z5JiftCGq0B59MP8PLhj1ls29gZmoBOLwY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pWWpdmpQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pWWpdmpQ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1FBD5C2BCF5; Fri, 29 May 2026 15:31:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780068692; bh=c9I9mrSZss9ipoBnXCmsbn04ME4OcIddnFHzKREDh4g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pWWpdmpQi1abzetdwtgJvS3URvDDWGCKPwfy4DeTNby7Pcjc8dxlhDvojqs3jv4pM rLoQk9wwSwQkmAsDidPJd1/RJfqqNTv1msrzGX+jNK9gvaPsdQ5baMVCOOfI23gEd8 V5vOyZuxaM8Y4jVMUun2Dkxt8Luz0ti7IphmRkY1dcKEGzcgi55RXhNWVg2ufFHujj /jYdY2PJNZaV6y7aC7sxmzkUEO88NYa6fzclj3Wazaz5zRuWKSFRIC9w9+H8vYxyKd Kb9z6FZyXLUoLKNV2RWfZfl4Stf4XDD8xrKVUQr4d5o7z5zApHm2E1gx5o4y3VvgEB ECvXRqCSO8W2Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1870BCD6E51; Fri, 29 May 2026 15:31:32 +0000 (UTC) From: Ricardo Pardini via B4 Relay Date: Fri, 29 May 2026 17:31:25 +0200 Subject: [PATCH v2 2/2] arm64: dts: rockchip: fix PCIe regulator name on NanoPC-T6 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-rk3588-dts-rtl-eth-describe-dt-alias-v2-2-49700248143f@pardini.net> References: <20260529-rk3588-dts-rtl-eth-describe-dt-alias-v2-0-49700248143f@pardini.net> In-Reply-To: <20260529-rk3588-dts-rtl-eth-describe-dt-alias-v2-0-49700248143f@pardini.net> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Ricardo Pardini X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1834; i=ricardo@pardini.net; h=from:subject:message-id; bh=0u1U7cadCrfZljLfYE+rIEFeBThAN/F4SqtY240X3PA=; b=owGbwMvMwMFoHWf/eN7xty8ZT6slMWRJbgyaWGffcDNPdKV6xeNHq87baQTt8Z/yeEvA9IXlD 90VkgIDOhn9WRgYORgsxRRZ1kgo83xb/+rUHY+OyTCDWJlApkiLNDAAAQsDX25iXqmRjpGeqbah nqGRjoGOMQMXpwBMdZ4TB8Ma5zeHZx+QylB6rWYYfenQtcPRWmabN52a9u/N/9+HllsZHfKRiy4 MSBWJzHvleiYlyftBeyp/2r9VutPUGP32b5u4IpFTz32NW8OdyprGhV/PeJgIy6z9v6/Q8s+28D ahj9eK54iGnylnufdbx+/ln9/CUmtmpn9h4Z5zjtFv/X82cTuRpmdsOr+7Jxzy5Xpw9wer0dLPD gaRa95x6vaJlX53bFm5ylEw2claP+SzRfFSA/bTL9zl3gTyPZikZK9rU7aIfeqFOb6r+WP1+5UT ympXzjXac+7X9/T7p1rzH+knTLthHZC9N/aOWXK9SKWyCNOl+Ju2SkEhNXEJcqI7pe0yPnqLLlO 5cCE3GAA= X-Developer-Key: i=ricardo@pardini.net; a=openpgp; fpr=AC18230CF6AFEACADC4888933B5E3FE39EC7EDE9 X-Endpoint-Received: by B4 Relay for ricardo@pardini.net/default with auth_id=588 X-Original-From: Ricardo Pardini Reply-To: ricardo@pardini.net From: Ricardo Pardini The GPIO-switched 3v3 regulator on the NanoPC-T6 is labeled vcc3v3_pcie2x1l0, but it is wired to and consumed by &pcie2x1l1, and its enable is the pcie_m2_1_pwren pin - i.e. it powers the M.2 slot on pcie2x1l1, not pcie2x1l0. The two soldered RTL8125 NICs on pcie2x1l0 and pcie2x1l2 instead share the always-on vcc_3v3_pcie20 rail, so nothing actually uses an "l0" switched supply. Rename the label, node name and regulator-name to vcc3v3_pcie2x1l1 so they match the controller the rail actually supplies. Signed-off-by: Ricardo Pardini --- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm6= 4/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 04c4479f08170..7d314df3f947b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -203,13 +203,13 @@ vbus5v0_usb: regulator-vbus5v0-usb { vin-supply =3D <&vcc5v0_sys>; }; =20 - vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { + vcc3v3_pcie2x1l1: regulator-vcc3v3-pcie2x1l1 { compatible =3D "regulator-fixed"; enable-active-high; gpio =3D <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie_m2_1_pwren>; - regulator-name =3D "vcc3v3_pcie2x1l0"; + regulator-name =3D "vcc3v3_pcie2x1l1"; regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; vin-supply =3D <&vcc5v0_sys>; @@ -655,7 +655,7 @@ rtl_eth0: ethernet@0,0 { =20 &pcie2x1l1 { reset-gpios =3D <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply =3D <&vcc3v3_pcie2x1l0>; + vpcie3v3-supply =3D <&vcc3v3_pcie2x1l1>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie2_1_rst>; status =3D "okay"; --=20 2.54.0