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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Yury Norov , Rasmus Villemoes , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Mieczyslaw Nalewaj , Luiz Angelo Daros de Luca X-Mailer: b4 0.15.2 Convert numeric error codes into human-readable strings by using %pe together with ERR_PTR() in dev_err() messages. Also use dev_err_probe() instead of checking for -EPROBE_DEFER. Reviewed-by: Linus Walleij Reviewed-by: Mieczyslaw Nalewaj Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/rtl8365mb.c | 51 +++++++++++++++++++++------------= ---- 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/= rtl8365mb.c index 0da048da533a..2637884fe472 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -803,8 +803,8 @@ static int rtl8365mb_phy_read(struct realtek_priv *priv= , int phy, int regnum) ret =3D rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); if (ret) { dev_err(priv->dev, - "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy, - regnum, ocp_addr, ret); + "failed to read PHY%d reg %02x @ %04x, ret %pe\n", phy, + regnum, ocp_addr, ERR_PTR(ret)); return ret; } =20 @@ -831,8 +831,8 @@ static int rtl8365mb_phy_write(struct realtek_priv *pri= v, int phy, int regnum, ret =3D rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); if (ret) { dev_err(priv->dev, - "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy, - regnum, ocp_addr, ret); + "failed to write PHY%d reg %02x @ %04x, ret %pe\n", phy, + regnum, ocp_addr, ERR_PTR(ret)); return ret; } =20 @@ -1082,8 +1082,8 @@ static void rtl8365mb_phylink_mac_config(struct phyli= nk_config *config, ret =3D rtl8365mb_ext_config_rgmii(priv, port, state->interface); if (ret) dev_err(priv->dev, - "failed to configure RGMII mode on port %d: %d\n", - port, ret); + "failed to configure RGMII mode on port %d: %pe\n", + port, ERR_PTR(ret)); return; } =20 @@ -1112,8 +1112,8 @@ static void rtl8365mb_phylink_mac_link_down(struct ph= ylink_config *config, false, false); if (ret) dev_err(priv->dev, - "failed to reset forced mode on port %d: %d\n", - port, ret); + "failed to reset forced mode on port %d: %pe\n", + port, ERR_PTR(ret)); =20 return; } @@ -1143,8 +1143,8 @@ static void rtl8365mb_phylink_mac_link_up(struct phyl= ink_config *config, rx_pause); if (ret) dev_err(priv->dev, - "failed to force mode on port %d: %d\n", port, - ret); + "failed to force mode on port %d: %pe\n", port, + ERR_PTR(ret)); =20 return; } @@ -1299,8 +1299,8 @@ static void rtl8365mb_get_ethtool_stats(struct dsa_sw= itch *ds, int port, u64 *da mib->length, &data[i]); if (ret) { dev_err(priv->dev, - "failed to read port %d counters: %d\n", port, - ret); + "failed to read port %d counters: %pe\n", port, + ERR_PTR(ret)); break; } } @@ -1652,7 +1652,8 @@ static irqreturn_t rtl8365mb_irq(int irq, void *data) return IRQ_HANDLED; =20 out_error: - dev_err(priv->dev, "failed to read interrupt status: %d\n", ret); + dev_err(priv->dev, "failed to read interrupt status: %pe\n", + ERR_PTR(ret)); =20 out_none: return IRQ_NONE; @@ -1725,10 +1726,13 @@ static int rtl8365mb_irq_setup(struct realtek_priv = *priv) /* rtl8365mb IRQs cascade off this one */ irq =3D of_irq_get(intc, 0); if (irq <=3D 0) { - if (irq !=3D -EPROBE_DEFER) - dev_err(priv->dev, "failed to get parent irq: %d\n", - irq); - ret =3D irq ? irq : -EINVAL; + if (!irq) { + dev_err(priv->dev, "failed to map IRQ\n"); + ret =3D -EINVAL; + } else { + ret =3D dev_err_probe(priv->dev, irq, + "failed to get parent irq\n"); + } goto out_put_node; } =20 @@ -1790,7 +1794,8 @@ static int rtl8365mb_irq_setup(struct realtek_priv *p= riv) ret =3D request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, "rtl8365mb", priv); if (ret) { - dev_err(priv->dev, "failed to request irq: %d\n", ret); + dev_err(priv->dev, "failed to request irq: %pe\n", + ERR_PTR(ret)); goto out_remove_irqdomain; } =20 @@ -1966,14 +1971,16 @@ static int rtl8365mb_setup(struct dsa_switch *ds) =20 ret =3D rtl8365mb_reset_chip(priv); if (ret) { - dev_err(priv->dev, "failed to reset chip: %d\n", ret); + dev_err(priv->dev, "failed to reset chip: %pe\n", + ERR_PTR(ret)); goto out_error; } =20 /* Configure switch to vendor-defined initial state */ ret =3D rtl8365mb_switch_init(priv); if (ret) { - dev_err(priv->dev, "failed to initialize switch: %d\n", ret); + dev_err(priv->dev, "failed to initialize switch: %pe\n", + ERR_PTR(ret)); goto out_error; } =20 @@ -2091,8 +2098,8 @@ static int rtl8365mb_detect(struct realtek_priv *priv) =20 ret =3D rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); 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Thu, 28 May 2026 21:30:29 -0700 (PDT) From: Luiz Angelo Daros de Luca Date: Fri, 29 May 2026 01:29:47 -0300 Subject: [net-next PATCH v9 2/8] net: dsa: realtek: rtl8365mb: use dsa helpers for port iteration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-realtek_forward-v9-2-e7c61872d923@gmail.com> References: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> In-Reply-To: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Yury Norov , Rasmus Villemoes , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Abdulkader Alrezej , Mieczyslaw Nalewaj , Luiz Angelo Daros de Luca X-Mailer: b4 0.15.2 Convert open-coded port iteration loops to use the DSA helpers and restructure rtl8365mb_setup() into clear blocking, user, and CPU port phases. This refactoring introduces the following behavioral and defensive changes: - CPU port forwarding/isolation is now explicitly configured. This is necessary to prevent egress traffic from being blocked by the new initialization loop that starts with all ports disabled (reported by Abdulkader Alrezej during series testing). - A guard check is added to the interrupt handler (rtl8365mb_irq) to safely skip ports without a virtual IRQ mapping. Since unused ports no longer receive a virq mapping, this prevents dangerous calls to handle_nested_irq(0) if a link event fires on an unmapped port. - The driver now explicitly returns -EOPNOTSUPP if a DSA cascade link port is detected. This topology is not supported yet and has historically been broken because the absence of a direct CPU port disables CPU tagging entirely, rendering the switch non-functional for DSA. - The rtl8365mb_setup() function now explicitly enforces the presence of a CPU port, returning -EINVAL if none are found. Suggested-by: Abdulkader Alrezej Reviewed-by: Linus Walleij Reviewed-by: Mieczyslaw Nalewaj Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/rtl8365mb.c | 158 +++++++++++++++++++++++++-------= ---- 1 file changed, 109 insertions(+), 49 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/= rtl8365mb.c index 2637884fe472..be7726a6e9a6 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -1554,18 +1554,15 @@ static void rtl8365mb_stats_setup(struct realtek_pr= iv *priv) { struct rtl8365mb *mb =3D priv->chip_data; struct dsa_switch *ds =3D &priv->ds; - int i; + struct dsa_port *dp; =20 /* Per-chip global mutex to protect MIB counter access, since doing * so requires accessing a series of registers in a particular order. */ mutex_init(&mb->mib_lock); =20 - for (i =3D 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p =3D &mb->ports[i]; - - if (dsa_is_unused_port(ds, i)) - continue; + dsa_switch_for_each_available_port(dp, ds) { + struct rtl8365mb_port *p =3D &mb->ports[dp->index]; =20 /* Per-port spinlock to protect the stats64 data */ spin_lock_init(&p->stats_lock); @@ -1581,13 +1578,10 @@ static void rtl8365mb_stats_teardown(struct realtek= _priv *priv) { struct rtl8365mb *mb =3D priv->chip_data; struct dsa_switch *ds =3D &priv->ds; - int i; - - for (i =3D 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p =3D &mb->ports[i]; + struct dsa_port *dp; =20 - if (dsa_is_unused_port(ds, i)) - continue; + dsa_switch_for_each_available_port(dp, ds) { + struct rtl8365mb_port *p =3D &mb->ports[dp->index]; =20 cancel_delayed_work_sync(&p->mib_work); } @@ -1646,6 +1640,9 @@ static irqreturn_t rtl8365mb_irq(int irq, void *data) for_each_set_bit(line, &line_changes, priv->num_ports) { int child_irq =3D irq_find_mapping(priv->irqdomain, line); =20 + if (!child_irq) + continue; + handle_nested_irq(child_irq); } =20 @@ -1709,13 +1706,14 @@ static int rtl8365mb_irq_disable(struct realtek_pri= v *priv) static int rtl8365mb_irq_setup(struct realtek_priv *priv) { struct rtl8365mb *mb =3D priv->chip_data; + struct dsa_switch *ds =3D &priv->ds; struct device_node *intc; + struct dsa_port *dp; u32 irq_trig; int virq; int irq; u32 val; int ret; - int i; =20 intc =3D of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); if (!intc) { @@ -1744,8 +1742,8 @@ static int rtl8365mb_irq_setup(struct realtek_priv *p= riv) goto out_put_node; } =20 - for (i =3D 0; i < priv->num_ports; i++) { - virq =3D irq_create_mapping(priv->irqdomain, i); + dsa_switch_for_each_available_port(dp, ds) { + virq =3D irq_create_mapping(priv->irqdomain, dp->index); if (!virq) { dev_err(priv->dev, "failed to create irq domain mapping\n"); @@ -1815,9 +1813,11 @@ static int rtl8365mb_irq_setup(struct realtek_priv *= priv) mb->irq =3D 0; =20 out_remove_irqdomain: - for (i =3D 0; i < priv->num_ports; i++) { - virq =3D irq_find_mapping(priv->irqdomain, i); - irq_dispose_mapping(virq); + dsa_switch_for_each_port(dp, ds) { + virq =3D irq_find_mapping(priv->irqdomain, dp->index); + + if (virq) + irq_dispose_mapping(virq); } =20 irq_domain_remove(priv->irqdomain); @@ -1832,8 +1832,9 @@ static int rtl8365mb_irq_setup(struct realtek_priv *p= riv) static void rtl8365mb_irq_teardown(struct realtek_priv *priv) { struct rtl8365mb *mb =3D priv->chip_data; + struct dsa_switch *ds =3D &priv->ds; + struct dsa_port *dp; int virq; - int i; =20 if (mb->irq) { free_irq(mb->irq, priv); @@ -1841,9 +1842,15 @@ static void rtl8365mb_irq_teardown(struct realtek_pr= iv *priv) } =20 if (priv->irqdomain) { - for (i =3D 0; i < priv->num_ports; i++) { - virq =3D irq_find_mapping(priv->irqdomain, i); - irq_dispose_mapping(virq); + /* Unused ports with a linked PHY still have an active IRQ + * mapping that must be disposed of during teardown. Loop + * through all ports. + */ + dsa_switch_for_each_port(dp, ds) { + virq =3D irq_find_mapping(priv->irqdomain, dp->index); + + if (virq) + irq_dispose_mapping(virq); } =20 irq_domain_remove(priv->irqdomain); @@ -1961,10 +1968,11 @@ static int rtl8365mb_setup(struct dsa_switch *ds) { struct realtek_priv *priv =3D ds->priv; struct rtl8365mb_cpu *cpu; - struct dsa_port *cpu_dp; + u32 downports_mask =3D 0; + u32 upports_mask =3D 0; struct rtl8365mb *mb; + struct dsa_port *dp; int ret; - int i; =20 mb =3D priv->chip_data; cpu =3D &mb->cpu; @@ -1991,46 +1999,98 @@ static int rtl8365mb_setup(struct dsa_switch *ds) else if (ret) dev_info(priv->dev, "no interrupt support\n"); =20 - /* Configure CPU tagging */ - dsa_switch_for_each_cpu_port(cpu_dp, ds) { - cpu->mask |=3D BIT(cpu_dp->index); + /* Start with all ports blocked, including unused ports */ + dsa_switch_for_each_port(dp, ds) { + struct rtl8365mb_port *p =3D &mb->ports[dp->index]; + + if (dsa_port_is_dsa(dp)) { + /* Cascading (DSA links) is not supported yet. + * Historically, the driver has always been broken + * without a dedicated CPU port because CPU tagging + * would be disabled, rendering the switch entirely + * non-functional for DSA operations. + */ + dev_err(ds->dev, + "Cascading (DSA link) not supported\n"); + ret =3D -EOPNOTSUPP; + goto out_teardown_irq; + } =20 - if (cpu->trap_port =3D=3D RTL8365MB_MAX_NUM_PORTS) - cpu->trap_port =3D cpu_dp->index; - } - cpu->enable =3D cpu->mask > 0; - ret =3D rtl8365mb_cpu_config(priv); - if (ret) - goto out_teardown_irq; + /* Set the initial STP state of all ports to DISABLED, otherwise + * ports will still forward frames to the CPU despite being + * administratively down by default. + */ + rtl8365mb_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); =20 - /* Configure ports */ - for (i =3D 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p =3D &mb->ports[i]; + /* Start with all port completely isolated */ + ret =3D rtl8365mb_port_set_isolation(priv, dp->index, 0); + if (ret) + goto out_teardown_irq; + + /* Disable learning */ + ret =3D rtl8365mb_port_set_learning(priv, dp->index, false); + if (ret) + goto out_teardown_irq; + + /* Set up per-port private data */ + p->priv =3D priv; + p->index =3D dp->index; =20 - if (dsa_is_unused_port(ds, i)) + /* Collect CPU ports. If we support cascade switches, it should + * also include the upstream DSA ports. + */ + if (!dsa_port_is_cpu(dp)) + continue; + + upports_mask |=3D BIT(dp->index); + } + + /* Configure user ports */ + dsa_switch_for_each_port(dp, ds) { + if (!dsa_port_is_user(dp)) continue; =20 /* Forward only to the CPU */ - ret =3D rtl8365mb_port_set_isolation(priv, i, cpu->mask); + ret =3D rtl8365mb_port_set_isolation(priv, dp->index, + upports_mask); if (ret) goto out_teardown_irq; =20 - /* Disable learning */ - ret =3D rtl8365mb_port_set_learning(priv, i, false); + /* If we support cascade switches, it should also include the + * downstream DSA ports. + */ + downports_mask |=3D BIT(dp->index); + } + + /* Configure CPU tagging */ + /* If we support cascade switches, it should also include the upstream + * DSA ports. + */ + dsa_switch_for_each_cpu_port(dp, ds) { + /* Use the first CPU port as trap_port */ + if (cpu->trap_port =3D=3D RTL8365MB_MAX_NUM_PORTS) + cpu->trap_port =3D dp->index; + + /* Forward to all user ports */ + ret =3D rtl8365mb_port_set_isolation(priv, dp->index, + downports_mask); if (ret) goto out_teardown_irq; + } =20 - /* Set the initial STP state of all ports to DISABLED, otherwise - * ports will still forward frames to the CPU despite being - * administratively down by default. - */ - rtl8365mb_port_stp_state_set(ds, i, BR_STATE_DISABLED); + cpu->mask =3D upports_mask; + cpu->enable =3D cpu->mask > 0; =20 - /* Set up per-port private data */ - p->priv =3D priv; - p->index =3D i; + if (!cpu->enable) { + dev_err(priv->dev, "no upstream (CPU, Link) port defined\n"); + ret =3D -EINVAL; + goto out_teardown_irq; } =20 + ret =3D rtl8365mb_cpu_config(priv); + if (ret) + goto out_teardown_irq; + ret =3D rtl8365mb_port_change_mtu(ds, cpu->trap_port, ETH_DATA_LEN); if (ret) goto out_teardown_irq; --=20 2.54.0 From nobody Sun Jun 7 02:07:40 2026 Received: from mail-qt1-f178.google.com (mail-qt1-f178.google.com [209.85.160.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1DA730EF7B for ; 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Thu, 28 May 2026 21:30:36 -0700 (PDT) Received: from tresc054937.tre-sc.gov.br ([187.65.210.13]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5172ebc7d23sm9260991cf.29.2026.05.28.21.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 21:30:36 -0700 (PDT) From: Luiz Angelo Daros de Luca Date: Fri, 29 May 2026 01:29:48 -0300 Subject: [net-next PATCH v9 3/8] net: dsa: realtek: rtl8365mb: prepare for multiple source files Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-realtek_forward-v9-3-e7c61872d923@gmail.com> References: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> In-Reply-To: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Yury Norov , Rasmus Villemoes , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Mieczyslaw Nalewaj , Luiz Angelo Daros de Luca X-Mailer: b4 0.15.2 From: Alvin =C5=A0ipraga Rename rtl8365mb.c to rtl8365mb_main.c in preparation for subsequent commits which add additional source files to the driver. The trailing backslash in the Makefile is deliberate. It allows for new files to be added without clobbering git history. Signed-off-by: Alvin =C5=A0ipraga Reviewed-by: Linus Walleij Reviewed-by: Mieczyslaw Nalewaj Co-developed-by: Luiz Angelo Daros de Luca Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/Makefile | 1 + drivers/net/dsa/realtek/{rtl8365mb.c =3D> rtl8365mb_main.c} | 0 2 files changed, 1 insertion(+) diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Mak= efile index 17367bcba496..3f986e04912f 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -16,3 +16,4 @@ ifdef CONFIG_NET_DSA_REALTEK_RTL8366RB_LEDS rtl8366-objs +=3D rtl8366rb-leds.o endif obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) +=3D rtl8365mb.o +rtl8365mb-objs :=3D rtl8365mb_main.o \ diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/= rtl8365mb_main.c similarity index 100% rename from drivers/net/dsa/realtek/rtl8365mb.c rename to drivers/net/dsa/realtek/rtl8365mb_main.c --=20 2.54.0 From nobody Sun Jun 7 02:07:40 2026 Received: from mail-qt1-f181.google.com (mail-qt1-f181.google.com [209.85.160.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95C482E7391 for ; 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Thu, 28 May 2026 21:30:44 -0700 (PDT) Received: from tresc054937.tre-sc.gov.br ([187.65.210.13]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5172ebc7d23sm9260991cf.29.2026.05.28.21.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 21:30:43 -0700 (PDT) From: Luiz Angelo Daros de Luca Date: Fri, 29 May 2026 01:29:49 -0300 Subject: [net-next PATCH v9 4/8] net: dsa: realtek: rtl8365mb: add table lookup interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-realtek_forward-v9-4-e7c61872d923@gmail.com> References: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> In-Reply-To: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Yury Norov , Rasmus Villemoes , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Mieczyslaw Nalewaj , Luiz Angelo Daros de Luca X-Mailer: b4 0.15.2 From: Alvin =C5=A0ipraga Add a generic table lookup interface to centralize access to the RTL8365MB internal tables. This interface abstracts the low-level table access logic and will be used by subsequent commits to implement FDB and VLAN operations. Signed-off-by: Alvin =C5=A0ipraga Reviewed-by: Linus Walleij Reviewed-by: Mieczyslaw Nalewaj Co-developed-by: Luiz Angelo Daros de Luca Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/Makefile | 1 + drivers/net/dsa/realtek/rtl8365mb_table.c | 214 ++++++++++++++++++++++++++= ++++ drivers/net/dsa/realtek/rtl8365mb_table.h | 138 +++++++++++++++++++ 3 files changed, 353 insertions(+) diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Mak= efile index 3f986e04912f..99654c4c5a3d 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -17,3 +17,4 @@ rtl8366-objs +=3D rtl8366rb-leds.o endif obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) +=3D rtl8365mb.o rtl8365mb-objs :=3D rtl8365mb_main.o \ + rtl8365mb_table.o \ diff --git a/drivers/net/dsa/realtek/rtl8365mb_table.c b/drivers/net/dsa/re= altek/rtl8365mb_table.c new file mode 100644 index 000000000000..84e2151103dd --- /dev/null +++ b/drivers/net/dsa/realtek/rtl8365mb_table.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Look-up table query interface for the rtl8365mb switch family + * + * Copyright (C) 2022 Alvin =C5=A0ipraga + */ + +#include "rtl8365mb_table.h" +#include + +/* Table access control register */ +#define RTL8365MB_TABLE_CTRL_REG 0x0500 +/* Should be one of rtl8365mb_table enum members */ +#define RTL8365MB_TABLE_CTRL_TABLE_MASK GENMASK(2, 0) +/* Should be one of rtl8365mb_table_op enum members */ +#define RTL8365MB_TABLE_CTRL_OP_MASK GENMASK(3, 3) +/* Should be one of rtl8365mb_table_l2_method enum members */ +#define RTL8365MB_TABLE_CTRL_METHOD_MASK GENMASK(7, 4) +#define RTL8365MB_TABLE_CTRL_PORT_MASK GENMASK(11, 8) + +/* Table access address register */ +#define RTL8365MB_TABLE_ACCESS_ADDR_REG 0x0501 +#define RTL8365MB_TABLE_ADDR_MASK GENMASK(12, 0) + +/* Table status register */ +#define RTL8365MB_TABLE_STATUS_REG 0x0502 +#define RTL8365MB_TABLE_STATUS_ADDRESS_MASK GENMASK(10, 0) +/* set for L3, unset for L2 */ +#define RTL8365MB_TABLE_STATUS_ADDR_TYPE_MASK GENMASK(11, 11) +#define RTL8365MB_TABLE_STATUS_HIT_STATUS_MASK GENMASK(12, 12) +#define RTL8365MB_TABLE_STATUS_BUSY_FLAG_MASK GENMASK(13, 13) +#define RTL8365MB_TABLE_STATUS_ADDRESS_EXT_MASK GENMASK(14, 14) + +/* Table read/write registers */ +#define RTL8365MB_TABLE_WRITE_BASE 0x0510 +#define RTL8365MB_TABLE_WRITE_REG(_x) \ + (RTL8365MB_TABLE_WRITE_BASE + (_x)) +#define RTL8365MB_TABLE_READ_BASE 0x0520 +#define RTL8365MB_TABLE_READ_REG(_x) \ + (RTL8365MB_TABLE_READ_BASE + (_x)) +#define RTL8365MB_TABLE_10TH_DATA_MASK GENMASK(3, 0) +#define RTL8365MB_TABLE_WRITE_10TH_REG \ + RTL8365MB_TABLE_WRITE_REG(RTL8365MB_TABLE_ENTRY_MAX_SIZE - 1) + +static int rtl8365mb_table_poll_busy(struct realtek_priv *priv) +{ + u32 val; + + return regmap_read_poll_timeout(priv->map_nolock, + RTL8365MB_TABLE_STATUS_REG, val, + !FIELD_GET(RTL8365MB_TABLE_STATUS_BUSY_FLAG_MASK, val), + 10, 10000); +} + +int rtl8365mb_table_query(struct realtek_priv *priv, + enum rtl8365mb_table table, + enum rtl8365mb_table_op op, u16 *addr, + enum rtl8365mb_table_l2_method method, + u16 port, u16 *data, size_t size) +{ + bool addr_as_input =3D true; + bool write_data =3D false; + int ret =3D 0; + u32 cmd; + u32 val; + u32 hit; + + /* Prepare target table and operation (read or write) */ + cmd =3D 0; + cmd |=3D FIELD_PREP(RTL8365MB_TABLE_CTRL_TABLE_MASK, table); + cmd |=3D FIELD_PREP(RTL8365MB_TABLE_CTRL_OP_MASK, op); + if (op =3D=3D RTL8365MB_TABLE_OP_READ && table =3D=3D RTL8365MB_TABLE_L2)= { + cmd |=3D FIELD_PREP(RTL8365MB_TABLE_CTRL_METHOD_MASK, method); + switch (method) { + case RTL8365MB_TABLE_L2_METHOD_MAC: + /* + * Method MAC requires as input the same L2 table format + * you'll get as result. However, it might only use mac + * address and FID/VID fields. + */ + write_data =3D true; + + /* METHOD_MAC does not use addr as input, but may return + * the matched index. + */ + addr_as_input =3D false; + + break; + case RTL8365MB_TABLE_L2_METHOD_ADDR: + case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT: + case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC: + case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC: + break; + case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT: + cmd |=3D FIELD_PREP(RTL8365MB_TABLE_CTRL_PORT_MASK, port); + break; + default: + return -EINVAL; + } + } else if (op =3D=3D RTL8365MB_TABLE_OP_WRITE) { + write_data =3D true; + + /* Writing to L2 does not use addr as input, as the table index + * is derived from key fields. + */ + if (table =3D=3D RTL8365MB_TABLE_L2) + addr_as_input =3D false; + } + + /* To prevent concurrent access to the look-up tables, take the regmap + * lock manually and access via the map_nolock regmap. + */ + mutex_lock(&priv->map_lock); + + /* Protect from a busy table access (i.e. previous access timeouts) */ + ret =3D rtl8365mb_table_poll_busy(priv); + if (ret) + goto out; + + /* Write entry data if writing to the table (or L2_METHOD_MAC) */ + if (write_data) { + /* bulk write data up to 9th word */ + ret =3D regmap_bulk_write(priv->map_nolock, + RTL8365MB_TABLE_WRITE_BASE, + data, + min_t(size_t, size, + RTL8365MB_TABLE_ENTRY_MAX_SIZE - + 1)); + if (ret) + goto out; + + /* 10th register uses only 4 least significant bits */ + if (size =3D=3D RTL8365MB_TABLE_ENTRY_MAX_SIZE) { + val =3D FIELD_PREP(RTL8365MB_TABLE_10TH_DATA_MASK, + data[size - 1]); + ret =3D regmap_update_bits(priv->map_nolock, + RTL8365MB_TABLE_WRITE_10TH_REG, + RTL8365MB_TABLE_10TH_DATA_MASK, + val); + } + + if (ret) + goto out; + } + + /* Write address (if needed) */ + if (addr_as_input) { + ret =3D regmap_write(priv->map_nolock, + RTL8365MB_TABLE_ACCESS_ADDR_REG, + FIELD_PREP(RTL8365MB_TABLE_ADDR_MASK, + *addr)); + if (ret) + goto out; + } + + /* Execute */ + ret =3D regmap_write(priv->map_nolock, RTL8365MB_TABLE_CTRL_REG, cmd); + if (ret) + goto out; + + /* Poll for completion */ + ret =3D rtl8365mb_table_poll_busy(priv); + if (ret) + goto out; + + /* For both reads and writes to the L2 table, check status */ + if (table =3D=3D RTL8365MB_TABLE_L2) { + ret =3D regmap_read(priv->map_nolock, RTL8365MB_TABLE_STATUS_REG, + &val); + if (ret) + goto out; + + /* Did the query find an entry? */ + hit =3D FIELD_GET(RTL8365MB_TABLE_STATUS_HIT_STATUS_MASK, val); + if (!hit) { + ret =3D -ENOENT; + goto out; + } + + /* If so, extract the address */ + *addr =3D 0; + *addr |=3D FIELD_GET(RTL8365MB_TABLE_STATUS_ADDRESS_MASK, val); + *addr |=3D FIELD_GET(RTL8365MB_TABLE_STATUS_ADDRESS_EXT_MASK, val) + << 11; + /* only set if it is a L3 address */ + *addr |=3D FIELD_GET(RTL8365MB_TABLE_STATUS_ADDR_TYPE_MASK, val) + << 12; + } + + /* Finally, get the table entry if we were reading */ + if (op =3D=3D RTL8365MB_TABLE_OP_READ) { + ret =3D regmap_bulk_read(priv->map_nolock, + RTL8365MB_TABLE_READ_BASE, + data, size); + if (ret) + goto out; + + /* For the biggest table entries, the uppermost table + * entry register has space for only one nibble. Mask + * out the remainder bits. Empirically I saw nothing + * wrong with omitting this mask, but it may prevent + * unwanted behaviour. FYI. + */ + if (size =3D=3D RTL8365MB_TABLE_ENTRY_MAX_SIZE) { + val =3D FIELD_GET(RTL8365MB_TABLE_10TH_DATA_MASK, + data[size - 1]); + data[size - 1] =3D val; + } + } + +out: + mutex_unlock(&priv->map_lock); + + return ret; +} diff --git a/drivers/net/dsa/realtek/rtl8365mb_table.h b/drivers/net/dsa/re= altek/rtl8365mb_table.h new file mode 100644 index 000000000000..41280eb6f8b0 --- /dev/null +++ b/drivers/net/dsa/realtek/rtl8365mb_table.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Look-up table query interface for the rtl8365mb switch family + * + * Copyright (C) 2022 Alvin =C5=A0ipraga + */ + +#ifndef _REALTEK_RTL8365MB_TABLE_H +#define _REALTEK_RTL8365MB_TABLE_H + +#include +#include + +#include "realtek.h" + +#define RTL8365MB_TABLE_ENTRY_MAX_SIZE 10 + +/* + * enum rtl8365mb_table - available switch tables + * @RTL8365MB_TABLE_ACL_RULE: ACL rules + * @RTL8365MB_TABLE_ACL_ACTION: ACL actions + * @RTL8365MB_TABLE_CVLAN: VLAN4k configurations + * @RTL8365MB_TABLE_L2: filtering database (2K hash table) + * @RTL8365MB_TABLE_IGMP_GROUP: IGMP group database (readonly) + * + * NOTE: Don't change the enum values. They must concur with the field + * described by @RTL8365MB_TABLE_CTRL_TABLE_MASK. + */ +enum rtl8365mb_table { + RTL8365MB_TABLE_ACL_RULE =3D 1, + RTL8365MB_TABLE_ACL_ACTION =3D 2, + RTL8365MB_TABLE_CVLAN =3D 3, + RTL8365MB_TABLE_L2 =3D 4, + RTL8365MB_TABLE_IGMP_GROUP =3D 5, +}; + +/* + * enum rtl8365mb_table_op - table query operation + * @RTL8365MB_TABLE_OP_READ: read an entry from the target table + * @RTL8365MB_TABLE_OP_WRITE: write an entry to the target table + * + * NOTE: Don't change the enum values. They must concur with the field + * described by @RTL8365MB_TABLE_CTRL_OP_MASK. + */ +enum rtl8365mb_table_op { + RTL8365MB_TABLE_OP_READ =3D 0, + RTL8365MB_TABLE_OP_WRITE =3D 1, +}; + +/* + * enum rtl8365mb_table_l2_method - look-up method for read queries of L2 = table + * @RTL8365MB_TABLE_L2_METHOD_MAC: look-up by source MAC address and FID (= or + * VID) + * @RTL8365MB_TABLE_L2_METHOD_ADDR: look-up by entry address + * @RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT: look-up next entry starting from = the + * supplied address + * @RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC: same as ADDR_NEXT but search o= nly + * unicast addresses + * @RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC: same as ADDR_NEXT but search o= nly + * multicast addresses + * @RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT: same as ADDR_NEXT_UC but + * search only entries with matching source port + * + * NOTE: Don't change the enum values. They must concur with the field + * described by @RTL8365MB_TABLE_CTRL_METHOD_MASK + */ +enum rtl8365mb_table_l2_method { + RTL8365MB_TABLE_L2_METHOD_MAC =3D 0, + RTL8365MB_TABLE_L2_METHOD_ADDR =3D 1, + RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT =3D 2, + RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC =3D 3, + RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC =3D 4, + /* + * RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC_L3 =3D 5, + * RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC_L2L3 =3D 6, + */ + RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT =3D 7, +}; + +/* + * rtl8365mb_table_query() - read from or write to a switch table + * @priv: driver context + * @table: target table, see &enum rtl8365mb_table + * @op: read or write operation, see &enum rtl8365mb_table_op + * @addr: table address. For indexed tables, this selects the entry to acc= ess. + * For L2 read queries, it is ignored as input for MAC-based lookup + * methods and used as input for address-based lookup methods. On + * successful L2 queries, it is updated with the matched entry addr= ess. + * @method: L2 table lookup method, see &enum rtl8365mb_table_l2_method. + * Ignored for non-L2 tables. + * @port: for L2 read queries using method + * %RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT, restrict the search + * to entries associated with this source port. Ignored otherwise. + * @data: data buffer used to read from or write to the table. For L2 MAC + * lookups, this buffer provides the lookup key and receives the + * matched entry contents on success. + * @size: size of @data in 16-bit words. The caller must ensure that @size + * matches the target table's entry size and does not exceed + * RTL8365MB_TABLE_ENTRY_MAX_SIZE. + * + * This function provides unified access to the internal tables of the swi= tch. + * All tables except the L2 table are simple indexed tables, where @addr + * selects the entry and @op determines whether the access is a read or a + * write operation. + * + * The content of @data is used as input when writing to tables or when + * specifying the lookup key for L2 MAC searches, and as output for all + * successful read operations. It remains unchanged during write operation= s or + * failed read operations that return %-ENOENT. For other errors during re= ad + * operations, it is undefined. + * + * The L2 table is a hash table and supports multiple lookup methods. For + * %RTL8365MB_TABLE_L2_METHOD_MAC, an entry is searched based on the MAC + * address and FID/VID fields provided in @data, using the same format as + * an L2 table entry. Address-based methods either read a specific entry + * (%RTL8365MB_TABLE_L2_METHOD_ADDR) or iterate over valid entries starting + * from @addr (%RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT and variants). When us= ing + * %RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT, only entries associated w= ith + * the specified @port are considered. + * + * On successful L2 operations, @addr is updated with the matched table ad= dress + * or allocated entry address. If no matching entry is found, or if an L2 = write + * operation fails (e.g., due to a full table during addition or a missing= entry + * during deletion), %-ENOENT is returned and @addr remains unchanged. It = is the + * caller's responsibility to map the returned error to the appropriate + * semantic error. + * + * @size must match the size of the target table entry, expressed in 16-bit + * words. + * + * Return: 0 on success, or a negative error code on failure. + */ +int rtl8365mb_table_query(struct realtek_priv *priv, + enum rtl8365mb_table table, + enum rtl8365mb_table_op op, u16 *addr, + enum rtl8365mb_table_l2_method method, + u16 port, u16 *data, size_t size); + +#endif /* _REALTEK_RTL8365MB_TABLE_H */ --=20 2.54.0 From nobody Sun Jun 7 02:07:40 2026 Received: from mail-qt1-f177.google.com (mail-qt1-f177.google.com [209.85.160.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A7351427A for ; Fri, 29 May 2026 04:30:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 28 May 2026 21:30:52 -0700 (PDT) Received: from tresc054937.tre-sc.gov.br ([187.65.210.13]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5172ebc7d23sm9260991cf.29.2026.05.28.21.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 21:30:50 -0700 (PDT) From: Luiz Angelo Daros de Luca Date: Fri, 29 May 2026 01:29:50 -0300 Subject: [net-next PATCH v9 5/8] net: dsa: realtek: rtl8365mb: add VLAN support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-realtek_forward-v9-5-e7c61872d923@gmail.com> References: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> In-Reply-To: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Yury Norov , Rasmus Villemoes , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Yury Norov , Abdulkader Alrezej , Mieczyslaw Nalewaj , Luiz Angelo Daros de Luca X-Mailer: b4 0.15.2 From: Alvin =C5=A0ipraga Realtek RTL8365MB switches (a.k.a. RTL8367C family) use two different structures for VLANs: - VLAN4K: A full table with 4096 entries defining port membership and tagging. - VLANMC: A smaller table with 32 entries used primarily for PVID assignment. In this hardware, a port's PVID must point to an index in the VLANMC table rather than a VID directly. Since the VLANMC table is limited to 32 entries, the driver implements a dynamic allocation scheme to maximize resource usage: - VLAN4K is treated by the driver as the source of truth for membership. - A VLANMC entry is only allocated when a port is configured to use a specific VID as its PVID. - VLANMC entries are deleted when no longer needed as a PVID by any port. Although VLANMC has a members field, the switch only checks membership in the VLAN4K table. This driver will use VLANMC members field as way to track which ports are using that entry as PVID. VLANMC index 0, although a valid entry, is reserved in this driver as a neutral PVID value for ports not using a specific PVID. In the subsequent RTL8367D switch family, VLANMC table was removed and PVID assignment was delegated to a dedicated set of registers. All ports start isolated, forwarding exclusively to CPU ports, and with VLAN transparent, ignoring VLAN membership. Once a member in a bridge, the port isolation is expanded to include the bridge members. When that bridge enables VLAN filtering, the VLAN transparent feature is disabled, letting the switch filter based on VLAN setup. The use of FIELD_PREP for reconstructing LO/HI values was suggested by Yury Norov. Fix for vlan_setup and vlan_filtering was suggested by Abdulkader Alrezej. Suggested-by: Yury Norov Suggested-by: Abdulkader Alrezej Signed-off-by: Alvin =C5=A0ipraga Reviewed-by: Linus Walleij Reviewed-by: Mieczyslaw Nalewaj Co-developed-by: Luiz Angelo Daros de Luca Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/Makefile | 1 + drivers/net/dsa/realtek/realtek.h | 5 + drivers/net/dsa/realtek/rtl8365mb_main.c | 321 +++++++++++ drivers/net/dsa/realtek/rtl8365mb_vlan.c | 953 +++++++++++++++++++++++++++= ++++ drivers/net/dsa/realtek/rtl8365mb_vlan.h | 39 ++ drivers/net/dsa/realtek/rtl83xx.c | 1 + 6 files changed, 1320 insertions(+) diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Mak= efile index 99654c4c5a3d..b7fc4e852fd8 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -18,3 +18,4 @@ endif obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) +=3D rtl8365mb.o rtl8365mb-objs :=3D rtl8365mb_main.o \ rtl8365mb_table.o \ + rtl8365mb_vlan.o \ diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/re= altek.h index c03485a80d93..b9c4cbdd72fb 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -54,6 +54,11 @@ struct realtek_priv { struct regmap *map; struct regmap *map_nolock; struct mutex map_lock; + /* vlan_lock protects against concurrent Read-Modify-Write operations + * on the global VLAN 4K and VLANMC tables, such as when adding or + * deleting port VLAN memberships and PVID configurations. + */ + struct mutex vlan_lock; struct mii_bus *user_mii_bus; struct mii_bus *bus; int mdio_addr; diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/rea= ltek/rtl8365mb_main.c index be7726a6e9a6..59d1e4f5a0f8 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -104,6 +104,7 @@ #include "realtek-smi.h" #include "realtek-mdio.h" #include "rtl83xx.h" +#include "rtl8365mb_vlan.h" =20 /* Family-specific data and limits */ #define RTL8365MB_PHYADDRMAX 7 @@ -292,6 +293,57 @@ #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) =20 +/* Miscellaneous port configuration register, incl. VLAN egress mode */ +#define RTL8365MB_PORT_MISC_CFG_REG_BASE 0x000E +#define RTL8365MB_PORT_MISC_CFG_REG(_p) \ + (RTL8365MB_PORT_MISC_CFG_REG_BASE + ((_p) << 5)) +#define RTL8365MB_PORT_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8365MB_PORT_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8365MB_PORT_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8365MB_PORT_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8365MB_PORT_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x0800 +#define RTL8365MB_PORT_MISC_CFG_INGRESSBW_IFG_MASK 0x0400 +#define RTL8365MB_PORT_MISC_CFG_RX_SPC_MASK 0x0200 +#define RTL8365MB_PORT_MISC_CFG_CRC_SKIP_MASK 0x0100 +#define RTL8365MB_PORT_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x0080 +#define RTL8365MB_PORT_MISC_CFG_MAC_LOOPBACK_MASK 0x0040 +/* See &rtl8365mb_vlan_egress_mode */ +#define RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x0030 +#define RTL8365MB_PORT_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0x000F + +/** + * enum rtl8365mb_vlan_egress_mode - port VLAN egress mode + * @RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL: follow untag mask in VLAN4k table= entry + * @RTL8365MB_VLAN_EGRESS_MODE_KEEP: the VLAN tag format of egressed packe= ts + * will remain the same as their ingressed format, but the priority and VID + * fields may be altered + * @RTL8365MB_VLAN_EGRESS_MODE_PRI_TAG: always egress with priority tag + * @RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP: the VLAN tag format of egressed + * packets will remain the same as their ingressed format, and neither the + * priority nor VID fields can be altered + */ +enum rtl8365mb_vlan_egress_mode { + RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL =3D 0, + RTL8365MB_VLAN_EGRESS_MODE_KEEP =3D 1, + RTL8365MB_VLAN_EGRESS_MODE_PRI_TAG =3D 2, + RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP =3D 3, +}; + +/* VLAN control register */ +#define RTL8365MB_VLAN_CTRL_REG 0x07A8 +#define RTL8365MB_VLAN_CTRL_EN_MASK 0x0001 + +/* VLAN ingress filter register */ +#define RTL8365MB_VLAN_INGRESS_REG 0x07A9 +#define RTL8365MB_VLAN_INGRESS_MASK GENMASK(10, 0) +#define RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_OFFSET(_p) (_p) +#define RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(_p) BIT(_p) + +/* VLAN "transparent" setting registers */ +#define RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG_BASE 0x09D0 +#define RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG(_p) \ + (RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG_BASE + (_p)) + /* MIB counter value registers */ #define RTL8365MB_MIB_COUNTER_BASE 0x1000 #define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) @@ -1210,6 +1262,265 @@ static void rtl8365mb_port_stp_state_set(struct dsa= _switch *ds, int port, val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); } =20 +static int rtl8365mb_port_set_transparent(struct realtek_priv *priv, + int igr_port, int egr_port, + bool enable) +{ + dev_dbg(priv->dev, "%s transparent VLAN from %d to %d\n", + enable ? "Enable" : "Disable", igr_port, egr_port); + + /* "Transparent" between the two ports means that packets forwarded by + * igr_port and egressed on egr_port will not be filtered by the usual + * VLAN membership settings. + */ + return regmap_update_bits(priv->map, + RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG(egr_port), + BIT(igr_port), enable ? BIT(igr_port) : 0); +} + +static int rtl8365mb_port_set_ingress_filtering(struct realtek_priv *priv, + int port, bool enable) +{ + /* Ingress filtering enabled: Discard VLAN-tagged frames if the port is + * not a member of the VLAN with which the packet is associated. + * Untagged packets will also be discarded unless the port has a PVID + * programmed. Priority-tagged frames are treated as untagged frames. + * + * Ingress filtering disabled: Accept all tagged and untagged frames. + */ + return regmap_update_bits(priv->map, RTL8365MB_VLAN_INGRESS_REG, + RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(port), + enable ? + RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(port) : + 0); +} + +static int +rtl8365mb_port_set_vlan_egress_mode(struct realtek_priv *priv, int port, + enum rtl8365mb_vlan_egress_mode mode) +{ + u32 val; + + val =3D FIELD_PREP(RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK, mode); + return regmap_update_bits(priv->map, + RTL8365MB_PORT_MISC_CFG_REG(port), + RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK, val); +} + +static int rtl8365mb_port_vlan_filtering(struct dsa_switch *ds, int port, + bool vlan_filtering, + struct netlink_ext_ack *extack) +{ + enum rtl8365mb_frame_ingress accepted_frame, prev_accepted_frame; + enum rtl8365mb_vlan_egress_mode mode; + struct realtek_priv *priv =3D ds->priv; + u32 configured_ports =3D 0; + struct dsa_port *dp; + u16 pvid_vid; + int ret; + + dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port, + vlan_filtering ? "enable" : "disable"); + + ret =3D rtl8365mb_vlan_port_get_framefilter(priv, port, + &prev_accepted_frame); + if (ret) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to get current framefilter"); + return ret; + } + + /* While filtering, only accepts untagged frames if PVID is enabled */ + if (vlan_filtering) { + ret =3D rtl8365mb_vlan_port_get_pvid(priv, port, &pvid_vid); + if (ret) + return ret; + + if (pvid_vid) + accepted_frame =3D RTL8365MB_FRAME_TYPE_ANY_FRAME; + else + accepted_frame =3D RTL8365MB_FRAME_TYPE_TAGGED_ONLY; + } else { + accepted_frame =3D RTL8365MB_FRAME_TYPE_ANY_FRAME; + } + + /* When vlan filter is enable/disabled in a bridge, this function is + * called for all member ports. We need to enable/disable ingress + * VLAN membership check. + */ + ret =3D rtl8365mb_port_set_ingress_filtering(priv, port, vlan_filtering); + if (ret) + return ret; + + /* However, we also enable/disable egress filtering because the switch + * still consider the egress interface VLAN membership to forward the + * traffic. We enable/disable that check disabling/enabling transparent + * VLAN between the ingress port and all other available ports. + */ + dsa_switch_for_each_available_port(dp, ds) { + /* port isolation will still keep traffic inside the bridge */ + ret =3D rtl8365mb_port_set_transparent(priv, port, dp->index, + !vlan_filtering); + if (ret) + goto undo_transparent; + + configured_ports |=3D BIT(dp->index); + } + + if (accepted_frame !=3D prev_accepted_frame) { + ret =3D rtl8365mb_vlan_port_set_framefilter(priv, port, + accepted_frame); + if (ret) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to set port framefilter"); + goto undo_transparent; + } + } + + /* When VLAN filtering is disabled, preserve frames exactly as received. + * Otherwise, the VLAN egress pipeline may still alter tag state + * according to VLAN membership and untag configuration. + */ + if (vlan_filtering) + mode =3D RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL; + else + mode =3D RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP; + + ret =3D rtl8365mb_port_set_vlan_egress_mode(priv, port, mode); + if (ret) + goto undo_set_framefilter; + + return ret; + +undo_set_framefilter: + if (prev_accepted_frame !=3D accepted_frame) + rtl8365mb_vlan_port_set_framefilter(priv, port, + prev_accepted_frame); +undo_transparent: + dsa_switch_for_each_port(dp, ds) { + if (configured_ports & BIT(dp->index)) + rtl8365mb_port_set_transparent(priv, port, dp->index, + vlan_filtering); + } + + rtl8365mb_port_set_ingress_filtering(priv, port, !vlan_filtering); + + return ret; +} + +static int rtl8365mb_port_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack) +{ + bool untagged =3D !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); + bool pvid =3D !!(vlan->flags & BRIDGE_VLAN_INFO_PVID); + u16 pvid_vid; + struct realtek_priv *priv =3D ds->priv; + int ret; + + dev_dbg(priv->dev, "add VLAN %d on port %d, %s, %s\n", + vlan->vid, port, untagged ? "untagged" : "tagged", + pvid ? "PVID" : "no PVID"); + + /* VID =3D=3D 0 is reserved in this driver */ + if (vlan->vid =3D=3D 0) { + NL_SET_ERR_MSG_MOD(extack, + "VLAN 0 is not supported by this hardware"); + return -EOPNOTSUPP; + } + + mutex_lock(&priv->vlan_lock); + + ret =3D rtl8365mb_vlan_port_get_pvid(priv, port, &pvid_vid); + if (ret) + goto out_unlock; + + /* Set PVID if needed */ + if (pvid) { + ret =3D rtl8365mb_vlan_pvid_port_set(ds, port, vlan->vid, + extack); + if (ret) + goto out_unlock; + } else { + /* or try to unset it if not */ + ret =3D rtl8365mb_vlan_pvid_port_clear(ds, port, vlan->vid); + if (ret) + goto out_unlock; + } + + /* add port to vlan4k. It knows nothing about PVID */ + ret =3D rtl8365mb_vlan_4k_port_add(ds, port, vlan, extack); + if (ret) + goto undo_set_pvid; + + ret =3D 0; + goto out_unlock; + +undo_set_pvid: + /* undo the pvid definition */ + if (pvid !=3D (pvid_vid =3D=3D vlan->vid)) { + if (pvid_vid) + (void)rtl8365mb_vlan_pvid_port_set(ds, port, pvid_vid, + NULL); + else + (void)rtl8365mb_vlan_pvid_port_clear(ds, port, + vlan->vid); + } +out_unlock: + mutex_unlock(&priv->vlan_lock); + return ret; +} + +static int rtl8365mb_port_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + bool untagged =3D !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); + bool pvid =3D !!(vlan->flags & BRIDGE_VLAN_INFO_PVID); + struct realtek_priv *priv =3D ds->priv; + int ret1, ret2; + + dev_dbg(priv->dev, "del VLAN %d on port %d, %s, %s\n", + vlan->vid, port, untagged ? "untagged" : "tagged", + pvid ? "PVID" : "no PVID"); + + mutex_lock(&priv->vlan_lock); + ret1 =3D rtl8365mb_vlan_pvid_port_clear(ds, port, vlan->vid); + ret2 =3D rtl8365mb_vlan_4k_port_del(ds, port, vlan); + mutex_unlock(&priv->vlan_lock); + + return ret1 ?: ret2; +} + +/* VLAN support is always enabled in the switch. + * + * Standalone forwarding relies on transparent VLAN mode combined with per= -port + * isolation masks restricting egress to CPU ports only. + * + */ +static int rtl8365mb_vlan_setup(struct dsa_switch *ds) +{ + struct realtek_priv *priv =3D ds->priv; + struct dsa_port *dp; + int ret; + + dsa_switch_for_each_available_port(dp, ds) { + /* Disable vlan-filtering for all ports */ + ret =3D rtl8365mb_port_vlan_filtering(ds, dp->index, false, NULL); + if (ret) { + dev_err(priv->dev, + "Failed to disable vlan filtering on port %d\n", + dp->index); + return ret; + } + } + + /* VLAN is always enabled. */ + ret =3D regmap_update_bits(priv->map, RTL8365MB_VLAN_CTRL_REG, + RTL8365MB_VLAN_CTRL_EN_MASK, + FIELD_PREP(RTL8365MB_VLAN_CTRL_EN_MASK, 1)); + return ret; +} + static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, bool enable) { @@ -2095,6 +2406,13 @@ static int rtl8365mb_setup(struct dsa_switch *ds) if (ret) goto out_teardown_irq; =20 + ds->configure_vlan_while_not_filtering =3D true; + + /* Set up VLAN */ + ret =3D rtl8365mb_vlan_setup(ds); + if (ret) + goto out_teardown_irq; + ret =3D rtl83xx_setup_user_mdio(ds); if (ret) { dev_err(priv->dev, "could not set up MDIO bus\n"); @@ -2205,6 +2523,9 @@ static const struct dsa_switch_ops rtl8365mb_switch_o= ps =3D { .teardown =3D rtl8365mb_teardown, .phylink_get_caps =3D rtl8365mb_phylink_get_caps, .port_stp_state_set =3D rtl8365mb_port_stp_state_set, + .port_vlan_add =3D rtl8365mb_port_vlan_add, + .port_vlan_del =3D rtl8365mb_port_vlan_del, + .port_vlan_filtering =3D rtl8365mb_port_vlan_filtering, .get_strings =3D rtl8365mb_get_strings, .get_ethtool_stats =3D rtl8365mb_get_ethtool_stats, .get_sset_count =3D rtl8365mb_get_sset_count, diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.c b/drivers/net/dsa/rea= ltek/rtl8365mb_vlan.c new file mode 100644 index 000000000000..374f82a2713b --- /dev/null +++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.c @@ -0,0 +1,953 @@ +// SPDX-License-Identifier: GPL-2.0 +/* VLAN configuration interface for the rtl8365mb switch family + * + * Copyright (C) 2022 Alvin =C5=A0ipraga + * + * VLAN configuration takes place in two separate domains of the switch: t= he + * VLAN4k table and the VLAN membership configuration (MC) database. While= the + * VLAN4k table is exhaustive and can be fully populated with 4096 VLAN + * configurations, the same does not hold for the VLAN membership configur= ation + * database, which is limited to 32 entries. + * + * The switch will normally only use the VLAN4k table when making forwardi= ng + * decisions. The VLAN membership configuration database is a vestigial AS= IC + * design and is only used for a few specific features in the rtl8365mb + * family. This means that the limit of 32 entries should not hinder us in + * programming a huge number of VLANs into the switch. + * + * One necessary use of the VLAN membership configuration database is for = the + * programming of a port-based VLAN ID (PVID). The PVID is programmed on a + * per-port basis via register field, which refers to a specific VLAN memb= ership + * configuration via an index 0~31. In order to maintain coherent behaviou= r on a + * port with a PVID, it is necessary to keep the VLAN configuration synchr= onized + * between the VLAN4k table and the VLAN membership configuration database. + * + * Since VLAN membership configs are a scarce resource, it will only be us= ed + * when strictly needed (i.e. a VLAN with members using PVID). Otherwise, = the + * VLAN4k will be enough. + * + * With some exceptions, the entries in both the VLAN4k table and the VLAN + * membership configuration database offer the same configuration options.= The + * differences are as follows: + * + * 1. VLAN4k entries can specify whether to use Independent or Shared VLAN + * Learning (IVL or SVL respectively). VLAN membership config entries + * cannot. This underscores the fact that VLAN membership configs are n= ot + * involved in the learning process of the ASIC. + * + * 2. VLAN membership config entries use an "enhanced VLAN ID" (efid), whi= ch has + * a range 0~8191 compared with the standard 0~4095 range of the VLAN4k + * table. This underscores the fact that VLAN membership configs can be= used + * to group ports on a layer beyond the standard VLAN configuration, wh= ich + * may be useful for ACL rules which specify alternative forwarding + * decisions. + * + * VLANMC index 0 is reserved as a neutral PVID, used for standalone ports. + * + */ + +#include "rtl8365mb_vlan.h" +#include "rtl8365mb_table.h" +#include +#include +#include + +/* CVLAN (i.e. VLAN4k) table entry layout, u16[3] */ +#define RTL8365MB_CVLAN_ENTRY_SIZE 3 /* 48-bits */ +#define RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK GENMASK(7, 0) +#define RTL8365MB_CVLAN_MBR_LO_MASK GENMASK(7, 0) +#define RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK GENMASK(15, 8) +#define RTL8365MB_CVLAN_UNTAG_LO_MASK GENMASK(7, 0) +#define RTL8365MB_CVLAN_ENTRY_D1_FID_MASK GENMASK(3, 0) +#define RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK GENMASK(4, 4) +#define RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK GENMASK(7, 5) +#define RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK GENMASK(8, 8) +#define RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK GENMASK(13, 9) +#define RTL8365MB_CVLAN_METERIDX_LO_MASK GENMASK(4, 0) +#define RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK GENMASK(14, 14) +/* extends RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK */ +#define RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK GENMASK(2, 0) +#define RTL8365MB_CVLAN_MBR_HI_MASK GENMASK(10, 8) +/* extends RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK */ +#define RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK GENMASK(5, 3) +#define RTL8365MB_CVLAN_UNTAG_HI_MASK GENMASK(10, 8) +/* extends RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK */ +#define RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK GENMASK(6, 6) +#define RTL8365MB_CVLAN_METERIDX_HI_MASK GENMASK(5, 5) + +/* VLAN member configuration registers 0~31, u16[3] */ +#define RTL8365MB_VLAN_MC_BASE 0x0728 +#define RTL8365MB_VLAN_MC_ENTRY_SIZE 4 /* 64-bit */ +#define RTL8365MB_VLAN_MC_REG(index) \ + (RTL8365MB_VLAN_MC_BASE + \ + (RTL8365MB_VLAN_MC_ENTRY_SIZE * (index))) +#define RTL8365MB_VLAN_MC_D0_MBR_MASK GENMASK(10, 0) +#define RTL8365MB_VLAN_MC_D1_FID_MASK GENMASK(3, 0) + +#define RTL8365MB_VLAN_MC_D2_VBPEN_MASK GENMASK(0, 0) +#define RTL8365MB_VLAN_MC_D2_VBPRI_MASK GENMASK(3, 1) +#define RTL8365MB_VLAN_MC_D2_ENVLANPOL_MASK GENMASK(4, 4) +#define RTL8365MB_VLAN_MC_D2_METERIDX_MASK GENMASK(10, 5) +#define RTL8365MB_VLAN_MC_D3_EVID_MASK GENMASK(12, 0) + +/* Some limits for VLAN4k/VLAN membership config entries */ +#define RTL8365MB_PRIORITYMAX 7 +#define RTL8365MB_FIDMAX 15 +#define RTL8365MB_METERMAX 63 +#define RTL8365MB_VLAN_MCMAX 31 + +/* RTL8367S supports 4k vlans (vid<=3D4095) and 32 enhanced vlans + * for VIDs up to 8191 + */ +#define RTL8365MB_MAX_4K_VID 0x0FFF /* 4095 */ +#define RTL8365MB_MAX_MC_VID 0x1FFF /* 8191 */ + + /* Port-based VID registers 0~5 - each one holds an MC index for two port= s */ +#define RTL8365MB_VLAN_PVID_CTRL_BASE 0x0700 +#define RTL8365MB_VLAN_PVID_CTRL_REG(_p) \ + (RTL8365MB_VLAN_PVID_CTRL_BASE + ((_p) >> 1)) +#define RTL8365MB_VLAN_PVID_CTRL_PORT0_MCIDX_MASK 0x001F +#define RTL8365MB_VLAN_PVID_CTRL_PORT1_MCIDX_MASK 0x1F00 +#define RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(_p) \ + (((_p) & 1) << 3) +#define RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_MASK(_p) \ + (0x1F << RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(_p)) + +/* Frame type filtering registers */ +#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_BASE 0x07aa +#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_REG(port) \ + (RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_BASE + ((port) >> 3)) +/* required as FIELD_PREP cannot use non-constant masks */ +#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_MASK(port) \ + (0x3 << RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_OFFSET(port)) +#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_OFFSET(port) \ + (((port) & 0x7) << 1) + +/* + * struct rtl8365mb_vlan4k - VLAN4k table entry + * @vid: VLAN ID (0~4095) + * @member: port mask of ports in this VLAN + * @untag: port mask of ports which untag on egress + * @fid: filter ID - only used with SVL (unused) + * @priority: priority classification (unused) + * @priority_en: enable priority (unused) + * @policing_en: enable policing (unused) + * @ivl_en: enable IVL instead of default SVL + * @meteridx: metering index (unused) + * + * This structure is used to get/set entries in the VLAN4k table. The + * VLAN4k table dictates the VLAN configuration for the switch for the + * vast majority of features. + */ +struct rtl8365mb_vlan4k { + u16 vid; + u16 member; + u16 untag; + u8 fid : 4; + u8 priority : 3; + u8 priority_en : 1; + u8 policing_en : 1; + u8 ivl_en : 1; + u8 meteridx : 6; +}; + +/* + * struct rtl8365mb_vlanmc - VLAN membership config + * @evid: Enhanced VLAN ID (0~8191) + * @member: port mask of ports in this VLAN + * @fid: filter ID - only used with SVL (unused) + * @priority: priority classification (unused) + * @priority_en: enable priority (unused) + * @policing_en: enable policing (unused) + * @meteridx: metering index (unused) + * + * This structure is used to get/set entries in the VLAN membership + * configuration database. This feature is largely vestigial, but + * still needed for at least the following features: + * - PVID configuration + * - ACL configuration + * - selection of VLAN by the CPU tag when VSEL=3D1, although the switch + * can also select VLAN based on the VLAN tag if VSEL=3D0 + * + * This is a low-level structure and it is recommended to interface with + * the VLAN membership config database via &struct rtl8365mb_vlanmc_entry. + */ +struct rtl8365mb_vlanmc { + u16 evid; + u16 member; + u8 fid : 4; + u8 priority : 3; + u8 priority_en : 1; + u8 policing_en : 1; + u8 meteridx : 6; +}; + +static int rtl8365mb_vlan_4k_read(struct realtek_priv *priv, u16 vid, + struct rtl8365mb_vlan4k *vlan4k) +{ + u16 data[RTL8365MB_CVLAN_ENTRY_SIZE]; + int val; + int ret; + + ret =3D rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN, + RTL8365MB_TABLE_OP_READ, &vid, 0, 0, + data, ARRAY_SIZE(data)); + if (ret) + return ret; + + /* Unpack table entry */ + memset(vlan4k, 0, sizeof(*vlan4k)); + vlan4k->vid =3D vid; + + val =3D FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, data[0]); + vlan4k->member =3D FIELD_PREP(RTL8365MB_CVLAN_MBR_LO_MASK, val); + val =3D FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, data[2]); + vlan4k->member |=3D FIELD_PREP(RTL8365MB_CVLAN_MBR_HI_MASK, val); + + val =3D FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, data[0]); + vlan4k->untag =3D FIELD_PREP(RTL8365MB_CVLAN_UNTAG_LO_MASK, val); + val =3D FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, data[2]); + vlan4k->untag |=3D FIELD_PREP(RTL8365MB_CVLAN_UNTAG_HI_MASK, val); + + vlan4k->fid =3D FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, data[1]); + vlan4k->priority_en =3D + FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK, data[1]); + vlan4k->priority =3D + FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK, data[1]); + vlan4k->policing_en =3D + FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK, data[1]); + + val =3D FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, data[1]); + val =3D FIELD_PREP(RTL8365MB_CVLAN_METERIDX_LO_MASK, val); + vlan4k->meteridx =3D val; + val =3D FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, data[2]); + val =3D FIELD_PREP(RTL8365MB_CVLAN_METERIDX_HI_MASK, val); + vlan4k->meteridx |=3D val; + + vlan4k->ivl_en =3D + FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK, data[1]); + + return 0; +} + +static int rtl8365mb_vlan_4k_write(struct realtek_priv *priv, + const struct rtl8365mb_vlan4k *vlan4k) +{ + u16 data[RTL8365MB_CVLAN_ENTRY_SIZE] =3D { 0 }; + u16 vid; + int val; + + /* Pack table entry value */ + val =3D FIELD_GET(RTL8365MB_CVLAN_MBR_LO_MASK, vlan4k->member); + data[0] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, val); + + val =3D FIELD_GET(RTL8365MB_CVLAN_UNTAG_LO_MASK, vlan4k->untag); + data[0] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, val); + + data[1] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, vlan4k->fid); + data[1] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK, + vlan4k->priority_en); + data[1] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK, + vlan4k->priority); + data[1] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK, + vlan4k->policing_en); + + /* FIELD_* does not play nice with struct bitfield. */ + val =3D vlan4k->meteridx; + val =3D FIELD_GET(RTL8365MB_CVLAN_METERIDX_LO_MASK, val); + data[1] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, val); + + data[1] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK, + vlan4k->ivl_en); + + val =3D FIELD_GET(RTL8365MB_CVLAN_MBR_HI_MASK, vlan4k->member); + data[2] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, val); + + val =3D FIELD_GET(RTL8365MB_CVLAN_UNTAG_HI_MASK, vlan4k->untag); + data[2] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, val); + + val =3D vlan4k->meteridx; + val =3D FIELD_GET(RTL8365MB_CVLAN_METERIDX_HI_MASK, val); + data[2] |=3D FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, val); + + vid =3D vlan4k->vid; + return rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN, + RTL8365MB_TABLE_OP_WRITE, &vid, 0, 0, + data, ARRAY_SIZE(data)); +} + +#define RTL_VLAN_ERR(msg) \ + do { \ + const char *__msg =3D (msg); \ + \ + if (extack) \ + NL_SET_ERR_MSG_FMT_MOD(extack, "%s", __msg); \ + dev_err(priv->dev, "%s", __msg); \ + } while (0) + +static int +rtl8365mb_vlan_4k_port_set(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack, + bool include) +{ + struct realtek_priv *priv =3D ds->priv; + struct rtl8365mb_vlan4k vlan4k =3D {0}; + int ret; + + dev_dbg(priv->dev, "%s VLAN %d 4K on port %d\n", + include ? "add" : "del", + vlan->vid, port); + + if (vlan->vid > RTL8365MB_MAX_4K_VID) { + RTL_VLAN_ERR("VLAN ID greater than " + __stringify(RTL8365MB_MAX_4K_VID)); + return -EINVAL; + } + + ret =3D rtl8365mb_vlan_4k_read(priv, vlan->vid, &vlan4k); + if (ret) { + RTL_VLAN_ERR("Failed to read VLAN 4k table"); + return ret; + } + + if (include) + vlan4k.member |=3D BIT(port); + else + vlan4k.member &=3D ~BIT(port); + + if (include && (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) + vlan4k.untag |=3D BIT(port); + else + vlan4k.untag &=3D ~BIT(port); + vlan4k.ivl_en =3D true; /* always use Independent VLAN Learning */ + + ret =3D rtl8365mb_vlan_4k_write(priv, &vlan4k); + if (ret) { + RTL_VLAN_ERR("Failed to write VLAN 4k table"); + return ret; + } + + return 0; +} + +/* + * rtl8365mb_vlan_4k_port_add() - Add a port to a VLAN 4K table entry + * @ds: dsa switch instance + * @port: port index + * @vlan: switchdev VLAN object containing the target VID and flags + * @extack: netlink extended ACK for error reporting + * + * Adds the specified port to the hardware VLAN 4K membership table. + * + * Context: Can sleep. Must be called with &priv->vlan_lock held. + * Takes and releases &priv->map_lock. + * Return: 0 on success, or a negative error code on failure. + */ +int rtl8365mb_vlan_4k_port_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack) +{ + struct realtek_priv *priv =3D ds->priv; + + lockdep_assert_held(&priv->vlan_lock); + + return rtl8365mb_vlan_4k_port_set(ds, port, vlan, extack, true); +} + +/* + * rtl8365mb_vlan_4k_port_del() - Remove a port from a VLAN 4K table entry + * @ds: dsa switch instance + * @port: port index + * @vlan: switchdev VLAN object containing the target VID + * + * Removes the specified port from the hardware VLAN 4K membership table. + * + * Context: Can sleep. Must be called with &priv->vlan_lock held. + * Takes and releases &priv->map_lock. + * Return: 0 on success, or a negative error code on failure. + */ +int rtl8365mb_vlan_4k_port_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct realtek_priv *priv =3D ds->priv; + + lockdep_assert_held(&priv->vlan_lock); + + return rtl8365mb_vlan_4k_port_set(ds, port, vlan, NULL, false); +} + +static int rtl8365mb_vlan_mc_read(struct realtek_priv *priv, u32 index, + struct rtl8365mb_vlanmc *vlanmc) +{ + u16 data[RTL8365MB_VLAN_MC_ENTRY_SIZE]; + int ret; + + ret =3D regmap_bulk_read(priv->map, RTL8365MB_VLAN_MC_REG(index), &data, + RTL8365MB_VLAN_MC_ENTRY_SIZE); + if (ret) + return ret; + + vlanmc->member =3D FIELD_GET(RTL8365MB_VLAN_MC_D0_MBR_MASK, data[0]); + vlanmc->fid =3D FIELD_GET(RTL8365MB_VLAN_MC_D1_FID_MASK, data[1]); + vlanmc->meteridx =3D FIELD_GET(RTL8365MB_VLAN_MC_D2_METERIDX_MASK, + data[2]); + vlanmc->policing_en =3D FIELD_GET(RTL8365MB_VLAN_MC_D2_ENVLANPOL_MASK, + data[2]); + vlanmc->priority =3D FIELD_GET(RTL8365MB_VLAN_MC_D2_VBPRI_MASK, data[2]); + vlanmc->priority_en =3D FIELD_GET(RTL8365MB_VLAN_MC_D2_VBPEN_MASK, + data[2]); + vlanmc->evid =3D FIELD_GET(RTL8365MB_VLAN_MC_D3_EVID_MASK, data[3]); + + return 0; +} + +static int rtl8365mb_vlan_mc_write(struct realtek_priv *priv, u32 index, + const struct rtl8365mb_vlanmc *vlanmc) +{ + u16 data[RTL8365MB_VLAN_MC_ENTRY_SIZE] =3D { 0 }; + int ret; + + data[0] |=3D FIELD_PREP(RTL8365MB_VLAN_MC_D0_MBR_MASK, vlanmc->member); + data[1] |=3D FIELD_PREP(RTL8365MB_VLAN_MC_D1_FID_MASK, vlanmc->fid); + data[2] |=3D FIELD_PREP(RTL8365MB_VLAN_MC_D2_METERIDX_MASK, + vlanmc->meteridx); + data[2] |=3D FIELD_PREP(RTL8365MB_VLAN_MC_D2_ENVLANPOL_MASK, + vlanmc->policing_en); + data[2] |=3D + FIELD_PREP(RTL8365MB_VLAN_MC_D2_VBPRI_MASK, vlanmc->priority); + data[2] |=3D FIELD_PREP(RTL8365MB_VLAN_MC_D2_VBPEN_MASK, + vlanmc->priority_en); + data[3] |=3D FIELD_PREP(RTL8365MB_VLAN_MC_D3_EVID_MASK, vlanmc->evid); + + ret =3D regmap_bulk_write(priv->map, RTL8365MB_VLAN_MC_REG(index), &data, + RTL8365MB_VLAN_MC_ENTRY_SIZE); + + return ret; +} + +static int rtl8365mb_vlan_mc_erase(struct realtek_priv *priv, u32 index) +{ + u16 data[RTL8365MB_VLAN_MC_ENTRY_SIZE] =3D { 0 }; + int ret; + + ret =3D regmap_bulk_write(priv->map, RTL8365MB_VLAN_MC_REG(index), &data, + RTL8365MB_VLAN_MC_ENTRY_SIZE); + + return ret; +} + +/* + * rtl8365mb_vlan_mc_find() - find VLANMC index by VID or the first free i= ndex + * + * @priv: realtek_priv pointer + * @vid: VLAN ID + * @index: found index + * @first_free: found free index + * + * If a VLAN MC entry using @vid was found, @index will return the matched= index + * and @first_free is undefined. If not found, @index will return 0 and + * @first_free will return the first found free index in VLAN MC or 0 if t= he + * table is full. + * + * Although 0 is a valid VLAN MC index, it is reserved for ports without P= VID, + * including standalone, non-member ports. It uses VID =3D=3D 0. + * + * Both @index and @first_free will be in the * 1..@RTL8365MB_VLAN_MCMAX r= ange. + * + * Return: Returns 0 on success, a negative error on failure. + */ +static int rtl8365mb_vlan_mc_find(struct realtek_priv *priv, u16 vid, + u8 *index, u8 *first_free) +{ + u32 vlan_entry_d3; + u8 vlanmc_idx; + u16 evid; + int ret; + + *index =3D 0; + *first_free =3D 0; + + /* look for existing entry or an empty one */ + /* By design, VlanMC[0] is reserved as a neutral PVID value for + * standalone ports. It always has EVID =3D=3D 0. That way, we assume that + * all entries after index 0 with VID =3D=3D 0 are empty. + **/ + for (vlanmc_idx =3D 1; vlanmc_idx <=3D RTL8365MB_VLAN_MCMAX; vlanmc_idx++= ) { + /* just read the 4th word, where the evid is */ + ret =3D regmap_read(priv->map, + RTL8365MB_VLAN_MC_REG(vlanmc_idx) + 3, + &vlan_entry_d3); + if (ret) + return ret; + + evid =3D FIELD_GET(RTL8365MB_VLAN_MC_D3_EVID_MASK, vlan_entry_d3); + + if (evid =3D=3D vid) { + *index =3D vlanmc_idx; + return 0; + } + + if (evid =3D=3D 0x0 && *first_free < 1) + *first_free =3D vlanmc_idx; + } + return 0; +} + +static int rtl8365mb_vlan_port_get_pvid_idx(struct realtek_priv *priv, + int port, u8 *vlanmc_idx) +{ + u32 data; + int ret; + + ret =3D regmap_read(priv->map, RTL8365MB_VLAN_PVID_CTRL_REG(port), &data); + if (ret) + return ret; + + *vlanmc_idx =3D (data & RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_MASK(port)) + >> RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(port); + + return 0; +} + +/* + * rtl8365mb_vlan_mc_port_set() - include or exclude a port from VlanMC + * @ds: dsa switch + * @port: the port number + * @vid: the vlan VID to include/exclude @port + * @pvid: inform if vid is used as pvid in @port + * @extack: optional extack to return errors + * @include: whether to include or exclude @port + * + * This function is used to include/exclude ports to the VlanMC table. + * + * VlanMC stands for VLAN membership config and it is used exclusively for + * PVID. If @vlan members are not using PVID, this function will either + * remove or not create a new VlanMC entry. + * + * VlanMC members are used as a reference port map, cleaning the entry once + * no port is using it. + * + * Port PVID and accepted frame type are updated as well. + * + * Context: Can sleep. Must be called with &priv->vlan_lock held. + * Takes and releases &priv->map_lock. + * Return: Returns 0 on success, a negative error on failure. + */ +static +int rtl8365mb_vlan_mc_port_set(struct dsa_switch *ds, int port, + u16 vid, bool pvid, + struct netlink_ext_ack *extack, + bool include) +{ + struct realtek_priv *priv =3D ds->priv; + struct rtl8365mb_vlanmc vlanmc =3D {0}; + u8 first_unused =3D 0; + u8 vlanmc_idx =3D 0; + int ret; + + dev_dbg(priv->dev, "%s VLAN %d MC on port %d\n", + include ? "add" : "del", + vid, port); + + if (vid > RTL8365MB_MAX_MC_VID) { + RTL_VLAN_ERR("VLAN ID greater than " + __stringify(RTL8365MB_MAX_MC_VID)); + return -EINVAL; + } + + /* look for existing entry or an empty slot */ + ret =3D rtl8365mb_vlan_mc_find(priv, vid, &vlanmc_idx, + &first_unused); + if (ret) { + RTL_VLAN_ERR("Failed to find a VLAN MC table index"); + return ret; + } + + if (vlanmc_idx) { + ret =3D rtl8365mb_vlan_mc_read(priv, vlanmc_idx, &vlanmc); + if (ret) { + RTL_VLAN_ERR("Failed to read VLAN MC table"); + return ret; + } + } else if (include) { + /* for now, vlan_mc is only required for PVID. Defer allocation + * until at least one port uses PVID. + */ + if (!pvid) { + dev_dbg(priv->dev, + "Not creating VlanMC for vlan %d until a port uses PVID (%d does not)\= n", + vid, port); + return 0; + } + + if (!first_unused) { + RTL_VLAN_ERR("All VLAN MC entries (0.." + __stringify(RTL8365MB_VLAN_MCMAX) + ") are in use."); + return -E2BIG; + } + + vlanmc_idx =3D first_unused; + vlanmc.evid =3D vid; + + } else /* excluding and VLANMC not found */ { + return 0; + } + + dev_dbg(priv->dev, + "VLAN %d (idx: %d) PVID curr members: %08x\n", + vid, vlanmc_idx, vlanmc.member); + + /* here we either have an existing VLANMC (with PVID members) or the + * added port is using this VLAN as PVID + */ + if (include) + vlanmc.member |=3D BIT(port); + else + vlanmc.member &=3D ~BIT(port); + + /* just like we don't need to create a VLAN_MC when there is no port + * using it as PVID, we can erase it when there is no more port using + * it as PVID. + */ + if (!vlanmc.member) { + dev_dbg(priv->dev, + "Clearing VlanMC index %d previously used by VID %d\n", + vlanmc_idx, vid); + ret =3D rtl8365mb_vlan_mc_erase(priv, vlanmc_idx); + } else { + dev_dbg(priv->dev, + "Saving VlanMC index %d with VID %d\n", + vlanmc_idx, vid); + ret =3D rtl8365mb_vlan_mc_write(priv, vlanmc_idx, &vlanmc); + } + if (ret) { + RTL_VLAN_ERR("Failed to write vlan MC entry"); + return ret; + } + + return 0; +} + +static int rtl8365mb_vlan_port_set_pvid(struct realtek_priv *priv, + int port, u16 vlanmc_idx) +{ + int ret; + u32 val; + + dev_dbg(priv->dev, "set PVID IDX %d on port %d\n", vlanmc_idx, port); + + val =3D vlanmc_idx << RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(port); + ret =3D regmap_update_bits(priv->map, + RTL8365MB_VLAN_PVID_CTRL_REG(port), + RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_MASK(port), + val); + if (ret) + return ret; + + return 0; +} + +static int rtl8365mb_vlan_mc_get_pvid(struct realtek_priv *priv, + int port, u8 *vlanmc_idx, + struct rtl8365mb_vlanmc *vlanmc) +{ + int ret; + + ret =3D rtl8365mb_vlan_port_get_pvid_idx(priv, port, vlanmc_idx); + if (ret) + return ret; + + memset(vlanmc, 0, sizeof(*vlanmc)); + + if (!*vlanmc_idx) + return 0; + + ret =3D rtl8365mb_vlan_mc_read(priv, *vlanmc_idx, vlanmc); + if (ret) + return ret; + + return 0; +} + +/* + * rtl8365mb_vlan_port_get_pvid - Retrieve the port PVID + * @priv: realtek switch private structure + * @port: port index + * @pvid: pointer to store the retrieved VLAN ID + * + * Returns the port PVID if defined or 0 if not. + * + * Context: Can sleep. Takes and releases &priv->map_lock. + * Return: 0 on success or a negative error code on failure. + */ +int rtl8365mb_vlan_port_get_pvid(struct realtek_priv *priv, int port, u16 = *pvid) +{ + struct rtl8365mb_vlanmc vlanmc; + u8 vlanmc_idx; + int ret; + + ret =3D rtl8365mb_vlan_mc_get_pvid(priv, port, &vlanmc_idx, &vlanmc); + if (ret) + return ret; + + *pvid =3D vlanmc.evid; + return 0; +} + +/* + * rtl8365mb_vlan_port_get_framefilter() - Get the ingress frame filtering= mode + * for a port + * @priv: realtek switch private structure + * @port: port index + * @frame_type: pointer to store the retrieved ingress frame filter type + * + * Context: Can sleep. Takes and releases &priv->map_lock. + * Return: 0 on success, or a negative error code on failure. + */ +int +rtl8365mb_vlan_port_get_framefilter(struct realtek_priv *priv, + int port, + enum rtl8365mb_frame_ingress *frame_type) +{ + u32 val; + int ret; + + /* Even if ACCEPT_FRAME_TYPE_ANY, the switch will still check if the + * port is a member of vlan PVID + */ + + ret =3D regmap_read(priv->map, RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_REG(port), + &val); + if (ret) + return ret; + + *frame_type =3D field_get(RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_MASK(port), + val); + + return 0; +} + +/* + * rtl8365mb_vlan_port_set_framefilter() - Set the ingress frame filtering= mode + * for a port + * @priv: realtek switch private structure + * @port: port index + * @frame_type: the ingress frame filter type to configure + * + * Context: Can sleep. Takes and releases &priv->map_lock. + * Return: 0 on success, or a negative error code on failure. + */ +int +rtl8365mb_vlan_port_set_framefilter(struct realtek_priv *priv, + int port, + enum rtl8365mb_frame_ingress frame_type) +{ + u32 val; + + /* Even if ACCEPT_FRAME_TYPE_ANY, the switch will still check if the + * port is a member of vlan PVID + */ + val =3D frame_type << RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_OFFSET(port); + + return regmap_update_bits(priv->map, + RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_REG(port), + RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_MASK(port), + val); +} + +/* + * rtl8365mb_vlan_pvid_port_set() - Configure a port's PVID and associated + * VLANMC entry + * @ds: dsa switch instance + * @port: port index + * @vid: target VID + * @extack: netlink extended ACK for error reporting + * + * Allocates or reuses a hardware VLANMC entry to map the given port to it= s new + * PVID. Gracefully unwinds and restores previous configuration if a hardw= are + * write operation fails during execution. + * + * Context: Can sleep. Must be called with &priv->vlan_lock held. + * Takes and releases &priv->map_lock. + * Return: 0 on success, or a negative error code on failure. + */ +int rtl8365mb_vlan_pvid_port_set(struct dsa_switch *ds, int port, u16 vid, + struct netlink_ext_ack *extack) +{ + enum rtl8365mb_frame_ingress accepted_frame, prev_accepted_frame; + struct realtek_priv *priv =3D ds->priv; + struct rtl8365mb_vlanmc prev_vlanmc =3D {0}; + u8 _unused_first_free_idx; + u8 prev_vlanmc_idx; + u8 vlanmc_idx; + int ret; + + lockdep_assert_held(&priv->vlan_lock); + + /* Read the old PVID exclusively to undo in case of error */ + ret =3D rtl8365mb_vlan_mc_get_pvid(priv, port, &prev_vlanmc_idx, + &prev_vlanmc); + if (ret) { + RTL_VLAN_ERR("Failed to read current VLAN MC"); + return ret; + } + + ret =3D rtl8365mb_vlan_port_get_framefilter(priv, port, + &prev_accepted_frame); + if (ret) { + RTL_VLAN_ERR("Failed to get current framefilter"); + return ret; + } + + /* Find or allocate a new vlan MC and add port to members, + * although members are not checked by the HW in vlan MC. + */ + ret =3D rtl8365mb_vlan_mc_port_set(ds, port, vid, true, + extack, true); + if (ret) + return ret; + + /* look for existing entry */ + ret =3D rtl8365mb_vlan_mc_find(priv, vid, &vlanmc_idx, + &_unused_first_free_idx); + if (ret) { + RTL_VLAN_ERR("Failed to find a VLAN MC table index"); + goto undo_vlan_mc_port_set; + } + + if (!vlanmc_idx) { + RTL_VLAN_ERR("VLAN should already exist in VLAN MC"); + ret =3D -ENOENT; + goto undo_vlan_mc_port_set; + } + + ret =3D rtl8365mb_vlan_port_set_pvid(priv, port, vlanmc_idx); + if (ret) { + RTL_VLAN_ERR("Failed to set port PVID"); + goto undo_vlan_mc_port_set; + } + + /* Changing accept frame is what enables PVID (if not enabled before) */ + accepted_frame =3D RTL8365MB_FRAME_TYPE_ANY_FRAME; + ret =3D rtl8365mb_vlan_port_set_framefilter(priv, port, accepted_frame); + if (ret) { + RTL_VLAN_ERR("Failed to set port frame filter"); + goto undo_vlan_port_set_pvid; + } + + /* A VLAN can be added with PVID without removing from the old + * PVID VLAN. Clear PVID from the old VLAN MC (if needed). + */ + if (prev_vlanmc_idx && (prev_vlanmc.evid !=3D vid)) { + ret =3D rtl8365mb_vlan_mc_port_set(ds, port, prev_vlanmc.evid, + false, NULL, false); + if (ret) { + RTL_VLAN_ERR("Failed to clear old VLAN MC"); + goto undo_set_framefilter; + } + } + + return 0; + +undo_set_framefilter: + (void)rtl8365mb_vlan_port_set_framefilter(priv, port, + prev_accepted_frame); + +undo_vlan_port_set_pvid: + (void)rtl8365mb_vlan_port_set_pvid(priv, port, prev_vlanmc_idx); + +undo_vlan_mc_port_set: + (void)rtl8365mb_vlan_mc_port_set(ds, port, vid, false, NULL, false); + + return ret; +} + +/* + * rtl8365mb_vlan_pvid_port_clear() - Remove a port's PVID configuration + * @ds: dsa switch instance + * @port: port index + * @vid: VLAN VID for PVID + * + * Resets the target port's hardware PVID allocation to 0. Cleans up and f= rees + * the associated VLANMC entry if no other ports are referencing it. + * + * Context: Can sleep. Must be called with &priv->vlan_lock held. + * Takes and releases &priv->map_lock. + * Return: 0 on success, or a negative error code on failure. + */ +int rtl8365mb_vlan_pvid_port_clear(struct dsa_switch *ds, int port, u16 vi= d) +{ + enum rtl8365mb_frame_ingress accepted_frame, prev_accepted_frame; + struct netlink_ext_ack *extack =3D NULL; + struct realtek_priv *priv =3D ds->priv; + struct rtl8365mb_vlanmc vlanmc =3D {0}; + u8 vlanmc_idx; + int ret; + + lockdep_assert_held(&priv->vlan_lock); + + ret =3D rtl8365mb_vlan_mc_get_pvid(priv, port, &vlanmc_idx, + &vlanmc); + if (ret) { + RTL_VLAN_ERR("Failed to read current VLAN MC"); + return ret; + } + + /* Port is not using PVID. Nothing to remove. */ + if (!vlanmc_idx) + return 0; + + /* We are leaving a non PVID vlan, Nothing to remove. */ + if (vlanmc.evid !=3D vid) + return 0; + + ret =3D rtl8365mb_vlan_port_get_framefilter(priv, port, + &prev_accepted_frame); + if (ret) { + RTL_VLAN_ERR("Failed to get current framefilter"); + return ret; + } + + /* Changing accept frame is what really removes PVID. But only do + * that if we are filtering vlan + */ + if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) { + accepted_frame =3D RTL8365MB_FRAME_TYPE_TAGGED_ONLY; + + ret =3D rtl8365mb_vlan_port_set_framefilter(priv, port, + accepted_frame); + if (ret) { + RTL_VLAN_ERR("Failed to set port frame filter"); + return ret; + } + } else { + /* skip undo_set_framefilter */ + accepted_frame =3D prev_accepted_frame; + } + + ret =3D rtl8365mb_vlan_port_set_pvid(priv, port, 0); + if (ret) { + RTL_VLAN_ERR("Failed to set port PVID to 0"); + goto undo_set_framefilter; + } + + /* Clears the VLAN MC membership and maybe VLAN MC entry if empty */ + ret =3D rtl8365mb_vlan_mc_port_set(ds, port, vlanmc.evid, + false, NULL, false); + if (ret) + goto undo_port_set_pvid; + + return 0; + +undo_port_set_pvid: + (void)rtl8365mb_vlan_port_set_pvid(priv, port, vlanmc_idx); + +undo_set_framefilter: + if (prev_accepted_frame !=3D accepted_frame) + (void)rtl8365mb_vlan_port_set_framefilter(priv, port, + prev_accepted_frame); + + return ret; +} diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.h b/drivers/net/dsa/rea= ltek/rtl8365mb_vlan.h new file mode 100644 index 000000000000..27a526b61873 --- /dev/null +++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* VLAN configuration interface for the rtl8365mb switch family + * + * Copyright (C) 2022 Alvin =C5=A0ipraga + * + */ + +#ifndef _REALTEK_RTL8365MB_VLAN_H +#define _REALTEK_RTL8365MB_VLAN_H + +#include + +#include "realtek.h" + +enum rtl8365mb_frame_ingress { + RTL8365MB_FRAME_TYPE_ANY_FRAME =3D 0, + RTL8365MB_FRAME_TYPE_TAGGED_ONLY, + RTL8365MB_FRAME_TYPE_UNTAGGED_ONLY, +}; + +int rtl8365mb_vlan_port_get_pvid(struct realtek_priv *priv, int port, + u16 *pvid); +int +rtl8365mb_vlan_port_get_framefilter(struct realtek_priv *priv, + int port, + enum rtl8365mb_frame_ingress *frame_type); +int +rtl8365mb_vlan_port_set_framefilter(struct realtek_priv *priv, + int port, + enum rtl8365mb_frame_ingress frame_type); +int rtl8365mb_vlan_4k_port_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack); +int rtl8365mb_vlan_4k_port_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan); +int rtl8365mb_vlan_pvid_port_set(struct dsa_switch *ds, int port, u16 vid, + struct netlink_ext_ack *extack); +int rtl8365mb_vlan_pvid_port_clear(struct dsa_switch *ds, int port, u16 vi= d); +#endif /* _REALTEK_RTL8365MB_VLAN_H */ diff --git a/drivers/net/dsa/realtek/rtl83xx.c b/drivers/net/dsa/realtek/rt= l83xx.c index 2b9bd4462714..93bc47dfe7f7 100644 --- a/drivers/net/dsa/realtek/rtl83xx.c +++ b/drivers/net/dsa/realtek/rtl83xx.c @@ -155,6 +155,7 @@ rtl83xx_probe(struct device *dev, return ERR_PTR(-ENOMEM); =20 mutex_init(&priv->map_lock); + mutex_init(&priv->vlan_lock); =20 rc.lock_arg =3D priv; priv->map =3D devm_regmap_init(dev, NULL, priv, &rc); --=20 2.54.0 From nobody Sun Jun 7 02:07:40 2026 Received: from mail-qt1-f181.google.com (mail-qt1-f181.google.com [209.85.160.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACB5D369D71 for ; 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Thu, 28 May 2026 21:30:59 -0700 (PDT) Received: from tresc054937.tre-sc.gov.br ([187.65.210.13]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5172ebc7d23sm9260991cf.29.2026.05.28.21.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 21:30:58 -0700 (PDT) From: Luiz Angelo Daros de Luca Date: Fri, 29 May 2026 01:29:51 -0300 Subject: [net-next PATCH v9 6/8] net: dsa: realtek: rtl8365mb: add port_bridge_{join,leave} Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-realtek_forward-v9-6-e7c61872d923@gmail.com> References: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> In-Reply-To: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Yury Norov , Rasmus Villemoes , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Mieczyslaw Nalewaj , Luiz Angelo Daros de Luca X-Mailer: b4 0.15.2 From: Alvin =C5=A0ipraga Implement hardware offloading of bridge functionality. This is achieved by using the per-port isolation registers, which contain a forwarding port mask. The switch will refuse to forward packets ingressed on a given port to a port which is not in its forwarding mask. For each bridge that is offloaded, use the DSA-provided bridge number for the Extended Filtering ID (EFID). When using Independent VLAN Learning (IVL), the forwarding database is keyed with the tuple {VID, MAC, EFID}. There are 8 EFIDs available (0~7), but we reserve the default EFID 0 for standalone ports where learning is disabled. This fits nicely because DSA indexes the bridge number starting from 1. Because of the limited number of EFIDs, we have to set the max_num_bridges property of our switch to 7: we can't offload more than that or we will fail to offer IVL as at least two bridges would end up having to share an EFID. Signed-off-by: Alvin =C5=A0ipraga Reviewed-by: Linus Walleij Reviewed-by: Mieczyslaw Nalewaj Co-developed-by: Luiz Angelo Daros de Luca Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/realtek.h | 7 ++ drivers/net/dsa/realtek/rtl8365mb_main.c | 58 +++++++++++- drivers/net/dsa/realtek/rtl83xx.c | 149 +++++++++++++++++++++++++++= ++++ drivers/net/dsa/realtek/rtl83xx.h | 7 ++ 4 files changed, 220 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/re= altek.h index b9c4cbdd72fb..c271a15a9ae2 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -112,6 +112,13 @@ struct realtek_ops { int (*enable_vlan)(struct realtek_priv *priv, bool enable); int (*enable_vlan4k)(struct realtek_priv *priv, bool enable); int (*enable_port)(struct realtek_priv *priv, int port, bool enable); + int (*port_add_isolation)(struct realtek_priv *priv, int port, + u32 mask); + int (*port_remove_isolation)(struct realtek_priv *priv, int port, + u32 mask); + int (*port_set_efid)(struct realtek_priv *priv, int port, u32 efid); + int (*port_set_learning)(struct realtek_priv *priv, int port, + bool enable); int (*phy_read)(struct realtek_priv *priv, int phy, int regnum); int (*phy_write)(struct realtek_priv *priv, int phy, int regnum, u16 val); diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/rea= ltek/rtl8365mb_main.c index 59d1e4f5a0f8..c70e162038cd 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -285,6 +285,15 @@ (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) #define RTL8365MB_PORT_ISOLATION_MASK 0x07FF =20 +/* Extended filter ID registers - used to key forwarding database with IVL= */ +#define RTL8365MB_EFID_MASK GENMASK(2, 0) +#define RTL8365MB_PORT_EFID_REG_BASE 0x0A32 +#define RTL8365MB_PORT_EFID_REG(_p) \ + (RTL8365MB_PORT_EFID_REG_BASE + ((_p) >> 2)) +#define RTL8365MB_PORT_EFID_OFFSET(_p) (((_p) & 0x3) << 2) +#define RTL8365MB_PORT_EFID_MASK(_p) \ + (RTL8365MB_EFID_MASK << RTL8365MB_PORT_EFID_OFFSET(_p)) + /* MSTP port state registers - indexed by tree instance */ #define RTL8365MB_MSTI_CTRL_BASE 0x0A00 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ @@ -1533,10 +1542,44 @@ static int rtl8365mb_port_set_learning(struct realt= ek_priv *priv, int port, enable ? RTL8365MB_LEARN_LIMIT_MAX : 0); } =20 +static int rtl8365mb_port_set_efid(struct realtek_priv *priv, int port, + u32 efid) +{ + return regmap_update_bits(priv->map, RTL8365MB_PORT_EFID_REG(port), + RTL8365MB_PORT_EFID_MASK(port), + efid << RTL8365MB_PORT_EFID_OFFSET(port)); +} + +/* Port isolation manipulation functions. + * + * The port isolation register controls the forwarding mask of a given + * port. The switch will not forward packets ingressed on a given port + * to ports which are not enabled in its forwarding mask. + * + * The port forwarding mask has the highest priority in forwarding + * decisions. The only exception to this rule is when the switch + * receives a packet on its CPU port with ALLOW=3D0. In that case the TX + * field of the CPU tag will override the forwarding port mask. + */ static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int por= t, u32 mask) { - return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); + return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), + mask); +} + +static int rtl8365mb_port_add_isolation(struct realtek_priv *priv, int por= t, + u32 mask) +{ + return regmap_update_bits(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), + mask, mask); +} + +static int rtl8365mb_port_remove_isolation(struct realtek_priv *priv, int = port, + u32 mask) +{ + return regmap_update_bits(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), + mask, 0); } =20 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, @@ -2338,6 +2381,11 @@ static int rtl8365mb_setup(struct dsa_switch *ds) if (ret) goto out_teardown_irq; =20 + /* Set the default EFID 0 for standalone mode */ + ret =3D rtl8365mb_port_set_efid(priv, dp->index, 0); + if (ret) + goto out_teardown_irq; + /* Disable learning */ ret =3D rtl8365mb_port_set_learning(priv, dp->index, false); if (ret) @@ -2406,6 +2454,8 @@ static int rtl8365mb_setup(struct dsa_switch *ds) if (ret) goto out_teardown_irq; =20 + /* The EFID is 3 bits, but EFID 0 is reserved for standalone ports */ + ds->max_num_bridges =3D FIELD_MAX(RTL8365MB_EFID_MASK); ds->configure_vlan_while_not_filtering =3D true; =20 /* Set up VLAN */ @@ -2522,6 +2572,8 @@ static const struct dsa_switch_ops rtl8365mb_switch_o= ps =3D { .setup =3D rtl8365mb_setup, .teardown =3D rtl8365mb_teardown, .phylink_get_caps =3D rtl8365mb_phylink_get_caps, + .port_bridge_join =3D rtl83xx_port_bridge_join, + .port_bridge_leave =3D rtl83xx_port_bridge_leave, .port_stp_state_set =3D rtl8365mb_port_stp_state_set, .port_vlan_add =3D rtl8365mb_port_vlan_add, .port_vlan_del =3D rtl8365mb_port_vlan_del, @@ -2541,6 +2593,10 @@ static const struct dsa_switch_ops rtl8365mb_switch_= ops =3D { =20 static const struct realtek_ops rtl8365mb_ops =3D { .detect =3D rtl8365mb_detect, + .port_add_isolation =3D rtl8365mb_port_add_isolation, + .port_remove_isolation =3D rtl8365mb_port_remove_isolation, + .port_set_efid =3D rtl8365mb_port_set_efid, + .port_set_learning =3D rtl8365mb_port_set_learning, .phy_read =3D rtl8365mb_phy_read, .phy_write =3D rtl8365mb_phy_write, }; diff --git a/drivers/net/dsa/realtek/rtl83xx.c b/drivers/net/dsa/realtek/rt= l83xx.c index 93bc47dfe7f7..bd38091fdc76 100644 --- a/drivers/net/dsa/realtek/rtl83xx.c +++ b/drivers/net/dsa/realtek/rtl83xx.c @@ -326,6 +326,155 @@ void rtl83xx_reset_deassert(struct realtek_priv *priv) gpiod_set_value(priv->reset, false); } =20 +/** + * rtl83xx_port_bridge_join() - join a port to a bridge + * @ds: DSA switch instance + * @port: port index + * @bridge: bridge being joined + * @tx_forward_offload: if the switch can offload TX forwarding + * @extack: netlink extended ack for reporting errors + * + * This function handles joining a port to a bridge. It updates the port + * isolation masks and EFID. + * + * Context: Can sleep. + * Return: 0 on success, negative value for failure. + */ +int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port, + struct dsa_bridge bridge, + bool *tx_forward_offload, + struct netlink_ext_ack *extack) +{ + struct realtek_priv *priv =3D ds->priv; + struct dsa_port *dp; + u32 mask =3D 0; + int ret; + + if (!priv->ops->port_add_isolation) + return -EOPNOTSUPP; + + if (!priv->ops->port_set_learning) + return -EOPNOTSUPP; + + dev_dbg(priv->dev, "bridge %d join port %d\n", bridge.num, port); + + /* Add this port to the isolation group of every other port + * offloading this bridge. + */ + dsa_switch_for_each_user_port(dp, ds) { + /* Handle this port after */ + if (dp->index =3D=3D port) + continue; + + /* Skip ports that are not in this bridge */ + if (!dsa_port_offloads_bridge(dp, &bridge)) + continue; + + ret =3D priv->ops->port_add_isolation(priv, dp->index, BIT(port)); + if (ret) + goto undo_isolation; + + mask |=3D BIT(dp->index); + } + + /* If we support cascade switches, it should also include the + * downstream DSA ports to the isolation group. + */ + + /* Add those ports to the isolation group of this port */ + ret =3D priv->ops->port_add_isolation(priv, port, mask); + if (ret) + goto undo_isolation; + + ret =3D priv->ops->port_set_learning(priv, port, true); + if (ret) + goto undo_self_isolation; + + /* Use the bridge number as the EFID for this port */ + if (priv->ops->port_set_efid) { + ret =3D priv->ops->port_set_efid(priv, port, bridge.num); + if (ret) + goto undo_learning; + } + + return 0; + +undo_learning: + priv->ops->port_set_learning(priv, port, false); + +undo_self_isolation: + priv->ops->port_remove_isolation(priv, port, mask); + +undo_isolation: + dsa_switch_for_each_port(dp, ds) { + if (mask & BIT(dp->index)) + priv->ops->port_remove_isolation(priv, dp->index, + BIT(port)); + } + + return ret; +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_bridge_join, "REALTEK_DSA"); + +/** + * rtl83xx_port_bridge_leave() - leave a bridge + * @ds: DSA switch instance + * @port: port index + * @bridge: bridge being left + * + * This function handles removing a port from a bridge. It updates the port + * isolation masks and EFID. + * + * Context: Can sleep. + * Return: nothing + */ +void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port, + struct dsa_bridge bridge) +{ + struct realtek_priv *priv =3D ds->priv; + struct dsa_port *dp; + u32 mask =3D 0; + + if (!priv->ops->port_remove_isolation) + return; + + if (!priv->ops->port_set_learning) + return; + + dev_dbg(priv->dev, "bridge %d leave port %d\n", bridge.num, port); + + /* Remove this port from the isolation group of every other + * port offloading this bridge. + */ + dsa_switch_for_each_user_port(dp, ds) { + /* Handle this port after */ + if (dp->index =3D=3D port) + continue; + + /* Skip ports that are not in this bridge */ + if (!dsa_port_offloads_bridge(dp, &bridge)) + continue; + + priv->ops->port_remove_isolation(priv, dp->index, BIT(port)); + + mask |=3D BIT(dp->index); + } + + /* If we support cascade switches, it should also exclude the + * downstream DSA ports from the isolation group. + */ + + priv->ops->port_set_learning(priv, port, false); + + /* Remove those ports from the isolation group of this port */ + priv->ops->port_remove_isolation(priv, port, mask); + + /* Revert to the default EFID 0 for standalone mode */ + if (priv->ops->port_set_efid) + priv->ops->port_set_efid(priv, port, 0); +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_bridge_leave, "REALTEK_DSA"); + MODULE_AUTHOR("Luiz Angelo Daros de Luca "); MODULE_AUTHOR("Linus Walleij "); MODULE_DESCRIPTION("Realtek DSA switches common module"); diff --git a/drivers/net/dsa/realtek/rtl83xx.h b/drivers/net/dsa/realtek/rt= l83xx.h index c8a0ff8fd75e..2481a1aaa226 100644 --- a/drivers/net/dsa/realtek/rtl83xx.h +++ b/drivers/net/dsa/realtek/rtl83xx.h @@ -21,4 +21,11 @@ void rtl83xx_remove(struct realtek_priv *priv); void rtl83xx_reset_assert(struct realtek_priv *priv); void rtl83xx_reset_deassert(struct realtek_priv *priv); =20 +int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port, + struct dsa_bridge bridge, + bool *tx_forward_offload, + struct netlink_ext_ack *extack); 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Thu, 28 May 2026 21:31:05 -0700 (PDT) From: Luiz Angelo Daros de Luca Date: Fri, 29 May 2026 01:29:52 -0300 Subject: [net-next PATCH v9 7/8] net: dsa: realtek: rtl8365mb: add FDB support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-realtek_forward-v9-7-e7c61872d923@gmail.com> References: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> In-Reply-To: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Yury Norov , Rasmus Villemoes , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Mieczyslaw Nalewaj , Luiz Angelo Daros de Luca X-Mailer: b4 0.15.2 From: Alvin =C5=A0ipraga Implement support for FDB and MDB management for the RTL8365MB series switches. The hardware supports IVL by keying the unicast forwarding database with the {MAC, VID, EFID} tuple. The Extended Filtering ID (EFID) is 3 bits wide, providing 8 unique filtering domains. This driver reserves EFID 0 for standalone ports, effectively limiting the hardware offload to a maximum of 7 bridges. The multicast database uses a {MAC, VID} key, with ports from different bridges sharing the same multicast group. Introduce a mutex lock (l2_lock) to protect concurrent L2 table updates. Add support for forwarding database operations, including unicast and multicast entry handling as well as fast aging support. Set DSA switch flags assisted_learning_on_cpu_port and fdb_isolation. Signed-off-by: Alvin =C5=A0ipraga Reviewed-by: Linus Walleij Reviewed-by: Mieczyslaw Nalewaj Co-developed-by: Luiz Angelo Daros de Luca Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/Makefile | 1 + drivers/net/dsa/realtek/realtek.h | 29 ++ drivers/net/dsa/realtek/rtl8365mb_l2.c | 566 +++++++++++++++++++++++++++= ++++ drivers/net/dsa/realtek/rtl8365mb_l2.h | 32 ++ drivers/net/dsa/realtek/rtl8365mb_main.c | 25 +- drivers/net/dsa/realtek/rtl83xx.c | 317 +++++++++++++++++ drivers/net/dsa/realtek/rtl83xx.h | 16 + 7 files changed, 985 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Mak= efile index b7fc4e852fd8..6c329e046d0b 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) +=3D rtl8365mb.o rtl8365mb-objs :=3D rtl8365mb_main.o \ rtl8365mb_table.o \ rtl8365mb_vlan.o \ + rtl8365mb_l2.o \ diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/re= altek.h index c271a15a9ae2..426c9d345e6e 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -45,6 +45,12 @@ struct rtl8366_vlan_4k { u8 fid; }; =20 +struct realtek_fdb_entry { + u8 mac_addr[ETH_ALEN]; + u16 vid; + bool is_static; +}; + struct realtek_priv { struct device *dev; struct reset_control *reset_ctl; @@ -59,6 +65,15 @@ struct realtek_priv { * deleting port VLAN memberships and PVID configurations. */ struct mutex vlan_lock; + /* l2_lock is used to prevent concurrent modifications of L2 table + * entries while another function is reading it. l2_(add,del)_mc + * is an example that first read current table entry and then + * create/update it. l2_(add|del)_uc uses a single table op and, + * internally, it might not need this lock. However, altering FDB + * may still collide, as well as l2_flush, with fdb_dump iterating + * over FDB. + */ + struct mutex l2_lock; struct mii_bus *user_mii_bus; struct mii_bus *bus; int mdio_addr; @@ -119,6 +134,19 @@ struct realtek_ops { int (*port_set_efid)(struct realtek_priv *priv, int port, u32 efid); int (*port_set_learning)(struct realtek_priv *priv, int port, bool enable); + int (*l2_add_uc)(struct realtek_priv *priv, int port, + const unsigned char addr[ETH_ALEN], + u16 efid, u16 vid); + int (*l2_del_uc)(struct realtek_priv *priv, int port, + const unsigned char addr[ETH_ALEN], + u16 efid, u16 vid); + int (*l2_get_next_uc)(struct realtek_priv *priv, u16 *addr, + int port, struct realtek_fdb_entry *entry); + int (*l2_add_mc)(struct realtek_priv *priv, int port, + const unsigned char addr[ETH_ALEN], u16 vid); + int (*l2_del_mc)(struct realtek_priv *priv, int port, + const unsigned char addr[ETH_ALEN], u16 vid); + int (*l2_flush)(struct realtek_priv *priv, int port, u16 vid); int (*phy_read)(struct realtek_priv *priv, int phy, int regnum); int (*phy_write)(struct realtek_priv *priv, int phy, int regnum, u16 val); @@ -131,6 +159,7 @@ struct realtek_variant { unsigned int clk_delay; u8 cmd_read; u8 cmd_write; + u16 l2_table_size; size_t chip_data_sz; }; =20 diff --git a/drivers/net/dsa/realtek/rtl8365mb_l2.c b/drivers/net/dsa/realt= ek/rtl8365mb_l2.c new file mode 100644 index 000000000000..c88067eaae3e --- /dev/null +++ b/drivers/net/dsa/realtek/rtl8365mb_l2.c @@ -0,0 +1,566 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Forwarding and multicast database interface for the rtl8365mb switch fa= mily + * + * Copyright (C) 2022 Alvin =C5=A0ipraga + */ + +#include + +#include "rtl8365mb_l2.h" +#include "rtl8365mb_table.h" +#include + +#define RTL8365MB_L2_ENTRY_SIZE 6 + +#define RTL8365MB_L2_UC_D0_MAC5_MSK GENMASK(7, 0) +#define RTL8365MB_L2_UC_D0_MAC4_MSK GENMASK(15, 8) +#define RTL8365MB_L2_UC_D1_MAC3_MSK GENMASK(7, 0) +#define RTL8365MB_L2_UC_D1_MAC2_MSK GENMASK(15, 8) +#define RTL8365MB_L2_UC_D2_MAC1_MSK GENMASK(7, 0) +#define RTL8365MB_L2_UC_D2_MAC0_MSK GENMASK(15, 8) +#define RTL8365MB_L2_UC_D3_VID_MSK GENMASK(11, 0) +#define RTL8365MB_L2_UC_D3_IVL_MSK GENMASK(13, 13) +#define RTL8365MB_L2_UC_D3_PORT_EXT_MSK GENMASK(15, 15) +#define RTL8365MB_L2_UC_PORT_HI_MSK GENMASK(3, 3) +#define RTL8365MB_L2_UC_D4_EFID_MSK GENMASK(2, 0) +#define RTL8365MB_L2_UC_D4_FID_MSK GENMASK(6, 3) +#define RTL8365MB_L2_UC_D4_SA_PRI_MSK GENMASK(7, 7) +#define RTL8365MB_L2_UC_D4_PORT_MSK GENMASK(10, 8) +#define RTL8365MB_L2_UC_PORT_LO_MSK GENMASK(2, 0) +#define RTL8365MB_L2_UC_D4_AGE_MSK GENMASK(13, 11) +#define RTL8365MB_L2_UC_D4_AUTH_MSK GENMASK(14, 14) +#define RTL8365MB_L2_UC_D4_SA_BLOCK_MSK GENMASK(15, 15) + +#define RTL8365MB_L2_UC_D5_DA_BLOCK_MSK GENMASK(0, 0) +#define RTL8365MB_L2_UC_D5_PRIORITY_MSK GENMASK(3, 1) +#define RTL8365MB_L2_UC_D5_FWD_PRI_MSK GENMASK(4, 4) +#define RTL8365MB_L2_UC_D5_STATIC_MSK GENMASK(5, 5) + +#define RTL8365MB_L2_MC_D0_MAC5_MSK GENMASK(7, 0) +#define RTL8365MB_L2_MC_D0_MAC4_MSK GENMASK(15, 8) +#define RTL8365MB_L2_MC_D1_MAC3_MSK GENMASK(7, 0) +#define RTL8365MB_L2_MC_D1_MAC2_MSK GENMASK(15, 8) +#define RTL8365MB_L2_MC_D2_MAC1_MSK GENMASK(7, 0) +#define RTL8365MB_L2_MC_D2_MAC0_MSK GENMASK(15, 8) +#define RTL8365MB_L2_MC_D3_VID_MSK GENMASK(11, 0) +#define RTL8365MB_L2_MC_D3_IVL_MSK GENMASK(13, 13) +#define RTL8365MB_L2_MC_D3_MBR_HI1_MSK GENMASK(15, 14) +#define RTL8365MB_L2_MC_MBR_HI1_MSK GENMASK(9, 8) + +#define RTL8365MB_L2_MC_D4_MBR_MSK GENMASK(7, 0) +#define RTL8365MB_L2_MC_MBR_LO_MSK GENMASK(7, 0) +#define RTL8365MB_L2_MC_D4_IGMPIDX_MSK GENMASK(15, 8) + +#define RTL8365MB_L2_MC_D5_IGMP_ASIC_MSK GENMASK(0, 0) +#define RTL8365MB_L2_MC_D5_PRIORITY_MSK GENMASK(3, 1) +#define RTL8365MB_L2_MC_D5_FWD_PRI_MSK GENMASK(4, 4) +#define RTL8365MB_L2_MC_D5_STATIC_MSK GENMASK(5, 5) +#define RTL8365MB_L2_MC_D5_MBR_HI2_MSK GENMASK(7, 7) +#define RTL8365MB_L2_MC_MBR_HI2_MSK GENMASK(10, 10) + +/* Port flush command registers - writing a 1 to the port's MASK bit will + * initiate the flush procedure. Completion is signalled when the correspo= nding + * BUSY bit is 0. + */ +#define RTL8365MB_L2_FLUSH_PORT_REG 0x0A36 +#define RTL8365MB_L2_FLUSH_PORT_MSK_MSK GENMASK(7, 0) +#define RTL8365MB_L2_FLUSH_PORT_BUSY_MSK GENMASK(15, 8) + +#define RTL8365MB_L2_FLUSH_PORT_EXT_REG 0x0A35 +#define RTL8365MB_L2_FLUSH_PORT_EXT_MSK_MSK GENMASK(2, 0) +#define RTL8365MB_L2_FLUSH_PORT_EXT_BUSY_MSK GENMASK(5, 3) + +#define RTL8365MB_L2_FLUSH_CTRL1_REG 0x0A37 +#define RTL8365MB_L2_FLUSH_CTRL1_VID_MSK GENMASK(11, 0) +#define RTL8365MB_L2_FLUSH_CTRL1_FID_MSK GENMASK(15, 12) + +#define RTL8365MB_L2_FLUSH_CTRL2_REG 0x0A38 +#define RTL8365MB_L2_FLUSH_CTRL2_MODE_MSK GENMASK(1, 0) +#define RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT 0 +#define RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT_VID 1 +#define RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT_FID 2 +#define RTL8365MB_L2_FLUSH_CTRL2_TYPE_MSK GENMASK(2, 2) +#define RTL8365MB_L2_FLUSH_CTRL2_TYPE_DYNAMIC 0 +#define RTL8365MB_L2_FLUSH_CTRL2_TYPE_BOTH 1 + +/* This flushes the entire LUT, reading it back it will turn 0 when the + * operation is complete + */ +#define RTL8365MB_L2_FLUSH_CTRL3_REG 0x0A39 +#define RTL8365MB_L2_FLUSH_CTRL3_MSK GENMASK(0, 0) + +struct rtl8365mb_l2_uc_key { + u8 mac_addr[ETH_ALEN]; + u16 vid; + u16 fid; + bool ivl; + u16 efid; +}; + +struct rtl8365mb_l2_uc { + struct rtl8365mb_l2_uc_key key; + u8 port; + u8 age; + u8 priority; + + bool sa_block; + bool da_block; + bool auth; + bool is_static; + bool sa_pri; + bool fwd_pri; +}; + +struct rtl8365mb_l2_mc_key { + u8 mac_addr[ETH_ALEN]; + union { + u16 vid; /* IVL */ + u16 fid; /* SVL */ + }; + bool ivl; +}; + +struct rtl8365mb_l2_mc { + struct rtl8365mb_l2_mc_key key; + u16 member; + u8 priority; + u8 igmpidx; + + bool is_static; + bool fwd_pri; + bool igmp_asic; +}; + +static void rtl8365mb_l2_data_to_uc(const u16 *data, struct rtl8365mb_l2_u= c *uc) +{ + u32 val; + + uc->key.mac_addr[5] =3D FIELD_GET(RTL8365MB_L2_UC_D0_MAC5_MSK, data[0]); + uc->key.mac_addr[4] =3D FIELD_GET(RTL8365MB_L2_UC_D0_MAC4_MSK, data[0]); + uc->key.mac_addr[3] =3D FIELD_GET(RTL8365MB_L2_UC_D1_MAC3_MSK, data[1]); + uc->key.mac_addr[2] =3D FIELD_GET(RTL8365MB_L2_UC_D1_MAC2_MSK, data[1]); + uc->key.mac_addr[1] =3D FIELD_GET(RTL8365MB_L2_UC_D2_MAC1_MSK, data[2]); + uc->key.mac_addr[0] =3D FIELD_GET(RTL8365MB_L2_UC_D2_MAC0_MSK, data[2]); + uc->key.efid =3D FIELD_GET(RTL8365MB_L2_UC_D4_EFID_MSK, data[4]); + uc->key.vid =3D FIELD_GET(RTL8365MB_L2_UC_D3_VID_MSK, data[3]); + uc->key.ivl =3D FIELD_GET(RTL8365MB_L2_UC_D3_IVL_MSK, data[3]); + uc->key.fid =3D FIELD_GET(RTL8365MB_L2_UC_D4_FID_MSK, data[4]); + uc->age =3D FIELD_GET(RTL8365MB_L2_UC_D4_AGE_MSK, data[4]); + uc->auth =3D FIELD_GET(RTL8365MB_L2_UC_D4_AUTH_MSK, data[4]); + + val =3D FIELD_GET(RTL8365MB_L2_UC_D4_PORT_MSK, data[4]); + uc->port =3D FIELD_PREP(RTL8365MB_L2_UC_PORT_LO_MSK, val); + val =3D FIELD_GET(RTL8365MB_L2_UC_D3_PORT_EXT_MSK, data[3]); + uc->port |=3D FIELD_PREP(RTL8365MB_L2_UC_PORT_HI_MSK, val); + + uc->sa_pri =3D FIELD_GET(RTL8365MB_L2_UC_D4_SA_PRI_MSK, data[4]); + uc->fwd_pri =3D FIELD_GET(RTL8365MB_L2_UC_D5_FWD_PRI_MSK, data[5]); + uc->sa_block =3D FIELD_GET(RTL8365MB_L2_UC_D4_SA_BLOCK_MSK, data[4]); + uc->da_block =3D FIELD_GET(RTL8365MB_L2_UC_D5_DA_BLOCK_MSK, data[5]); + uc->priority =3D FIELD_GET(RTL8365MB_L2_UC_D5_PRIORITY_MSK, data[5]); + uc->is_static =3D FIELD_GET(RTL8365MB_L2_UC_D5_STATIC_MSK, data[5]); +} + +static void rtl8365mb_l2_uc_to_data(const struct rtl8365mb_l2_uc *uc, u16 = *data) +{ + u32 val; + + memset(data, 0, RTL8365MB_L2_ENTRY_SIZE * 2); + data[0] |=3D + FIELD_PREP(RTL8365MB_L2_UC_D0_MAC5_MSK, uc->key.mac_addr[5]); + data[0] |=3D + FIELD_PREP(RTL8365MB_L2_UC_D0_MAC4_MSK, uc->key.mac_addr[4]); + data[1] |=3D + FIELD_PREP(RTL8365MB_L2_UC_D1_MAC3_MSK, uc->key.mac_addr[3]); + data[1] |=3D + FIELD_PREP(RTL8365MB_L2_UC_D1_MAC2_MSK, uc->key.mac_addr[2]); + data[2] |=3D + FIELD_PREP(RTL8365MB_L2_UC_D2_MAC1_MSK, uc->key.mac_addr[1]); + data[2] |=3D + FIELD_PREP(RTL8365MB_L2_UC_D2_MAC0_MSK, uc->key.mac_addr[0]); + data[3] |=3D FIELD_PREP(RTL8365MB_L2_UC_D3_VID_MSK, uc->key.vid); + data[3] |=3D FIELD_PREP(RTL8365MB_L2_UC_D3_IVL_MSK, uc->key.ivl); + + val =3D FIELD_GET(RTL8365MB_L2_UC_PORT_HI_MSK, uc->port); + data[3] |=3D FIELD_PREP(RTL8365MB_L2_UC_D3_PORT_EXT_MSK, val); + + data[4] |=3D FIELD_PREP(RTL8365MB_L2_UC_D4_FID_MSK, uc->key.fid); + data[4] |=3D FIELD_PREP(RTL8365MB_L2_UC_D4_EFID_MSK, uc->key.efid); + data[4] |=3D FIELD_PREP(RTL8365MB_L2_UC_D4_AGE_MSK, uc->age); + data[4] |=3D FIELD_PREP(RTL8365MB_L2_UC_D4_AUTH_MSK, uc->auth); + + val =3D FIELD_GET(RTL8365MB_L2_UC_PORT_LO_MSK, uc->port); + data[4] |=3D FIELD_PREP(RTL8365MB_L2_UC_D4_PORT_MSK, val); + + data[4] |=3D FIELD_PREP(RTL8365MB_L2_UC_D4_SA_PRI_MSK, uc->sa_pri); + data[4] |=3D FIELD_PREP(RTL8365MB_L2_UC_D4_SA_BLOCK_MSK, uc->sa_block); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_UC_D5_FWD_PRI_MSK, uc->fwd_pri); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_UC_D5_DA_BLOCK_MSK, uc->da_block); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_UC_D5_PRIORITY_MSK, uc->priority); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_UC_D5_STATIC_MSK, uc->is_static); +} + +static void rtl8365mb_l2_data_to_mc(const u16 *data, struct rtl8365mb_l2_m= c *mc) +{ + u32 val; + + mc->key.mac_addr[5] =3D FIELD_GET(RTL8365MB_L2_MC_D0_MAC5_MSK, data[0]); + mc->key.mac_addr[4] =3D FIELD_GET(RTL8365MB_L2_MC_D0_MAC4_MSK, data[0]); + mc->key.mac_addr[3] =3D FIELD_GET(RTL8365MB_L2_MC_D1_MAC3_MSK, data[1]); + mc->key.mac_addr[2] =3D FIELD_GET(RTL8365MB_L2_MC_D1_MAC2_MSK, data[1]); + mc->key.mac_addr[1] =3D FIELD_GET(RTL8365MB_L2_MC_D2_MAC1_MSK, data[2]); + mc->key.mac_addr[0] =3D FIELD_GET(RTL8365MB_L2_MC_D2_MAC0_MSK, data[2]); + /* key.vid,key.fid shares the same memory space */ + mc->key.vid =3D FIELD_GET(RTL8365MB_L2_MC_D3_VID_MSK, data[3]); + mc->key.ivl =3D FIELD_GET(RTL8365MB_L2_MC_D3_IVL_MSK, data[3]); + mc->priority =3D FIELD_GET(RTL8365MB_L2_MC_D5_PRIORITY_MSK, data[5]); + mc->fwd_pri =3D FIELD_GET(RTL8365MB_L2_MC_D5_FWD_PRI_MSK, data[5]); + mc->is_static =3D FIELD_GET(RTL8365MB_L2_MC_D5_STATIC_MSK, data[5]); + + val =3D FIELD_GET(RTL8365MB_L2_MC_D4_MBR_MSK, data[4]); + mc->member =3D FIELD_PREP(RTL8365MB_L2_MC_MBR_LO_MSK, val); + val =3D FIELD_GET(RTL8365MB_L2_MC_D3_MBR_HI1_MSK, data[3]); + mc->member |=3D FIELD_PREP(RTL8365MB_L2_MC_MBR_HI1_MSK, val); + val =3D FIELD_GET(RTL8365MB_L2_MC_D5_MBR_HI2_MSK, data[5]); + mc->member |=3D FIELD_PREP(RTL8365MB_L2_MC_MBR_HI2_MSK, val); + + mc->igmpidx =3D FIELD_GET(RTL8365MB_L2_MC_D4_IGMPIDX_MSK, data[4]); + mc->igmp_asic =3D FIELD_GET(RTL8365MB_L2_MC_D5_IGMP_ASIC_MSK, data[5]); +} + +static void rtl8365mb_l2_mc_to_data(const struct rtl8365mb_l2_mc *mc, u16 = *data) +{ + u32 val; + + memset(data, 0, RTL8365MB_L2_ENTRY_SIZE * 2); + data[0] |=3D FIELD_PREP(RTL8365MB_L2_MC_D0_MAC5_MSK, mc->key.mac_addr[5]); + data[0] |=3D FIELD_PREP(RTL8365MB_L2_MC_D0_MAC4_MSK, mc->key.mac_addr[4]); + data[1] |=3D FIELD_PREP(RTL8365MB_L2_MC_D1_MAC3_MSK, mc->key.mac_addr[3]); + data[1] |=3D FIELD_PREP(RTL8365MB_L2_MC_D1_MAC2_MSK, mc->key.mac_addr[2]); + data[2] |=3D FIELD_PREP(RTL8365MB_L2_MC_D2_MAC1_MSK, mc->key.mac_addr[1]); + data[2] |=3D FIELD_PREP(RTL8365MB_L2_MC_D2_MAC0_MSK, mc->key.mac_addr[0]); + data[3] |=3D FIELD_PREP(RTL8365MB_L2_MC_D3_VID_MSK, mc->key.vid); + data[3] |=3D FIELD_PREP(RTL8365MB_L2_MC_D3_IVL_MSK, mc->key.ivl); + + val =3D FIELD_GET(RTL8365MB_L2_MC_MBR_HI1_MSK, mc->member); + data[3] |=3D FIELD_PREP(RTL8365MB_L2_MC_D3_MBR_HI1_MSK, val); + + val =3D FIELD_GET(RTL8365MB_L2_MC_MBR_LO_MSK, mc->member); + data[4] |=3D FIELD_PREP(RTL8365MB_L2_MC_D4_MBR_MSK, val); + + data[4] |=3D FIELD_PREP(RTL8365MB_L2_MC_D4_IGMPIDX_MSK, mc->igmpidx); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_MC_D5_IGMP_ASIC_MSK, mc->igmp_asic); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_MC_D5_PRIORITY_MSK, mc->priority); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_MC_D5_FWD_PRI_MSK, mc->fwd_pri); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_MC_D5_STATIC_MSK, mc->is_static); + + val =3D FIELD_GET(RTL8365MB_L2_MC_MBR_HI2_MSK, mc->member); + data[5] |=3D FIELD_PREP(RTL8365MB_L2_MC_D5_MBR_HI2_MSK, val); +} + +/** + * rtl8365mb_l2_get_next_uc() - get the next Unicast L2 entry + * @priv: realtek_priv pointer + * @addr: as input, the table index to start the walk + * as output, the found table index + * @port: restrict the walk on entries related to port + * @entry: returned L2 Unicast table entry + * + * This function get the next unicast L2 table entry starting from @addr + * and checking exclusively entries related to @port. If no more entries + * were found, the output @addr will be lower than the input @addr and @en= try + * will not be overwritten. + * + * Return: Returns 0 on success, a negative error on failure. + **/ +int rtl8365mb_l2_get_next_uc(struct realtek_priv *priv, u16 *addr, int por= t, + struct realtek_fdb_entry *entry) +{ + u16 data[RTL8365MB_L2_ENTRY_SIZE] =3D { 0 }; + struct rtl8365mb_l2_uc uc; + int ret; + + ret =3D rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2, + RTL8365MB_TABLE_OP_READ, addr, + RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT, + port, data, RTL8365MB_L2_ENTRY_SIZE); + if (ret) + return ret; + + rtl8365mb_l2_data_to_uc(data, &uc); + + ether_addr_copy(entry->mac_addr, uc.key.mac_addr); + entry->vid =3D uc.key.vid; + entry->is_static =3D uc.is_static; + + return 0; +} + +int rtl8365mb_l2_add_uc(struct realtek_priv *priv, int port, + const unsigned char mac_addr[static ETH_ALEN], + u16 efid, u16 vid) +{ + u16 data[RTL8365MB_L2_ENTRY_SIZE] =3D { 0 }; + struct rtl8365mb_l2_uc uc =3D { 0 }; + u16 addr; + int ret; + + memcpy(uc.key.mac_addr, mac_addr, ETH_ALEN); + uc.key.efid =3D efid; + uc.key.fid =3D 0; + uc.key.ivl =3D true; + uc.key.vid =3D vid; + + uc.port =3D port; + /* do not let HW decrease age */ + uc.is_static =3D true; + /* age greater than 0 adds/updates entries */ + uc.age =3D 1; + rtl8365mb_l2_uc_to_data(&uc, data); + + /* add the new entry or update an existing one */ + ret =3D rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2, + RTL8365MB_TABLE_OP_WRITE, &addr, + 0, 0, + data, RTL8365MB_L2_ENTRY_SIZE); + + /* Assume the missing new entry as the table is full */ + if (ret =3D=3D -ENOENT) + return -ENOSPC; + + /* addr will hold the table index, but it is not used here */ + return ret; +} + +int rtl8365mb_l2_del_uc(struct realtek_priv *priv, int port, + const unsigned char mac_addr[static ETH_ALEN], + u16 efid, u16 vid) +{ + u16 data[RTL8365MB_L2_ENTRY_SIZE] =3D { 0 }; + struct rtl8365mb_l2_uc uc =3D { 0 }; + u16 addr; + int ret; + + memcpy(uc.key.mac_addr, mac_addr, ETH_ALEN); + uc.key.efid =3D efid; + uc.key.fid =3D 0; + uc.key.ivl =3D true; + uc.key.vid =3D vid; + /* age 0 deletes the entry */ + uc.age =3D 0; + rtl8365mb_l2_uc_to_data(&uc, data); + + /* it looks like the switch will always add/update the entry, + * even when age is 0 or uc.key did not match an existing entry, + * just to immediately drop it because age is zero. You can still + * get the added/updated address from @addr + */ + ret =3D rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2, + RTL8365MB_TABLE_OP_WRITE, &addr, + 0, 0, + data, RTL8365MB_L2_ENTRY_SIZE); + + if (ret =3D=3D -ENOENT) { + dev_dbg(priv->dev, "%s: %pM vid=3D%d efid=3D%d missing\n", + __func__, mac_addr, vid, efid); + /* Silently return success */ + return 0; + } + + /* addr will hold the table index, but it is not used here */ + return ret; +} + +int rtl8365mb_l2_flush(struct realtek_priv *priv, int port, u16 vid) +{ + int mode =3D vid ? RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT_VID : + RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT; + u32 val, mask; + int ret; + + mutex_lock(&priv->map_lock); + + /* Configure flushing mode; only flush dynamic entries */ + ret =3D regmap_write(priv->map_nolock, RTL8365MB_L2_FLUSH_CTRL2_REG, + FIELD_PREP(RTL8365MB_L2_FLUSH_CTRL2_MODE_MSK, + mode) | + FIELD_PREP(RTL8365MB_L2_FLUSH_CTRL2_TYPE_MSK, + RTL8365MB_L2_FLUSH_CTRL2_TYPE_DYNAMIC)); + if (ret) + goto out; + + ret =3D regmap_write(priv->map_nolock, RTL8365MB_L2_FLUSH_CTRL1_REG, + FIELD_PREP(RTL8365MB_L2_FLUSH_CTRL1_VID_MSK, vid)); + + if (ret) + goto out; + /* Now issue the flush command and wait for its completion. There are + * two registers for this purpose, and which one to use depends on the + * port number. The _EXT register is for ports 8 or higher. + */ + if (port < 8) { + val =3D FIELD_PREP(RTL8365MB_L2_FLUSH_PORT_MSK_MSK, + BIT(port) & 0xFF); + ret =3D regmap_write(priv->map_nolock, + RTL8365MB_L2_FLUSH_PORT_REG, val); + if (ret) + goto out; + + mask =3D FIELD_PREP(RTL8365MB_L2_FLUSH_PORT_BUSY_MSK, + BIT(port) & 0xFF); + ret =3D regmap_read_poll_timeout(priv->map_nolock, + RTL8365MB_L2_FLUSH_PORT_REG, + val, !(val & mask), 10, 10000); + if (ret) + goto out; + } else { + val =3D FIELD_PREP(RTL8365MB_L2_FLUSH_PORT_EXT_MSK_MSK, + BIT(port) >> 8); + ret =3D regmap_write(priv->map_nolock, + RTL8365MB_L2_FLUSH_PORT_EXT_REG, val); + if (ret) + goto out; + + mask =3D FIELD_PREP(RTL8365MB_L2_FLUSH_PORT_EXT_BUSY_MSK, + BIT(port) >> 8); + ret =3D regmap_read_poll_timeout(priv->map_nolock, + RTL8365MB_L2_FLUSH_PORT_EXT_REG, + val, !(val & mask), 10, 10000); + if (ret) + goto out; + } + +out: + mutex_unlock(&priv->map_lock); + + return ret; +} + +int rtl8365mb_l2_add_mc(struct realtek_priv *priv, int port, + const unsigned char mac_addr[static ETH_ALEN], + u16 vid) +{ + u16 data[RTL8365MB_L2_ENTRY_SIZE] =3D { 0 }; + struct rtl8365mb_l2_mc mc =3D { 0 }; + u16 addr; + int ret; + + memcpy(mc.key.mac_addr, mac_addr, ETH_ALEN); + mc.key.vid =3D vid; + mc.key.ivl =3D true; + /* Already set the port and is_static, although not used in OP_READ, + * data will be ready for OP_WRITE if it is a new entry. + */ + mc.member |=3D BIT(port); + mc.is_static =3D 1; + rtl8365mb_l2_mc_to_data(&mc, data); + + /* First look for an existing entry (to get existing port members) */ + ret =3D rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2, + RTL8365MB_TABLE_OP_READ, &addr, + RTL8365MB_TABLE_L2_METHOD_MAC, 0, + data, RTL8365MB_L2_ENTRY_SIZE); + if (!ret) { + /* There is already an entry... */ + rtl8365mb_l2_data_to_mc(data, &mc); + dev_dbg(priv->dev, + "%s: found %pM addr=3D%d member=3D0x%x igmpidx=3D0x%x %s\n", + __func__, mac_addr, addr, mc.member, mc.igmpidx, + mc.is_static ? "static" : "dynamic"); + /* the port must be added as a member */ + mc.member |=3D BIT(port); + + if (!mc.is_static) { + dev_dbg(priv->dev, + "%s: promoting addr=3D%d group to static\n", + __func__, addr); + mc.is_static =3D 1; + } + + rtl8365mb_l2_mc_to_data(&mc, data); + } else if (ret =3D=3D -ENOENT) { + /* New entry, no need to update data again as it already + * includes the member. + * + * Multicast hardware entries do not support EFID (bridge + * isolation). However, traffic isolation is still maintained + * because the hardware applies the port isolation masks + * (pmasks) configured in bridge_join after the L2 lookup. + * Entries from different bridges will collide on the same + * MAC+VID slot with an OR'ed member mask, but packets will + * only exit through ports allowed by the source port's pmask. + */ + } else { + return ret; + } + + /* add the new entry or update an existing one */ + ret =3D rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2, + RTL8365MB_TABLE_OP_WRITE, &addr, + 0, 0, + data, RTL8365MB_L2_ENTRY_SIZE); + + /* Assume the missing new entry as the table is full */ + if (ret =3D=3D -ENOENT) + return -ENOSPC; + + return ret; +} + +int rtl8365mb_l2_del_mc(struct realtek_priv *priv, int port, + const unsigned char mac_addr[static ETH_ALEN], + u16 vid) +{ + u16 data[RTL8365MB_L2_ENTRY_SIZE] =3D { 0 }; + struct rtl8365mb_l2_mc mc =3D { 0 }; + u16 addr; + int ret; + + memcpy(mc.key.mac_addr, mac_addr, ETH_ALEN); + mc.key.vid =3D vid; + mc.key.ivl =3D true; + rtl8365mb_l2_mc_to_data(&mc, data); + + /* First look for an existing entry (to get existing port members) */ + ret =3D rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2, + RTL8365MB_TABLE_OP_READ, &addr, + RTL8365MB_TABLE_L2_METHOD_MAC, 0, + data, RTL8365MB_L2_ENTRY_SIZE); + if (ret =3D=3D -ENOENT) { + dev_dbg(priv->dev, "%s: %pM vid=3D%d missing\n", + __func__, mac_addr, vid); + /* Silently return success */ + return 0; + } + + if (ret) + /* Return on any other error */ + return ret; + + rtl8365mb_l2_data_to_mc(data, &mc); + dev_dbg(priv->dev, + "%s: found %pM addr=3D%d member=3D0x%x igmpidx=3D0x%x %s\n", + __func__, mac_addr, addr, mc.member, mc.igmpidx, + mc.is_static ? "static" : "dynamic"); + /* the port must be removed as a member */ + mc.member &=3D ~BIT(port); + if (!mc.member) { + /* Multicast entries do not have an age field. Clearing both + * the member portmask and is_static flags is the hardware + * signal to invalidate and reclaim the L2 table slot. + */ + mc.is_static =3D 0; + mc.igmpidx =3D 0; + mc.priority =3D 0; + mc.fwd_pri =3D 0; + mc.igmp_asic =3D 0; + } + rtl8365mb_l2_mc_to_data(&mc, data); + + /* update the existing entry. */ + ret =3D rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2, + RTL8365MB_TABLE_OP_WRITE, &addr, + 0, 0, + data, RTL8365MB_L2_ENTRY_SIZE); + return ret; +} diff --git a/drivers/net/dsa/realtek/rtl8365mb_l2.h b/drivers/net/dsa/realt= ek/rtl8365mb_l2.h new file mode 100644 index 000000000000..9470cf059ce5 --- /dev/null +++ b/drivers/net/dsa/realtek/rtl8365mb_l2.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Forwarding and multicast database interface for the rtl8365mb switch fa= mily + * + * Copyright (C) 2022 Alvin =C5=A0ipraga + */ + +#ifndef _REALTEK_RTL8365MB_L2_H +#define _REALTEK_RTL8365MB_L2_H + +#include +#include + +#include "realtek.h" + +int rtl8365mb_l2_get_next_uc(struct realtek_priv *priv, u16 *addr, int por= t, + struct realtek_fdb_entry *entry); +int rtl8365mb_l2_add_uc(struct realtek_priv *priv, int port, + const unsigned char addr[static ETH_ALEN], + u16 efid, u16 vid); +int rtl8365mb_l2_del_uc(struct realtek_priv *priv, int port, + const unsigned char addr[static ETH_ALEN], + u16 efid, u16 vid); +int rtl8365mb_l2_flush(struct realtek_priv *priv, int port, u16 vid); + +int rtl8365mb_l2_add_mc(struct realtek_priv *priv, int port, + const unsigned char mac_addr[static ETH_ALEN], + u16 vid); +int rtl8365mb_l2_del_mc(struct realtek_priv *priv, int port, + const unsigned char mac_addr[static ETH_ALEN], + u16 vid); + +#endif /* _REALTEK_RTL8365MB_L2_H */ diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/rea= ltek/rtl8365mb_main.c index c70e162038cd..3f7dc568d210 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -104,6 +104,7 @@ #include "realtek-smi.h" #include "realtek-mdio.h" #include "rtl83xx.h" +#include "rtl8365mb_l2.h" #include "rtl8365mb_vlan.h" =20 /* Family-specific data and limits */ @@ -111,8 +112,15 @@ #define RTL8365MB_NUM_PHYREGS 32 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) #define RTL8365MB_MAX_NUM_PORTS 11 -#define RTL8365MB_MAX_NUM_EXTINTS 3 +/* Valid for the whole family except RTL8370B, which has 4160 entries. + * RTL8370B is mentioned in vendor code but it might not even belong + * to the same RTL8367C family. + */ #define RTL8365MB_LEARN_LIMIT_MAX 2112 +#define RTL8365MB_MAX_NUM_EXTINTS 3 + +/* The LUT table size matches the maximum learning limit */ +#define RTL8365MB_L2_TABLE_SIZE RTL8365MB_LEARN_LIMIT_MAX =20 /* Chip identification registers */ #define RTL8365MB_CHIP_ID_REG 0x1300 @@ -2454,6 +2462,8 @@ static int rtl8365mb_setup(struct dsa_switch *ds) if (ret) goto out_teardown_irq; =20 + ds->assisted_learning_on_cpu_port =3D true; + ds->fdb_isolation =3D true; /* The EFID is 3 bits, but EFID 0 is reserved for standalone ports */ ds->max_num_bridges =3D FIELD_MAX(RTL8365MB_EFID_MASK); ds->configure_vlan_while_not_filtering =3D true; @@ -2575,6 +2585,12 @@ static const struct dsa_switch_ops rtl8365mb_switch_= ops =3D { .port_bridge_join =3D rtl83xx_port_bridge_join, .port_bridge_leave =3D rtl83xx_port_bridge_leave, .port_stp_state_set =3D rtl8365mb_port_stp_state_set, + .port_fast_age =3D rtl83xx_port_fast_age, + .port_fdb_add =3D rtl83xx_port_fdb_add, + .port_fdb_del =3D rtl83xx_port_fdb_del, + .port_fdb_dump =3D rtl83xx_port_fdb_dump, + .port_mdb_add =3D rtl83xx_port_mdb_add, + .port_mdb_del =3D rtl83xx_port_mdb_del, .port_vlan_add =3D rtl8365mb_port_vlan_add, .port_vlan_del =3D rtl8365mb_port_vlan_del, .port_vlan_filtering =3D rtl8365mb_port_vlan_filtering, @@ -2597,6 +2613,12 @@ static const struct realtek_ops rtl8365mb_ops =3D { .port_remove_isolation =3D rtl8365mb_port_remove_isolation, .port_set_efid =3D rtl8365mb_port_set_efid, .port_set_learning =3D rtl8365mb_port_set_learning, + .l2_add_uc =3D rtl8365mb_l2_add_uc, + .l2_del_uc =3D rtl8365mb_l2_del_uc, + .l2_get_next_uc =3D rtl8365mb_l2_get_next_uc, + .l2_add_mc =3D rtl8365mb_l2_add_mc, + .l2_del_mc =3D rtl8365mb_l2_del_mc, + .l2_flush =3D rtl8365mb_l2_flush, .phy_read =3D rtl8365mb_phy_read, .phy_write =3D rtl8365mb_phy_write, }; @@ -2608,6 +2630,7 @@ const struct realtek_variant rtl8365mb_variant =3D { .clk_delay =3D 10, .cmd_read =3D 0xb9, .cmd_write =3D 0xb8, + .l2_table_size =3D RTL8365MB_L2_TABLE_SIZE, .chip_data_sz =3D sizeof(struct rtl8365mb), }; =20 diff --git a/drivers/net/dsa/realtek/rtl83xx.c b/drivers/net/dsa/realtek/rt= l83xx.c index bd38091fdc76..9151d7fa6700 100644 --- a/drivers/net/dsa/realtek/rtl83xx.c +++ b/drivers/net/dsa/realtek/rtl83xx.c @@ -3,6 +3,7 @@ #include #include #include +#include =20 #include "realtek.h" #include "rtl83xx.h" @@ -156,6 +157,7 @@ rtl83xx_probe(struct device *dev, =20 mutex_init(&priv->map_lock); mutex_init(&priv->vlan_lock); + mutex_init(&priv->l2_lock); =20 rc.lock_arg =3D priv; priv->map =3D devm_regmap_init(dev, NULL, priv, &rc); @@ -475,6 +477,321 @@ void rtl83xx_port_bridge_leave(struct dsa_switch *ds,= int port, } EXPORT_SYMBOL_NS_GPL(rtl83xx_port_bridge_leave, "REALTEK_DSA"); =20 +/** + * rtl83xx_port_fast_age() - flush dynamic FDB entries learned on a port + * @ds: DSA switch instance + * @port: port index + * + * This function requests the switch to age out dynamic FDB entries learne= d on + * @port. + * + * Context: Can sleep. + * Return: Nothing. + */ +void rtl83xx_port_fast_age(struct dsa_switch *ds, int port) +{ + struct realtek_priv *priv =3D ds->priv; + int ret; + + if (!priv->ops->l2_flush) { + dev_warn_once(priv->dev, "l2_flush op not defined\n"); + return; + } + + dev_dbg(priv->dev, "fast_age port %d\n", port); + + mutex_lock(&priv->l2_lock); + ret =3D priv->ops->l2_flush(priv, port, 0); + mutex_unlock(&priv->l2_lock); + if (ret) + dev_err(priv->dev, "failed to fast age on port %d: %d\n", port, + ret); +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_fast_age, "REALTEK_DSA"); + +/** + * rtl83xx_port_fdb_add() - add a static FDB entry to a port database + * @ds: DSA switch instance + * @port: port index + * @addr: MAC address to add + * @vid: VLAN ID associated with @addr + * @db: database where the entry should be added + * + * This function adds a static unicast FDB entry to the standalone port + * database or to a bridge database. + * + * Context: Can sleep. + * Return: 0 on success, negative value for failure. + */ +int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct realtek_priv *priv =3D ds->priv; + int efid; + int ret; + + if (is_multicast_ether_addr(addr)) { + if (!priv->ops->l2_add_mc) + return -EOPNOTSUPP; + } else { + if (!priv->ops->l2_add_uc) + return -EOPNOTSUPP; + } + + if (db.type !=3D DSA_DB_PORT && db.type !=3D DSA_DB_BRIDGE) + return -EOPNOTSUPP; + + /* Bridge ports use bridge.num as EFID, while standalone ports use + * EFID 0. FDB entries for the CPU port follow the bridge EFID due + * to assisted learning. + */ + efid =3D db.type =3D=3D DSA_DB_BRIDGE ? db.bridge.num : 0; + + dev_dbg(priv->dev, "%s: port:%d addr:%pM efid:%d vid:%d dbtype:%d\n", + __func__, port, addr, efid, vid, db.type); + + mutex_lock(&priv->l2_lock); + if (is_multicast_ether_addr(addr)) { + dev_dbg(priv->dev, "%s: port:%d addr:%pM is multicast\n", + __func__, port, addr); + ret =3D priv->ops->l2_add_mc(priv, port, addr, vid); + } else { + ret =3D priv->ops->l2_add_uc(priv, port, addr, efid, vid); + } + + mutex_unlock(&priv->l2_lock); + + if (ret) + dev_err(priv->dev, "fdb_add ERROR %pe\n", ERR_PTR(ret)); + return ret; +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_fdb_add, "REALTEK_DSA"); + +/** + * rtl83xx_port_fdb_del() - delete a static FDB entry from a port database + * @ds: DSA switch instance + * @port: port index + * @addr: MAC address to delete + * @vid: VLAN ID associated with @addr + * @db: database where the entry should be removed + * + * This function deletes a static unicast FDB entry from the standalone po= rt + * database or from a bridge database. + * + * Context: Can sleep. + * Return: 0 on success, negative value for failure. + */ +int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct realtek_priv *priv =3D ds->priv; + int efid; + int ret; + + if (is_multicast_ether_addr(addr)) { + if (!priv->ops->l2_del_mc) + return -EOPNOTSUPP; + } else { + if (!priv->ops->l2_del_uc) + return -EOPNOTSUPP; + } + + if (db.type !=3D DSA_DB_PORT && db.type !=3D DSA_DB_BRIDGE) + return -EOPNOTSUPP; + + /* + * DSA_DB_BRIDGE ports use bridge number [1..N] as EFID, while + * DSA_DB_PORT use the default EFID (0), not used by any bridge. + */ + efid =3D db.type =3D=3D DSA_DB_BRIDGE ? db.bridge.num : 0; + + dev_dbg(priv->dev, "%s: port:%d addr:%pM efid:%d vid:%d dbtype:%d\n", + __func__, port, addr, efid, vid, db.type); + + mutex_lock(&priv->l2_lock); + if (is_multicast_ether_addr(addr)) { + dev_dbg(priv->dev, "%s: port:%d addr:%pM is multicast\n", + __func__, port, addr); + ret =3D priv->ops->l2_del_mc(priv, port, addr, vid); + } else { + ret =3D priv->ops->l2_del_uc(priv, port, addr, efid, vid); + } + mutex_unlock(&priv->l2_lock); + + if (ret) + dev_err(priv->dev, "fdb_del ERROR %pe\n", ERR_PTR(ret)); + return ret; +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_fdb_del, "REALTEK_DSA"); + +/** + * rtl83xx_port_fdb_dump() - iterate over FDB entries associated with a po= rt + * @ds: DSA switch instance + * @port: port index + * @cb: callback invoked for each entry + * @data: opaque pointer passed to @cb + * + * This function walks the unicast FDB entries associated with @port and c= alls + * @cb for each matching entry. + * + * Context: Can sleep. + * Return: 0 on success, or negative value for failure. + */ +int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) +{ + struct realtek_fdb_entry entry =3D { 0 }; + struct realtek_priv *priv =3D ds->priv; + u16 l2_table_size =3D priv->variant->l2_table_size; + u16 start_addr, addr =3D 0; + int ret =3D 0; + + if (!priv->ops->l2_get_next_uc) + return -EOPNOTSUPP; + if (!l2_table_size) { + dev_warn_once(priv->dev, "l2_table_size not defined\n"); + return -EOPNOTSUPP; + } + + mutex_lock(&priv->l2_lock); + while (true) { + start_addr =3D addr; + + dev_dbg(priv->dev, "l2_get_next_uc, addr:%d, port:%d\n", + addr, port); + ret =3D priv->ops->l2_get_next_uc(priv, &addr, port, &entry); + dev_dbg(priv->dev, + "%s addr:%d mac:%pM vid:%d static:%d ret:%pe\n", + __func__, addr, entry.mac_addr, entry.vid, + entry.is_static, ERR_PTR(ret)); + + if (ret =3D=3D -ENOENT) { + /* If the table is empty, returns without errors. Note + * that the l2_get_next_uc overflow to the first match + * when it reaches the end of the table. + */ + ret =3D 0; + break; + } + + if (ret) + break; + + /* When the addr returned is before the requested one, it + * indicates that we reached the end. + */ + if (addr < start_addr) + break; + + ret =3D cb(entry.mac_addr, entry.vid, entry.is_static, data); + if (ret) + break; + + addr++; + + /* Avoid querying beyond the valid L2 table range. */ + if (addr >=3D l2_table_size) + break; + } + mutex_unlock(&priv->l2_lock); + + return ret; +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_fdb_dump, "REALTEK_DSA"); + +/** + * rtl83xx_port_mdb_add() - add a multicast database entry to a port datab= ase + * @ds: DSA switch instance + * @port: port index + * @mdb: multicast database entry to add + * @db: database where the entry should be added + * + * This function adds a multicast database entry to the standalone port + * database or to a bridge database. + * + * Context: Can sleep. + * Return: 0 on success, negative value for failure. + */ +int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + struct realtek_priv *priv =3D ds->priv; + const unsigned char *addr =3D mdb->addr; + u16 vid =3D mdb->vid; + int efid; + int ret; + + if (!priv->ops->l2_add_mc) + return -EOPNOTSUPP; + + if (db.type !=3D DSA_DB_PORT && db.type !=3D DSA_DB_BRIDGE) + return -EOPNOTSUPP; + + /* EFID is not used by hardware MDB entries; debugging only */ + efid =3D db.type =3D=3D DSA_DB_BRIDGE ? db.bridge.num : 0; + + dev_dbg(priv->dev, "%s: port:%d addr:%pM efid:%d vid:%d dbtype:%d\n", + __func__, port, addr, efid, vid, db.type); + + mutex_lock(&priv->l2_lock); + ret =3D priv->ops->l2_add_mc(priv, port, addr, vid); + mutex_unlock(&priv->l2_lock); + + if (ret) + dev_err(priv->dev, "mdb_add ERROR %pe\n", ERR_PTR(ret)); + return ret; +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_mdb_add, "REALTEK_DSA"); + +/** + * rtl83xx_port_mdb_del() - delete a multicast database entry from a port + * database + * @ds: DSA switch instance + * @port: port index + * @mdb: multicast database entry to delete + * @db: database where the entry should be removed + * + * This function deletes a multicast database entry from the standalone po= rt + * database or from a bridge database. + * + * Context: Can sleep. + * Return: 0 on success, negative value for failure. + */ +int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_mdb *mdb, + struct dsa_db db) +{ + struct realtek_priv *priv =3D ds->priv; + const unsigned char *addr =3D mdb->addr; + u16 vid =3D mdb->vid; + int efid; + int ret; + + if (!priv->ops->l2_del_mc) + return -EOPNOTSUPP; + + if (db.type !=3D DSA_DB_PORT && db.type !=3D DSA_DB_BRIDGE) + return -EOPNOTSUPP; + + /* EFID is not used by hardware MDB entries; debugging only */ + efid =3D db.type =3D=3D DSA_DB_BRIDGE ? db.bridge.num : 0; + + dev_dbg(priv->dev, "%s: port:%d addr:%pM efid:%d vid:%d dbtype:%d\n", + __func__, port, addr, efid, vid, db.type); + + mutex_lock(&priv->l2_lock); + ret =3D priv->ops->l2_del_mc(priv, port, addr, vid); + mutex_unlock(&priv->l2_lock); + + if (ret) + dev_err(priv->dev, "mdb_del ERROR %pe\n", ERR_PTR(ret)); + return ret; +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_mdb_del, "REALTEK_DSA"); + MODULE_AUTHOR("Luiz Angelo Daros de Luca "); MODULE_AUTHOR("Linus Walleij "); MODULE_DESCRIPTION("Realtek DSA switches common module"); diff --git a/drivers/net/dsa/realtek/rtl83xx.h b/drivers/net/dsa/realtek/rt= l83xx.h index 2481a1aaa226..dcb819fe567f 100644 --- a/drivers/net/dsa/realtek/rtl83xx.h +++ b/drivers/net/dsa/realtek/rtl83xx.h @@ -28,4 +28,20 @@ int rtl83xx_port_bridge_join(struct dsa_switch *ds, int = port, void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge); 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Thu, 28 May 2026 21:31:13 -0700 (PDT) Received: from tresc054937.tre-sc.gov.br ([187.65.210.13]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5172ebc7d23sm9260991cf.29.2026.05.28.21.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 21:31:12 -0700 (PDT) From: Luiz Angelo Daros de Luca Date: Fri, 29 May 2026 01:29:53 -0300 Subject: [net-next PATCH v9 8/8] net: dsa: realtek: rtl8365mb: add bridge port flags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-realtek_forward-v9-8-e7c61872d923@gmail.com> References: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> In-Reply-To: <20260529-realtek_forward-v9-0-e7c61872d923@gmail.com> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Yury Norov , Rasmus Villemoes , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Mieczyslaw Nalewaj , Luiz Angelo Daros de Luca X-Mailer: b4 0.15.2 Implement support for bridge port flags to control learning and flooding behavior. This patch maps hardware functionalities to the following bridge flags: - BR_LEARNING - BR_FLOOD - BR_MCAST_FLOOD - BR_BCAST_FLOOD By default, all flooding types are enabled during port setup to ensure standard bridge behavior. Reviewed-by: Linus Walleij Reviewed-by: Mieczyslaw Nalewaj Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/realtek.h | 6 ++ drivers/net/dsa/realtek/rtl8365mb_main.c | 68 +++++++++++++++++++++ drivers/net/dsa/realtek/rtl83xx.c | 101 +++++++++++++++++++++++++++= ++++ drivers/net/dsa/realtek/rtl83xx.h | 4 ++ 4 files changed, 179 insertions(+) diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/re= altek.h index 426c9d345e6e..452e4e6dd157 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -134,6 +134,12 @@ struct realtek_ops { int (*port_set_efid)(struct realtek_priv *priv, int port, u32 efid); int (*port_set_learning)(struct realtek_priv *priv, int port, bool enable); + int (*port_set_ucast_flood)(struct realtek_priv *priv, int port, + bool enable); + int (*port_set_mcast_flood)(struct realtek_priv *priv, int port, + bool enable); + int (*port_set_bcast_flood)(struct realtek_priv *priv, int port, + bool enable); int (*l2_add_uc)(struct realtek_priv *priv, int port, const unsigned char addr[ETH_ALEN], u16 efid, u16 vid); diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/rea= ltek/rtl8365mb_main.c index 3f7dc568d210..2677b2be3220 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -310,6 +310,21 @@ #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) =20 +/* Unknown unicast DA flooding port mask */ +#define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG 0x0890 +#define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_MASK 0x07FF + +/* Unknown multicast DA flooding port mask */ +#define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG 0x0891 +#define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_MASK 0x07FF + +/* Broadcast flooding port mask */ +#define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG 0x0892 +#define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_MASK 0x07FF + +#define RTL8365MB_SUPPORTED_BRIDGE_FLAGS \ + (BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD) + /* Miscellaneous port configuration register, incl. VLAN egress mode */ #define RTL8365MB_PORT_MISC_CFG_REG_BASE 0x000E #define RTL8365MB_PORT_MISC_CFG_REG(_p) \ @@ -1550,6 +1565,49 @@ static int rtl8365mb_port_set_learning(struct realte= k_priv *priv, int port, enable ? RTL8365MB_LEARN_LIMIT_MAX : 0); } =20 +static int rtl8365mb_port_set_ucast_flood(struct realtek_priv *priv, int p= ort, + bool enable) +{ + /* Frames with unknown unicast DA will be flooded to a programmable + * port mask that by default includes all ports. Add or remove + * the specified port from this port mask accordingly. + */ + return regmap_update_bits(priv->map, + RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG, + BIT(port), enable ? BIT(port) : 0); +} + +static int rtl8365mb_port_set_mcast_flood(struct realtek_priv *priv, int p= ort, + bool enable) +{ + return regmap_update_bits(priv->map, + RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG, + BIT(port), enable ? BIT(port) : 0); +} + +static int rtl8365mb_port_set_bcast_flood(struct realtek_priv *priv, int p= ort, + bool enable) +{ + return regmap_update_bits(priv->map, + RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG, + BIT(port), enable ? BIT(port) : 0); +} + +static int rtl8365mb_port_pre_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct realtek_priv *priv =3D ds->priv; + + dev_dbg(priv->dev, "pre_bridge_flags port:%d flags:%lx supported:%lx\n", + port, flags.mask, RTL8365MB_SUPPORTED_BRIDGE_FLAGS); + + if (flags.mask & ~RTL8365MB_SUPPORTED_BRIDGE_FLAGS) + return -EINVAL; + + return 0; +} + static int rtl8365mb_port_set_efid(struct realtek_priv *priv, int port, u32 efid) { @@ -2399,6 +2457,11 @@ static int rtl8365mb_setup(struct dsa_switch *ds) if (ret) goto out_teardown_irq; =20 + /* Enable all types of flooding */ + ret =3D rtl83xx_setup_port_flood_control(priv, dp->index); + if (ret) + goto out_teardown_irq; + /* Set up per-port private data */ p->priv =3D priv; p->index =3D dp->index; @@ -2584,6 +2647,8 @@ static const struct dsa_switch_ops rtl8365mb_switch_o= ps =3D { .phylink_get_caps =3D rtl8365mb_phylink_get_caps, .port_bridge_join =3D rtl83xx_port_bridge_join, .port_bridge_leave =3D rtl83xx_port_bridge_leave, + .port_pre_bridge_flags =3D rtl8365mb_port_pre_bridge_flags, + .port_bridge_flags =3D rtl83xx_port_bridge_flags, .port_stp_state_set =3D rtl8365mb_port_stp_state_set, .port_fast_age =3D rtl83xx_port_fast_age, .port_fdb_add =3D rtl83xx_port_fdb_add, @@ -2613,6 +2678,9 @@ static const struct realtek_ops rtl8365mb_ops =3D { .port_remove_isolation =3D rtl8365mb_port_remove_isolation, .port_set_efid =3D rtl8365mb_port_set_efid, .port_set_learning =3D rtl8365mb_port_set_learning, + .port_set_ucast_flood =3D rtl8365mb_port_set_ucast_flood, + .port_set_mcast_flood =3D rtl8365mb_port_set_mcast_flood, + .port_set_bcast_flood =3D rtl8365mb_port_set_bcast_flood, .l2_add_uc =3D rtl8365mb_l2_add_uc, .l2_del_uc =3D rtl8365mb_l2_del_uc, .l2_get_next_uc =3D rtl8365mb_l2_get_next_uc, diff --git a/drivers/net/dsa/realtek/rtl83xx.c b/drivers/net/dsa/realtek/rt= l83xx.c index 9151d7fa6700..f15a1b287bed 100644 --- a/drivers/net/dsa/realtek/rtl83xx.c +++ b/drivers/net/dsa/realtek/rtl83xx.c @@ -3,6 +3,7 @@ #include #include #include +#include #include =20 #include "realtek.h" @@ -792,6 +793,106 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int p= ort, } EXPORT_SYMBOL_NS_GPL(rtl83xx_port_mdb_del, "REALTEK_DSA"); =20 +/** + * rtl83xx_port_bridge_flags() - set port bridge flags + * @ds: DSA switch instance + * @port: port index + * @flags: bridge port flags + * @extack: netlink extended ack for reporting errors + * + * This function handles setting bridge port flags like learning and flood= ing. + * + * Context: Can sleep. + * Return: 0 on success, negative value for failure. + */ +int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct realtek_priv *priv =3D ds->priv; + bool enable; + int ret; + + if (flags.mask & BR_LEARNING) { + if (!priv->ops->port_set_learning) + return -EOPNOTSUPP; + + enable =3D !!(flags.val & BR_LEARNING); + ret =3D priv->ops->port_set_learning(priv, port, enable); + if (ret) + return ret; + } + + if (flags.mask & BR_FLOOD) { + if (!priv->ops->port_set_ucast_flood) + return -EOPNOTSUPP; + + enable =3D !!(flags.val & BR_FLOOD); + ret =3D priv->ops->port_set_ucast_flood(priv, port, enable); + if (ret) + return ret; + } + + if (flags.mask & BR_MCAST_FLOOD) { + if (!priv->ops->port_set_mcast_flood) + return -EOPNOTSUPP; + + enable =3D !!(flags.val & BR_MCAST_FLOOD); + ret =3D priv->ops->port_set_mcast_flood(priv, port, enable); + if (ret) + return ret; + } + + if (flags.mask & BR_BCAST_FLOOD) { + if (!priv->ops->port_set_bcast_flood) + return -EOPNOTSUPP; + + enable =3D !!(flags.val & BR_BCAST_FLOOD); + ret =3D priv->ops->port_set_bcast_flood(priv, port, enable); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_port_bridge_flags, "REALTEK_DSA"); + +/** + * rtl83xx_setup_port_flood_control() - setup default flood control for a = port + * @priv: realtek_priv pointer + * @port: port index + * + * This function enables flooding for a given port. + * + * Context: Can sleep. + * Return: 0 on success, negative value for failure. + */ +int rtl83xx_setup_port_flood_control(struct realtek_priv *priv, int port) +{ + int ret; + + if (priv->ops->port_set_ucast_flood) { + ret =3D priv->ops->port_set_ucast_flood(priv, port, true); + if (ret) + return ret; + } + + if (priv->ops->port_set_mcast_flood) { + ret =3D priv->ops->port_set_mcast_flood(priv, port, true); + if (ret) + return ret; + } + + if (priv->ops->port_set_bcast_flood) { + ret =3D priv->ops->port_set_bcast_flood(priv, port, true); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_NS_GPL(rtl83xx_setup_port_flood_control, "REALTEK_DSA"); + MODULE_AUTHOR("Luiz Angelo Daros de Luca "); MODULE_AUTHOR("Linus Walleij "); MODULE_DESCRIPTION("Realtek DSA switches common module"); diff --git a/drivers/net/dsa/realtek/rtl83xx.h b/drivers/net/dsa/realtek/rt= l83xx.h index dcb819fe567f..d86447121276 100644 --- a/drivers/net/dsa/realtek/rtl83xx.h +++ b/drivers/net/dsa/realtek/rtl83xx.h @@ -27,6 +27,10 @@ int rtl83xx_port_bridge_join(struct dsa_switch *ds, int = port, struct netlink_ext_ack *extack); void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge); +int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack); +int rtl83xx_setup_port_flood_control(struct realtek_priv *priv, int port); =20 void rtl83xx_port_fast_age(struct dsa_switch *ds, int port); int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port, --=20 2.54.0