From nobody Mon Jun 8 09:49:26 2026 Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ADA7428487; Fri, 29 May 2026 20:58:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780088324; cv=none; b=i1Z4eE4uTyR/M6YoJBiknVSwaSyGu2Icscvfi0AnaM8QKYfBmFe08/bE+XXu4r9Ics/MLzEwWg73muwYNnyR8tvFtev3cyQpyi+fM/6mGkZUcCWd2zDAw3FS+/qetcghxp/wwJcuSVRYKAv3pqplviRexiUFVyB5cpw8DUyw4R0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780088324; c=relaxed/simple; bh=vD28/AyGV0MmCW4G4slp4QTDTlnESABAhUPRS1FugYQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=itH5FEvO9guVZqhpWm3lFzgHDh8zRY3qPcnkQsdMoZ6lxWx5rDRdX22sZyf/89gDboeRSNtIXJV//HiszPz1RqAREpCuy5A59oyr+cL8DHmp1bogks8A1w00FzLmnjIqcVILhgBJ5a571O1E4NgZDiM0VmHMSvfpSZZ2diI8obE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=Ug2e6ITg; arc=none smtp.client-ip=185.70.43.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="Ug2e6ITg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1780088321; x=1780347521; bh=f6tp+bBd2jU8ODsBayxMkDKqDmaxrKiuA1glTqBTayY=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Ug2e6ITgyqZ+q+EUnjwZKlLetIsVOfYqLc0gX0NsKI7mzlaTTxHFRV5zvI2pCU2Cp 790WfYuLojI8/YcgkF4u3vLfes/i7+1+K17qg8XGo13yXUAK5O11D0H9MDNEu+p1sL xe8fkNOBWwDw6qOCmUC1Z7wgZ/preYMuelgyhkzqdPjgwF4t6iznCq29dmoBQEx86J hgyvMx9cFSwkviW9gOHcd+usDrl3zQeJtB6U8UVVxYXQgzfV4rXcjddTE5YZ+r4GIX sdfXRSVjbTTxTWoZzMx5iObWT9jcTSm+ev4lC40ixvQ09Wgm64c20iB9MZxt62qUzM QvO5n3K01KhUQ== Date: Fri, 29 May 2026 20:58:34 +0000 To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Koskovich , Bjorn Andersson , Konrad Dybcio From: Alexander Koskovich Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 1/3] dt-bindings: media: qcom,milos-iris: Add Milos video codec Message-ID: <20260529-milos-iris-v2-1-7a763d7195ae@pm.me> In-Reply-To: <20260529-milos-iris-v2-0-7a763d7195ae@pm.me> References: <20260529-milos-iris-v2-0-7a763d7195ae@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 315cb6a380129afce23b99d1fa2505931176395e Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add binding for Qualcomm Milos Iris video codec. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexander Koskovich --- .../devicetree/bindings/media/qcom,milos-iris.yaml | 166 +++++++++++++++++= ++++ 1 file changed, 166 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml b= /Documentation/devicetree/bindings/media/qcom,milos-iris.yaml new file mode 100644 index 000000000000..36f49590d7b8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,milos-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos SoC Iris video encoder and decoder + +maintainers: + - Alexander Koskovich + +description: + The Iris video processing unit on Qualcomm Milos SoC is a video encode a= nd + decode accelerator. + +properties: + compatible: + enum: + - qcom,milos-iris + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + iommus: + maxItems: 2 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 4 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: cx + - const: mx + + resets: + maxItems: 2 + + reset-names: + items: + - const: bus + - const: core + +required: + - compatible + - dma-coherent + - interconnects + - interconnect-names + - iommus + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + #include + + video-codec@aa00000 { + compatible =3D "qcom,milos-iris"; + reg =3D <0x0aa00000 0xf0000>; + + clocks =3D <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names =3D "iface", + "core", + "vcodec0_core"; + + dma-coherent; + iommus =3D <&apps_smmu 0x1960 0>, + <&apps_smmu 0x1967 0>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_= ONLY + &cnoc_cfg SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONL= Y>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + interrupts =3D ; + + operating-points-v2 =3D <&iris_opp_table>; + + memory-region =3D <&video_mem>; + + power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "venus", + "vcodec0", + "cx", + "mx"; + + resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names =3D "bus", + "core"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-552000000 { + opp-hz =3D /bits/ 64 <552000000>; + required-opps =3D <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; --=20 2.53.0 From nobody Mon Jun 8 09:49:26 2026 Received: from mail-43103.protonmail.ch (mail-43103.protonmail.ch [185.70.43.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 503E242847C; Fri, 29 May 2026 20:58:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add support for the Milos Iris codec. This only supports the variant found on the SM7635-AB that has half of it's pipes disabled via efuse. Signed-off-by: Alexander Koskovich --- .../platform/qcom/iris/iris_platform_common.h | 1 + .../media/platform/qcom/iris/iris_platform_gen2.c | 106 ++++ .../media/platform/qcom/iris/iris_platform_milos.h | 655 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + 4 files changed, 766 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 5a489917580e..c8a9f122952e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -41,6 +41,7 @@ enum pipe_type { PIPE_4 =3D 4, }; =20 +extern const struct iris_platform_data milos_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 5da90d47f9c6..1690e463c8ce 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -12,6 +12,7 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" =20 +#include "iris_platform_milos.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" @@ -1317,3 +1318,108 @@ const struct iris_platform_data qcs8300_data =3D { .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu2_ops + * - icc_tbl to milos_icc_table + * - clk_rst_tbl to sm8650_clk_reset_table + * - opp_pd_tbl to milos_opp_pd_table + * - fwname to "qcom/vpu/vpu20_p2.mbn" + * - inst_iris_fmts to platform_fmts_milos_dec + * - inst_caps to platform_inst_cap_milos + * - inst_fw_caps_dec to inst_fw_cap_milos_dec + * - inst_fw_caps_enc to inst_fw_cap_milos_enc + * - ubwc_config to ubwc_config_milos + * - num_vpp_pipe to 2 + * - max_core_mbpf scaled for 4k@30fps dec/enc + * - max_core_mbps scaled for 4k@30fps dec & 1080p@30 enc + */ +const struct iris_platform_data milos_data =3D { + .get_instance =3D iris_hfi_gen2_get_instance, + .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu2_ops, + .set_preset_registers =3D iris_set_sm8550_preset_registers, + .icc_tbl =3D milos_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(milos_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D milos_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(milos_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu20_p2.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_iris_fmts =3D platform_fmts_milos_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_milos_dec), + .inst_caps =3D &platform_inst_cap_milos, + .inst_fw_caps_dec =3D inst_fw_cap_milos_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_milos_dec), + .inst_fw_caps_enc =3D inst_fw_cap_milos_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_milos_enc), + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config =3D &ubwc_config_milos, + .num_vpp_pipe =3D 2, + .max_session_count =3D 16, + .max_core_mbpf =3D ((4096 * 2176) / 256) * 2, + .max_core_mbps =3D ((3840 * 2176) / 256) * 30 + ((1920 * 1088) / 256) * 3= 0, + .dec_input_config_params_default =3D + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc =3D + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 =3D + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_output_config_params =3D + sm8550_vdec_output_config_params, + .dec_output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params =3D + sm8550_venc_input_config_params, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params =3D + sm8550_venc_output_config_params, + .enc_output_config_params_size =3D + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + + .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_milos.h b/drive= rs/media/platform/qcom/iris/iris_platform_milos.h new file mode 100644 index 000000000000..dacd3ad5aa7e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_milos.h @@ -0,0 +1,655 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IRIS_PLATFORM_MILOS_H__ +#define __IRIS_PLATFORM_MILOS_H__ + +#define MILOS_V1_MAX_BITRATE 100000000 +#define MILOS_V1_MAX_FPS 240 + +static struct iris_fmt platform_fmts_milos_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static const struct platform_inst_fw_cap inst_fw_cap_milos_dec[] =3D { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D PROFILE_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) | + BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2), + .value =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_0, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0), + .value =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_0, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D TIER, + .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), + .value =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .hfi_id =3D HFI_PROP_TIER, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D PIPE, + /* .max, .min and .value are set via platform data */ + .step_or_mask =3D 1, + .hfi_id =3D HFI_PROP_PIPE, + .set =3D iris_set_pipe, + }, + { + .cap_id =3D POC, + .min =3D 0, + .max =3D 2, + .step_or_mask =3D 1, + .value =3D 1, + .hfi_id =3D HFI_PROP_PIC_ORDER_CNT_TYPE, + }, + { + .cap_id =3D CODED_FRAMES, + .min =3D CODED_FRAMES_PROGRESSIVE, + .max =3D CODED_FRAMES_PROGRESSIVE, + .step_or_mask =3D 0, + .value =3D CODED_FRAMES_PROGRESSIVE, + .hfi_id =3D HFI_PROP_CODED_FRAMES, + }, + { + .cap_id =3D BIT_DEPTH, + .min =3D BIT_DEPTH_8, + .max =3D BIT_DEPTH_8, + .step_or_mask =3D 1, + .value =3D BIT_DEPTH_8, + .hfi_id =3D HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + }, + { + .cap_id =3D RAP_FRAME, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + .hfi_id =3D HFI_PROP_DEC_START_FROM_RAP_FRAME, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, +}; + +static const struct platform_inst_fw_cap inst_fw_cap_milos_enc[] =3D { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_0, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_level, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_level, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D HEADER_MODE, + .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id =3D HFI_PROP_SEQ_HEADER_MODE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_header_mode_gen2, + }, + { + .cap_id =3D PREPEND_SPSPPS_TO_IDR, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + }, + { + .cap_id =3D BITRATE, + .min =3D 1, + .max =3D MILOS_V1_MAX_BITRATE, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROP_TOTAL_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate, + }, + { + .cap_id =3D BITRATE_PEAK, + .min =3D 1, + .max =3D MILOS_V1_MAX_BITRATE, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROP_TOTAL_PEAK_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_peak_bitrate, + }, + { + .cap_id =3D BITRATE_MODE, + .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id =3D HFI_PROP_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_bitrate_mode_gen2, + }, + { + .cap_id =3D FRAME_SKIP_MODE, + .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_RC_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + }, + { + .cap_id =3D GOP_SIZE, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 2 * DEFAULT_FPS - 1, + .hfi_id =3D HFI_PROP_MAX_GOP_FRAMES, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_u32, + }, + { + .cap_id =3D ENTROPY_MODE, + .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .hfi_id =3D HFI_PROP_CABAC_SESSION, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_entropy_mode_gen2, + }, + { + .cap_id =3D MIN_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_min_qp, + }, + { + .cap_id =3D MIN_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_min_qp, + }, + { + .cap_id =3D MAX_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_max_qp, + }, + { + .cap_id =3D MAX_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_max_qp, + }, + { + .cap_id =3D I_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D I_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D I_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D I_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D P_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D P_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D B_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D B_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D OUTPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D ROTATION, + .min =3D 0, + .max =3D 270, + .step_or_mask =3D 90, + .value =3D 0, + .hfi_id =3D HFI_PROP_ROTATION, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_rotation, + }, + { + .cap_id =3D HFLIP, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_FLIP, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_flip, + }, + { + .cap_id =3D VFLIP, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_FLIP, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_flip, + }, + { + .cap_id =3D IR_TYPE, + .min =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .max =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .step_or_mask =3D BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RAND= OM), + .value =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D IR_PERIOD, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 0, + .flags =3D CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_ir_period, + }, +}; + +static struct platform_inst_caps platform_inst_cap_milos =3D { + .min_frame_width =3D 96, + .max_frame_width =3D 4096, + .min_frame_height =3D 96, + .max_frame_height =3D 4096, + .max_mbpf =3D (4096 * 2176) / 256, + .mb_cycles_vpp =3D 200, + .mb_cycles_fw =3D 326389, + .mb_cycles_fw_vpp =3D 44156, + .num_comv =3D 0, + .max_frame_rate =3D MILOS_V1_MAX_FPS, + .max_operating_rate =3D MILOS_V1_MAX_FPS, +}; + +static const struct icc_info milos_icc_table[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 10000000 }, +}; + +static const char * const milos_opp_pd_table[] =3D { "cx", "mx" }; + +static struct ubwc_config_data ubwc_config_milos =3D { + .max_channels =3D 8, + .mal_length =3D 32, + .highest_bank_bit =3D 15, + .bank_swzl_level =3D 0, + .bank_swz2_level =3D 1, + .bank_swz3_level =3D 1, + .bank_spreading =3D 1, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index ddaacda523ec..ff3f4f1dc2ff 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -348,6 +348,10 @@ static const struct dev_pm_ops iris_pm_ops =3D { }; =20 static const struct of_device_id iris_dt_match[] =3D { + { + .compatible =3D "qcom,milos-iris", + .data =3D &milos_data, + }, { .compatible =3D "qcom,qcs8300-iris", .data =3D &qcs8300_data, --=20 2.53.0 From nobody Mon Jun 8 09:49:26 2026 Received: from mail-10628.protonmail.ch (mail-10628.protonmail.ch [79.135.106.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42ED34218A3 for ; Fri, 29 May 2026 20:59:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none 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Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Koskovich , Bjorn Andersson , Konrad Dybcio From: Alexander Koskovich Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 3/3] arm64: dts: qcom: milos: Add Iris VPU v2.0 Message-ID: <20260529-milos-iris-v2-3-7a763d7195ae@pm.me> In-Reply-To: <20260529-milos-iris-v2-0-7a763d7195ae@pm.me> References: <20260529-milos-iris-v2-0-7a763d7195ae@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 696512aad79ae3e982608ab11b16d10f288cd25b Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree nodes for the Iris codec (VPU 2.0) found on the Milos platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexander Koskovich --- arch/arm64/boot/dts/qcom/milos.dtsi | 85 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 4a64a98a434b..94a3c51d1d0f 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1835,6 +1836,90 @@ usb_1_dwc3_hs: endpoint { }; }; =20 + iris: video-codec@aa00000 { + compatible =3D "qcom,milos-iris"; + reg =3D <0x0 0x0aa00000 0x0 0xf0000>; + + interrupts =3D ; + + power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "venus", + "vcodec0", + "cx", + "mx"; + + operating-points-v2 =3D <&iris_opp_table>; + + clocks =3D <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names =3D "iface", + "core", + "vcodec0_core"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + memory-region =3D <&video_mem>; + + resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names =3D "bus", + "core"; + + iommus =3D <&apps_smmu 0x1960 0>, + <&apps_smmu 0x1967 0>; + + dma-coherent; + + /* + * IRIS firmware is signed by vendors, only enable on + * boards where the proper signed firmware is available. + */ + status =3D "disabled"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-552000000 { + opp-hz =3D /bits/ 64 <552000000>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + }; + }; + videocc: clock-controller@aaf0000 { compatible =3D "qcom,milos-videocc"; reg =3D <0x0 0x0aaf0000 0x0 0x10000>; --=20 2.53.0