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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304ed5a114dsm173785eec.24.2026.05.28.18.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 18:10:34 -0700 (PDT) From: Matthew Leung Date: Fri, 29 May 2026 01:10:08 +0000 Subject: [PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-hawi-pcie-v2-1-de87c6cc230c@oss.qualcomm.com> References: <20260529-hawi-pcie-v2-0-de87c6cc230c@oss.qualcomm.com> In-Reply-To: <20260529-hawi-pcie-v2-0-de87c6cc230c@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780017033; l=7308; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=T0tWgEjR4o6C8nVwFL6x+ia02fTMEN/CzOEGgDTRQSg=; b=MSL6anP9TQ5j8LCPP3jobk6toKzVCjWc01xrEuT/IoVqGVXHslR3/6bTLV5dUQM9sLwvAGFq8 RVsfCQKBeHUCjzavxmnwZC0fyn/I7Lp8Ho5xfoZ64vK2cP017ZldKzC X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Authority-Analysis: v=2.4 cv=VeXH+lp9 c=1 sm=1 tr=0 ts=6a18e78f cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=y3igNv8VU7KrM5vZpNgA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDAwOCBTYWx0ZWRfX/+iB2AjzCIvY dYYgNuMTSW+X+xUiJgj/mmqM8o8IAfNIgqT3UlLOikE2m6IfSvvGZnH57JZa4DBbZTctUXTUGSw j9bPOtnJEBGo6auaDGn/qDV2nXwAgpqrGndyfv/wX0K34/PjBsuUodYQHX3eAKpg+7Okr+Fookb yfzXWZ0rFbW1uojY6Y6yyIqymI9fNWhSApS/jsMpkWv9UQVW2MooivIauBQTlOsYDk0zwM8Xmna 24sLSuHMepGxh1ILOM9xj3bfdQJr0AP45u5pGY8heWSay9fIYBpqii2X8gB2F5kWgx3lA8LQOel UtcldVPoN2+Lki+mXnSTBUo1pMPsLIgOy3az60xiV076lydPSlia169/OWqwHOaR1gEPPF7N2WK JZCPY1n2JCgt2hq5CGjcye4MPEwvbQ== X-Proofpoint-GUID: fo8KAUWRG3oiKtkbPqDW_o7BlEnENfwn X-Proofpoint-ORIG-GUID: fo8KAUWRG3oiKtkbPqDW_o7BlEnENfwn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 suspectscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290008 Add a dedicated schema for the PCIe controllers found on the Hawi platform. Signed-off-by: Matthew Leung --- .../devicetree/bindings/pci/qcom,hawi-pcie.yaml | 204 +++++++++++++++++= ++++ 1 file changed, 204 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Do= cumentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml new file mode 100644 index 000000000000..7e47b8472af7 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hawi PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based= on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + const: qcom,hawi-pcie + + reg: + minItems: 5 + items: + - description: Qualcomm specific registers + - description: DesignWare PCIe registers + - description: External local bus interface registers + - description: ATU address space + - description: PCIe configuration space + - description: MHI registers + + reg-names: + minItems: 5 + items: + - const: parf + - const: dbi + - const: elbi + - const: atu + - const: config + - const: mhi + + clocks: + minItems: 6 + items: + - description: PCIe Auxiliary clock + - description: PCIe Configuration clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Aggre NoC AXI clock + - description: PCIe Config NoC AXI clock + + clock-names: + minItems: 6 + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: noc_aggr + - const: cnoc_sf_axi + + interrupts: + minItems: 8 + maxItems: 9 + + interrupt-names: + minItems: 8 + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: global + + resets: + minItems: 1 + items: + - description: PCIe core reset + - description: PCIe link down reset + + reset-names: + minItems: 1 + items: + - const: pci + - const: link_down + +required: + - power-domains + - resets + - reset-names + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c00000 { + compatible =3D "qcom,hawi-pcie"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100= 000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEV= EL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL= _HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL= _HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL= _HIGH>; /* int_d */ + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIV= E_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_O= NLY>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &apps_smmu 0x1000 0x1>, + <0x100 &apps_smmu 0x1001 0x1>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc GCC_PCIE_0_PHY_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", "link_down"; + + msi-map =3D <0x0 &gic_its 0x1000 0x1>, + <0x100 &gic_its 0x1001 0x1>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304ed5a114dsm173785eec.24.2026.05.28.18.10.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 18:10:34 -0700 (PDT) From: Matthew Leung Date: Fri, 29 May 2026 01:10:09 +0000 Subject: [PATCH v2 2/2] PCI: qcom: Add support for Hawi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260529-hawi-pcie-v2-2-de87c6cc230c@oss.qualcomm.com> References: <20260529-hawi-pcie-v2-0-de87c6cc230c@oss.qualcomm.com> In-Reply-To: <20260529-hawi-pcie-v2-0-de87c6cc230c@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780017033; l=919; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=SqRYyWGxDpggIYoY312hZiHBKDzS7/Y1bj/4uMnD8EA=; b=x2Mhs1h6QGe3C4hNRrzrpoZoETXQ2icHktNcZc//QGUXgaYDXCh2J0HryCQSgSeaG6TwVcjag AjHlnzlbhLMBN167zvse9emeWKy4lZdA/Veg3xo7Ms8JJvicb1ZMpOB X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Proofpoint-GUID: wLaLrPkyREvNdcPXIaOBRPL9HLyfKbll X-Proofpoint-ORIG-GUID: wLaLrPkyREvNdcPXIaOBRPL9HLyfKbll X-Authority-Analysis: v=2.4 cv=auOCzyZV c=1 sm=1 tr=0 ts=6a18e78c cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=KdxOZhL9OB_EpBcCT-QA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDAwOCBTYWx0ZWRfX3fsf6KhAVpsu 0t4zsvNyn+8nCZ8gXFT8qvl8FCeMBhg6Cy020k/4SP/cHqjibsqGYykQPl6k2MuAuCEhhRxJDNs OP19rvPkz4qI0wCm5kO6LlSfOeKnGMhqBiNEitqu8UeseIhecIqJ7diJzpOFNQOMpNTwcPqhLRz byBmnTkLlJ5LWNLWXMEu5JDnfCyNIu8iH94Lh1AYkRBl6gGEk9JEKb6shGhhqHriFqS0LpmCLon 08KoyrUXAwTQAczCUpC2YrJLhbYboDpTDHFYnkqAt1rnZrsVmhCQvWXTgCLIAGQ2icJE5dZ0Jb+ oRmEQczHfML0k2F6uoNqdV/JIuQT+2v878/ckATSSYmE6Fk8pTQwb/6RblMLyIooS8d74zxJIqM rnE1I9f/qCkrxuQaua83exgTl0qbNntbaS1NGF2DdRfrEl7SYPhe+8VXTo2gsEMUQJVB5zkmPdS RPT6e9GKjkrRFBwjmvQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290008 Add support for the Hawi platform which has two PCIe controllers: one capable of Gen3 x2 operation and one capable of Gen4 x1 operation. Signed-off-by: Matthew Leung --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 11fc60489892..5fe8667fdb8f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -2280,6 +2280,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) } =20 static const struct of_device_id qcom_pcie_match[] =3D { + { .compatible =3D "qcom,hawi-pcie", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-apq8064", .data =3D &cfg_2_1_0 }, { .compatible =3D "qcom,pcie-apq8084", .data =3D &cfg_1_0_0 }, { .compatible =3D "qcom,pcie-ipq4019", .data =3D &cfg_2_4_0 }, --=20 2.34.1