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[79.42.252.49]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-45ee2a12a69sm8625408f8f.16.2026.05.28.12.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 12:00:17 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v5 1/3] dt-bindings: clock: airoha: Document support for AN7583 clock Date: Thu, 28 May 2026 20:59:54 +0200 Message-ID: <20260528190000.9164-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260528190000.9164-1-ansuelsmth@gmail.com> References: <20260528190000.9164-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for Airoha AN7583 clock. This is based on the EN7523 clock schema with the new requirement of the "airoha,chip-scu". Add additional binding for additional clock and reset lines. Signed-off-by: Christian Marangi --- .../bindings/clock/airoha,en7523-scu.yaml | 18 ++++++ include/dt-bindings/clock/en7523-clk.h | 3 + .../dt-bindings/reset/airoha,an7583-reset.h | 62 +++++++++++++++++++ 3 files changed, 83 insertions(+) create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml= b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index eb24a5687639..6c3c88798515 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -30,6 +30,7 @@ properties: compatible: items: - enum: + - airoha,an7583-scu - airoha,en7523-scu - airoha,en7581-scu - econet,en751221-scu @@ -50,12 +51,29 @@ properties: description: ID of the controller reset line const: 1 =20 + airoha,chip-scu: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to Chip SCU + required: - compatible - reg - '#clock-cells' =20 allOf: + - if: + properties: + compatible: + const: airoha,an7583-scu + + then: + required: + - airoha,chip-scu + + else: + properties: + airoha,chip-scu: false + - if: properties: compatible: diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/c= lock/en7523-clk.h index edfa64045f52..0fbbcb7b1b25 100644 --- a/include/dt-bindings/clock/en7523-clk.h +++ b/include/dt-bindings/clock/en7523-clk.h @@ -14,4 +14,7 @@ =20 #define EN7581_CLK_EMMC 8 =20 +#define AN7583_CLK_MDIO0 9 +#define AN7583_CLK_MDIO1 10 + #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ diff --git a/include/dt-bindings/reset/airoha,an7583-reset.h b/include/dt-b= indings/reset/airoha,an7583-reset.h new file mode 100644 index 000000000000..7ff07986f8ba --- /dev/null +++ b/include/dt-bindings/reset/airoha,an7583-reset.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ + +/* RST_CTRL2 */ +#define AN7583_XPON_PHY_RST 0 +#define AN7583_GPON_OLT_RST 1 +#define AN7583_CPU_TIMER2_RST 2 +#define AN7583_HSUART_RST 3 +#define AN7583_UART4_RST 4 +#define AN7583_UART5_RST 5 +#define AN7583_I2C2_RST 6 +#define AN7583_XSI_MAC_RST 7 +#define AN7583_XSI_PHY_RST 8 +#define AN7583_NPU_RST 9 +#define AN7583_TRNG_MSTART_RST 10 +#define AN7583_DUAL_HSI0_RST 11 +#define AN7583_DUAL_HSI1_RST 12 +#define AN7583_DUAL_HSI0_MAC_RST 13 +#define AN7583_DUAL_HSI1_MAC_RST 14 +#define AN7583_XPON_XFI_RST 15 +#define AN7583_WDMA_RST 16 +#define AN7583_WOE0_RST 17 +#define AN7583_HSDMA_RST 18 +#define AN7583_TDMA_RST 19 +#define AN7583_EMMC_RST 20 +#define AN7583_SOE_RST 21 +#define AN7583_XFP_MAC_RST 22 +#define AN7583_MDIO0 23 +#define AN7583_MDIO1 24 +/* RST_CTRL1 */ +#define AN7583_PCM1_ZSI_ISI_RST 25 +#define AN7583_FE_PDMA_RST 26 +#define AN7583_FE_QDMA_RST 27 +#define AN7583_PCM_SPIWP_RST 28 +#define AN7583_CRYPTO_RST 29 +#define AN7583_TIMER_RST 30 +#define AN7583_PCM1_RST 31 +#define AN7583_UART_RST 32 +#define AN7583_GPIO_RST 33 +#define AN7583_GDMA_RST 34 +#define AN7583_I2C_MASTER_RST 35 +#define AN7583_PCM2_ZSI_ISI_RST 36 +#define AN7583_SFC_RST 37 +#define AN7583_UART2_RST 38 +#define AN7583_GDMP_RST 39 +#define AN7583_FE_RST 40 +#define AN7583_USB_HOST_P0_RST 41 +#define AN7583_GSW_RST 42 +#define AN7583_SFC2_PCM_RST 43 +#define AN7583_PCIE0_RST 44 +#define AN7583_PCIE1_RST 45 +#define AN7583_CPU_TIMER_RST 46 +#define AN7583_PCIE_HB_RST 47 +#define AN7583_XPON_MAC_RST 48 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */ --=20 2.53.0 From nobody Mon Jun 8 14:35:24 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D6BA3403E7 for ; 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[79.42.252.49]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-45ee2a12a69sm8625408f8f.16.2026.05.28.12.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 12:00:18 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v5 2/3] clk: en7523: generalize register clocks function Date: Thu, 28 May 2026 20:59:55 +0200 Message-ID: <20260528190000.9164-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260528190000.9164-1-ansuelsmth@gmail.com> References: <20260528190000.9164-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Airoha AN7583 SoC will use the same logic used by Airoha EN7581 SoC to register clocks. Generalize it to register clocks defined in soc_data. Add the clocks definition in EN7581 SoC to support this new implementation. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 1ab0e2eca5d3..087ff4568124 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -115,6 +115,7 @@ struct en_rst_data { =20 struct en_clk_soc_data { u32 num_clocks; + const struct en_clk_desc *base_clks; const struct clk_ops pcie_ops; int (*hw_init)(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data); @@ -711,12 +712,15 @@ static int en7523_clk_hw_init(struct platform_device = *pdev, static void en7581_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, struct regmap *map, void __iomem *base) { + const struct en_clk_soc_data *soc_data; struct clk_hw *hw; u32 rate; int i; =20 - for (i =3D 0; i < ARRAY_SIZE(en7581_base_clks); i++) { - const struct en_clk_desc *desc =3D &en7581_base_clks[i]; + soc_data =3D device_get_match_data(dev); + + for (i =3D 0; i < soc_data->num_clocks - 1; i++) { + const struct en_clk_desc *desc =3D &soc_data->base_clks[i]; u32 val, reg =3D desc->div_reg ? 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[79.42.252.49]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-45ee2a12a69sm8625408f8f.16.2026.05.28.12.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 12:00:21 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v5 3/3] clk: en7523: add support for Airoha AN7583 clock Date: Thu, 28 May 2026 20:59:56 +0200 Message-ID: <20260528190000.9164-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260528190000.9164-1-ansuelsmth@gmail.com> References: <20260528190000.9164-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Airoha AN7583 clock and reset. Airoha AN7583 SoC have the same register address of EN7581 but implement different bits and additional base clocks. Also reset are different with the introduction of 2 dedicated MDIO line and drop of some reset lines. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 230 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 230 insertions(+) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 087ff4568124..217d5d5f932d 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -134,6 +135,14 @@ static const u32 crypto_base[] =3D { 540000000, 480000= 000 }; static const u32 emmc7581_base[] =3D { 200000000, 150000000 }; /* EN751221 */ static const u32 gsw751221_base[] =3D { 500000000, 250000000, 400000000, 2= 00000000 }; +/* AN7583 */ +static const u32 gsw7583_base[] =3D { 540672000, 270336000, 400000000, 200= 000000 }; +static const u32 emi7583_base[] =3D { 540672000, 480000000, 400000000, 300= 000000 }; +static const u32 bus7583_base[] =3D { 600000000, 540672000, 480000000, 400= 000000 }; +static const u32 spi7583_base[] =3D { 400000000, 12500000 }; +static const u32 npu7583_base[] =3D { 666000000, 800000000, 720000000, 600= 000000 }; +static const u32 crypto7583_base[] =3D { 540672000, 400000000 }; +static const u32 emmc7583_base[] =3D { 150000000, 200000000 }; =20 static const struct en_clk_desc en7523_base_clks[] =3D { { @@ -336,6 +345,138 @@ static const struct en_clk_desc en7581_base_clks[] = =3D { } }; =20 +static const struct en_clk_desc an7583_base_clks[] =3D { + { + .id =3D EN7523_CLK_GSW, + .name =3D "gsw", + + .base_reg =3D REG_GSW_CLK_DIV_SEL, + .base_bits =3D 2, + .base_shift =3D 8, + .base_values =3D gsw7583_base, + .n_base_values =3D ARRAY_SIZE(gsw7583_base), + + .div_bits =3D 3, + .div_shift =3D 0, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D EN7523_CLK_EMI, + .name =3D "emi", + + .base_reg =3D REG_EMI_CLK_DIV_SEL, + .base_bits =3D 2, + .base_shift =3D 8, + .base_values =3D emi7583_base, + .n_base_values =3D ARRAY_SIZE(emi7583_base), + + .div_bits =3D 3, + .div_shift =3D 0, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D EN7523_CLK_BUS, + .name =3D "bus", + + .base_reg =3D REG_BUS_CLK_DIV_SEL, + .base_bits =3D 2, + .base_shift =3D 8, + .base_values =3D bus7583_base, + .n_base_values =3D ARRAY_SIZE(bus7583_base), + + .div_bits =3D 3, + .div_shift =3D 0, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D EN7523_CLK_SLIC, + .name =3D "slic", + + .base_reg =3D REG_SPI_CLK_FREQ_SEL, + .base_bits =3D 1, + .base_shift =3D 1, + .base_values =3D slic_base, + .n_base_values =3D ARRAY_SIZE(slic_base), + + .div_reg =3D REG_SPI_CLK_DIV_SEL, + .div_bits =3D 5, + .div_shift =3D 24, + .div_val0 =3D 20, + .div_step =3D 2, + }, { + .id =3D EN7523_CLK_SPI, + .name =3D "spi", + + .base_reg =3D REG_SPI_CLK_FREQ_SEL, + .base_bits =3D 1, + .base_shift =3D 0, + .base_values =3D spi7583_base, + .n_base_values =3D ARRAY_SIZE(spi7583_base), + + .div_reg =3D REG_SPI_CLK_DIV_SEL, + .div_bits =3D 5, + .div_shift =3D 8, + .div_val0 =3D 40, + .div_step =3D 2, + }, { + .id =3D EN7523_CLK_NPU, + .name =3D "npu", + + .base_reg =3D REG_NPU_CLK_DIV_SEL, + .base_bits =3D 2, + .base_shift =3D 9, + .base_values =3D npu7583_base, + .n_base_values =3D ARRAY_SIZE(npu7583_base), + + .div_bits =3D 3, + .div_shift =3D 0, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D EN7523_CLK_CRYPTO, + .name =3D "crypto", + + .base_reg =3D REG_CRYPTO_CLKSRC2, + .base_bits =3D 1, + .base_shift =3D 0, + .base_values =3D crypto7583_base, + .n_base_values =3D ARRAY_SIZE(crypto7583_base), + }, { + .id =3D EN7581_CLK_EMMC, + .name =3D "emmc", + + .base_reg =3D REG_CRYPTO_CLKSRC2, + .base_bits =3D 1, + .base_shift =3D 13, + .base_values =3D emmc7583_base, + .n_base_values =3D ARRAY_SIZE(emmc7583_base), + }, { + .id =3D AN7583_CLK_MDIO0, + .name =3D "mdio0", + + .base_reg =3D REG_CRYPTO_CLKSRC2, + + .base_value =3D 25000000, + + .div_bits =3D 4, + .div_shift =3D 15, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D AN7583_CLK_MDIO1, + .name =3D "mdio1", + + .base_reg =3D REG_CRYPTO_CLKSRC2, + + .base_value =3D 25000000, + + .div_bits =3D 4, + .div_shift =3D 19, + .div_step =3D 1, + .div_offset =3D 1, + } +}; + static const u16 en7581_rst_ofs[] =3D { REG_RST_CTRL2, REG_RST_CTRL1, @@ -505,6 +646,60 @@ static const u16 en751221_rst_map[] =3D { [EN751221_USB_PHY_P1_RST] =3D 3 * RST_NR_PER_BANK + 7, }; =20 +static const u16 an7583_rst_map[] =3D { + /* RST_CTRL2 */ + [AN7583_XPON_PHY_RST] =3D 0, + [AN7583_GPON_OLT_RST] =3D 1, + [AN7583_CPU_TIMER2_RST] =3D 2, + [AN7583_HSUART_RST] =3D 3, + [AN7583_UART4_RST] =3D 4, + [AN7583_UART5_RST] =3D 5, + [AN7583_I2C2_RST] =3D 6, + [AN7583_XSI_MAC_RST] =3D 7, + [AN7583_XSI_PHY_RST] =3D 8, + [AN7583_NPU_RST] =3D 9, + [AN7583_TRNG_MSTART_RST] =3D 12, + [AN7583_DUAL_HSI0_RST] =3D 13, + [AN7583_DUAL_HSI1_RST] =3D 14, + [AN7583_DUAL_HSI0_MAC_RST] =3D 16, + [AN7583_DUAL_HSI1_MAC_RST] =3D 17, + [AN7583_XPON_XFI_RST] =3D 18, + [AN7583_WDMA_RST] =3D 19, + [AN7583_WOE0_RST] =3D 20, + [AN7583_HSDMA_RST] =3D 22, + [AN7583_TDMA_RST] =3D 24, + [AN7583_EMMC_RST] =3D 25, + [AN7583_SOE_RST] =3D 26, + [AN7583_XFP_MAC_RST] =3D 28, + [AN7583_MDIO0] =3D 30, + [AN7583_MDIO1] =3D 31, + /* RST_CTRL1 */ + [AN7583_PCM1_ZSI_ISI_RST] =3D RST_NR_PER_BANK + 0, + [AN7583_FE_PDMA_RST] =3D RST_NR_PER_BANK + 1, + [AN7583_FE_QDMA_RST] =3D RST_NR_PER_BANK + 2, + [AN7583_PCM_SPIWP_RST] =3D RST_NR_PER_BANK + 4, + [AN7583_CRYPTO_RST] =3D RST_NR_PER_BANK + 6, + [AN7583_TIMER_RST] =3D RST_NR_PER_BANK + 8, + [AN7583_PCM1_RST] =3D RST_NR_PER_BANK + 11, + [AN7583_UART_RST] =3D RST_NR_PER_BANK + 12, + [AN7583_GPIO_RST] =3D RST_NR_PER_BANK + 13, + [AN7583_GDMA_RST] =3D RST_NR_PER_BANK + 14, + [AN7583_I2C_MASTER_RST] =3D RST_NR_PER_BANK + 16, + [AN7583_PCM2_ZSI_ISI_RST] =3D RST_NR_PER_BANK + 17, + [AN7583_SFC_RST] =3D RST_NR_PER_BANK + 18, + [AN7583_UART2_RST] =3D RST_NR_PER_BANK + 19, + [AN7583_GDMP_RST] =3D RST_NR_PER_BANK + 20, + [AN7583_FE_RST] =3D RST_NR_PER_BANK + 21, + [AN7583_USB_HOST_P0_RST] =3D RST_NR_PER_BANK + 22, + [AN7583_GSW_RST] =3D RST_NR_PER_BANK + 23, + [AN7583_SFC2_PCM_RST] =3D RST_NR_PER_BANK + 25, + [AN7583_PCIE0_RST] =3D RST_NR_PER_BANK + 26, + [AN7583_PCIE1_RST] =3D RST_NR_PER_BANK + 27, + [AN7583_CPU_TIMER_RST] =3D RST_NR_PER_BANK + 28, + [AN7583_PCIE_HB_RST] =3D RST_NR_PER_BANK + 29, + [AN7583_XPON_MAC_RST] =3D RST_NR_PER_BANK + 31, +}; + static int en7581_reset_register(struct device *dev, void __iomem *base, const u16 *rst_map, int nr_resets, const u16 *rst_reg_ofs); @@ -862,6 +1057,28 @@ static int en7581_clk_hw_init(struct platform_device = *pdev, en7581_rst_ofs); } =20 +static int an7583_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + struct device *dev =3D &pdev->dev; + struct regmap *map; + void __iomem *base; + + map =3D syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + en7581_register_clocks(dev, clk_data, map, base); + + return en7581_reset_register(dev, base, an7583_rst_map, + ARRAY_SIZE(an7583_rst_map), + en7581_rst_ofs); +} + static enum en_hir get_hw_id(void __iomem *np_base) { u32 val =3D FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR)); @@ -1006,6 +1223,18 @@ static const struct en_clk_soc_data en7581_data =3D { .hw_init =3D en7581_clk_hw_init, }; =20 +static const struct en_clk_soc_data an7583_data =3D { + .base_clks =3D an7583_base_clks, + /* We increment num_clocks by 1 to account for additional PCIe clock */ + .num_clocks =3D ARRAY_SIZE(an7583_base_clks) + 1, + .pcie_ops =3D { + .is_enabled =3D en7581_pci_is_enabled, + .enable =3D en7581_pci_enable, + .disable =3D en7581_pci_disable, + }, + .hw_init =3D an7583_clk_hw_init, +}; + static const struct en_clk_soc_data en751221_data =3D { .num_clocks =3D EN751221_MAX_CLKS, .pcie_ops =3D { @@ -1019,6 +1248,7 @@ static const struct en_clk_soc_data en751221_data =3D= { static const struct of_device_id of_match_clk_en7523[] =3D { { .compatible =3D "airoha,en7523-scu", .data =3D &en7523_data }, { .compatible =3D "airoha,en7581-scu", .data =3D &en7581_data }, + { .compatible =3D "airoha,an7583-scu", .data =3D &an7583_data }, { .compatible =3D "econet,en751221-scu", .data =3D &en751221_data }, { /* sentinel */ } }; --=20 2.53.0