From nobody Mon Jun 8 14:36:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C0AE303A37 for ; Thu, 28 May 2026 18:50:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779994241; cv=none; b=mKPGpVWPKm6rJKcsVZWASv/U3oPmdUOFguRkt27OICy9aU3IF6tUwVVpf1kjPbLPOrxlIGFwIhSKI/4HPJ57dzYFQGX6uQ2e9KCEUvutdspTi1hXdNvR07xQMiwvE/1OXSY3/9++EdQ8HTibv8KKmAwfqNlyL2Qr7764N0Tw0Hw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779994241; c=relaxed/simple; bh=b186u+L36MGLZLgAuQ/McU5X65GWLoUVVPgjIz+qg/A=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=M5LMFcyxkEqXuq4pF/3FoBkXnVKfiB52qu7k/sO6JvmplwCVLrUTheKFlX2eBK3w+zyhmFiJ+zOHG9Ol06uzy5GNjYtqhWgJNkOHqdgCcxkvvchzLyWx4jsDyme0g68vFd+RqWGxh2K4IbAQRmG5OxkvDf2znt5IUuQSSCHNBMQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bLP+Lph3; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bLP+Lph3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779994239; x=1811530239; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=b186u+L36MGLZLgAuQ/McU5X65GWLoUVVPgjIz+qg/A=; b=bLP+Lph3qIfRXcAE87ZMFXJRVQi5H4B6nyvf6OpuNbQFQxHRmLAviGeG i+WNFOCwUO6P/o9zfcLlkexhBjSEW5v3fLnvsiYH2gRSAmRsDFjbJ85rH n1hdjx7Lq6t2If94EGJ4GECBkEEW95Cy567QPrQd36m4NoWbOXW1t8Fzf J6YMIJPBIdHW6ezxSpk/HZULN6tJsu+t8WeUSSTHnHVoF7hp5xKi+W5h2 9NUZDhGTdoQmM3cOG1pnF79tSNGvGR3/Em/kFmR+k/8EpfYHRWIo7EqPP ZIz3IWdK9pAgG2rVWI9pRxHYvFtHQI41hWXNAszl7X3rDiwZ0EvFdap+d A==; X-CSE-ConnectionGUID: oU/d88zRQYeXq9iq3nvmYQ== X-CSE-MsgGUID: Iu7aID7BQO2uEvBd0hiSKg== X-IronPort-AV: E=McAfee;i="6800,10657,11800"; a="98260238" X-IronPort-AV: E=Sophos;i="6.24,174,1774335600"; d="scan'208";a="98260238" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2026 11:50:39 -0700 X-CSE-ConnectionGUID: 0GK73v9eRnSCLfxFT5CkLQ== X-CSE-MsgGUID: Mtb90UhASfizlv1Yzi/FCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,174,1774335600"; d="scan'208";a="246920331" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa004.jf.intel.com with ESMTP; 28 May 2026 11:50:38 -0700 From: Sohil Mehta To: Dave Hansen , Borislav Petkov , x86@kernel.org Cc: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Josh Poimboeuf , Richard Weinberger , Andrew Cooper , Tony Luck , Sohil Mehta , "Ahmed S . Darwish" , linux-kernel@vger.kernel.org Subject: [PATCH v4] x86/cpu: Fix a F00F bug warning and clean up surrounding code Date: Thu, 28 May 2026 11:48:25 -0700 Message-ID: <20260528184826.3642051-1-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On x86 SMP systems with the F00F bug present, the following (alternatives_patched) warning occurs for each AP: WARNING: arch/x86/kernel/cpu/cpuid-deps.c:126 at do_clear_cpu_cap+0xb4/0x= 110 Call Trace: clear_cpu_cap+0x8/0x10 init_intel+0x1b/0x4b0 identify_cpu+0x154/0x750 identify_secondary_cpu+0x3d/0x90 start_secondary+0x6b/0xf0 startup_32_smp+0x151/0x160 X86_BUG_F00F is first cleared in intel_workarounds() and then set for the affected models. This sequence works fine on the BSP but on AP bringup, where alternatives have already been patched, clearing the flag triggers the warning. There is no technical reason for clearing the flag before setting it. It is mainly an artifact of introducing the X86_BUG_F00F flag in commit e2604b49e8a8 ("x86, cpu: Convert F00F bug detection"). Remove the unnecessary clearing of the flag. While at it, remove the kernel notification and the surrounding logic to inform the user about the workaround exactly once. If needed, the presence of the F00F bug can be determined through /proc/cpuinfo. Additionally, the F00F bug was the last remaining user of clear_cpu_bug(). With no users left, get rid of this helper as well. Co-developed-by: Richard Weinberger Signed-off-by: Richard Weinberger Signed-off-by: Sohil Mehta Reviewed-by: Ahmed S. Darwish --- v4: - Combined the 3-patch series into a single patch. (Boris) v3: - Picked up Ahmed's review tag. --- arch/x86/include/asm/cpufeature.h | 1 - arch/x86/kernel/cpu/intel.c | 15 +++------------ 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index 3ddc1d33399b..90680f978d43 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -125,7 +125,6 @@ static __always_inline bool _static_cpu_has(u16 bit) =20 #define cpu_has_bug(c, bit) cpu_has(c, (bit)) #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) -#define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) =20 #define static_cpu_has_bug(bit) static_cpu_has((bit)) #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index f28c0efb7c8f..abb3984336eb 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -388,24 +388,15 @@ __setup("forcepae", forcepae_setup); =20 static void intel_workarounds(struct cpuinfo_x86 *c) { -#ifdef CONFIG_X86_F00F_BUG /* * All models of Pentium and Pentium with MMX technology CPUs * have the F0 0F bug, which lets nonprivileged users lock up the - * system. Announce that the fault handler will be checking for it. + * system. The fault handler always checks for it. * The Quark is also family 5, but does not have the same bug. */ - clear_cpu_bug(c, X86_BUG_F00F); - if (c->x86_vfm >=3D INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000) { - static int f00f_workaround_enabled; - + if (IS_ENABLED(CONFIG_X86_F00F_BUG) && + (c->x86_vfm >=3D INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000)) set_cpu_bug(c, X86_BUG_F00F); - if (!f00f_workaround_enabled) { - pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); - f00f_workaround_enabled =3D 1; - } - } -#endif =20 /* * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until --=20 2.43.0