From nobody Mon Jun 8 15:36:57 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E54A53B960B for ; Thu, 28 May 2026 11:36:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968180; cv=none; b=QP4/24JVX83D0xIcX/Q4TlpKBpI6YUlZRALhSdXNwt7xBFC9oVVePvI16JQUxmt8CmzEpWZW+eNuoYD6Cx6g69XICdHn6kQ4uEwmdpyjEpy3a8eYhgVb84r2gzuGT0WJyJeEyD6dMO+oiFK7rg5/PvoqyJu7/k0gHF8lzJaevMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968180; c=relaxed/simple; bh=1mbzqhm3jy/Z0crtDf0D8EOqHaTPu3u7Z/3xM1xXZGc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HtgCuaa//EAe7R1ZpE4LWjf9IpYpWFYYVCfvoeualMnw2M5Zc+mKphAvxQprSpGskId5JrBitBgvyh7q/VYsEqvvWtbSUmMqOAii2SXI5ABeu8nuJYUHsNyoQ78qtYU0gA/NajcfR1ZWriZobxCkBD3CAREYPw9ZdQ4yeo57fBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=n835pV6E; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=n835pV6E; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="n835pV6E"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="n835pV6E" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 448D56ADE3; Thu, 28 May 2026 11:36:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1779968177; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5DAIrNcZ6OVljSwBirP057gz50SAEW+xPSlSG6M1iNU=; b=n835pV6ENAf3ymjUFLGuV8V3YpJW0+NAEFq9RUufYC1RAqcWX7vUGnRoHug2+xiBA7qfDA cU4UR0t5qxq55wXBPvDY+X4pJ8KgY9bdXM7jY/iFyuR88Vq9CBjJF0BvW0zaYZKosfvIDk gEYPt0dkwRL81JbJ4pzCblq25L2fAhg= Authentication-Results: smtp-out1.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1779968177; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5DAIrNcZ6OVljSwBirP057gz50SAEW+xPSlSG6M1iNU=; b=n835pV6ENAf3ymjUFLGuV8V3YpJW0+NAEFq9RUufYC1RAqcWX7vUGnRoHug2+xiBA7qfDA cU4UR0t5qxq55wXBPvDY+X4pJ8KgY9bdXM7jY/iFyuR88Vq9CBjJF0BvW0zaYZKosfvIDk gEYPt0dkwRL81JbJ4pzCblq25L2fAhg= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 061445AD77; Thu, 28 May 2026 11:36:17 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id KfBsALEoGGpkSQAAD6G6ig (envelope-from ); Thu, 28 May 2026 11:36:17 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: Juergen Gross , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 1/6] KVM/x86: Change comment before KVM_MSR_RET_* defines Date: Thu, 28 May 2026 13:36:00 +0200 Message-ID: <20260528113605.267111-2-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260528113605.267111-1-jgross@suse.com> References: <20260528113605.267111-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.998]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] Content-Type: text/plain; charset="utf-8" For MSR emulation return values only 2 special cases have defines, while the most used values 0 and 1 don't. Reason seems to be the maze of function calls of MSR emulation intertwined with the KVM guest exit handlers, which are using the values 0 and 1 for other purposes. This even led to the comment above the already existing defines, warning to use the values 0 and 1 (and negative errno values) in the MSR emulation at all. Fact is that MSR emulation and exit handlers are in fact rather well distinct, with only very few exceptions which are handled in a sane way. Negative errno values and 0 are fine to be used, while the value "1" is just used for unspecific error cases. Drop the warning comment part, as it is just plainly wrong. Replace it with a statement that it is fine to use negative errno values, 0, and the special MSR emulation return values defined. Don't mention the value "1", as current cases where MSR emulation is returning "1" should be modified to return a negative errno value instead. No change of functionality intended. Signed-off-by: Juergen Gross --- V2: - instead of defining new return value macros, adapt the comment --- arch/x86/kvm/x86.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 38a905fa86de..5ca2f3d44092 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -675,8 +675,8 @@ enum kvm_msr_access { /* * Internal error codes that are used to indicate that MSR emulation encou= ntered * an error that should result in #GP in the guest, unless userspace handl= es it. - * Note, '1', '0', and negative numbers are off limits, as they are used b= y KVM - * as part of KVM's lightly documented internal KVM_RUN return codes. + * Other than these internal error codes negative errno values can be used= for + * error cases, or 0 for success. * * UNSUPPORTED - The MSR isn't supported, either because it is completely * unknown to KVM, or because the MSR should not exist according --=20 2.54.0 From nobody Mon Jun 8 15:36:57 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD5013E120D for ; Thu, 28 May 2026 11:36:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968188; cv=none; b=Dm7bR0e+tzZmkzIh2IT1upxjQYAsSLmBcdlDUuWyO1gQ3mdtmIM8UG4pO1AWgIPDhM6n+zDe52Uuj0CHoo40GiZTMXabBBDtrvmH3JO0zIdwAIsN0nva+mYMRsTaz+tzHNX1hnSm36u3HdAVDDj5LtkWMQBoDz3zOJXXTYBC80s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968188; c=relaxed/simple; bh=c/BRJrvMgUknobRNXd28o9C5+IkXCI0PYo28UU2pMjQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gqVSGQyabTkd4IfMPG9jOldBlEm3RALF2H1ekohiXY8A+hMUBdvcPds+pIhJ05d+YZNtXd/Smp+eOE/LXq/VxK8plbwkbvaalH0XLIzdnOa4FBCf3fiLsGiD9EW6m1Cb3ZI9XEsnQP8suHNXnm00UXVEY7NYEO3NohJEtTmQiwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id D10946AE3A; Thu, 28 May 2026 11:36:22 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 904CD5AD77; Thu, 28 May 2026 11:36:22 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id /yQuIrYoGGpqSQAAD6G6ig (envelope-from ); Thu, 28 May 2026 11:36:22 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: Juergen Gross , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 2/6] KVM/x86: Return -errno instead of "1" for APIC related MSR emulation Date: Thu, 28 May 2026 13:36:01 +0200 Message-ID: <20260528113605.267111-3-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260528113605.267111-1-jgross@suse.com> References: <20260528113605.267111-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: D10946AE3A X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Rspamd-Action: no action X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spam-Score: -4.00 X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" Instead of a literal "1" for signalling an error, use a negative errno value in the emulation code of APIC related MSR registers. Remove some not needed braces. Signed-off-by: Juergen Gross --- V2: - use -errno instead of KVM_MSR_RET_ERR --- arch/x86/kvm/lapic.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4078e624ca66..3e7d83db2f7a 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2412,11 +2412,10 @@ static int kvm_lapic_reg_write(struct kvm_lapic *ap= ic, u32 reg, u32 val) =20 switch (reg) { case APIC_ID: /* Local APIC ID */ - if (!apic_x2apic_mode(apic)) { + if (!apic_x2apic_mode(apic)) kvm_apic_set_xapic_id(apic, val >> 24); - } else { - ret =3D 1; - } + else + ret =3D -EINVAL; break; =20 case APIC_TASKPRI: @@ -2432,14 +2431,14 @@ static int kvm_lapic_reg_write(struct kvm_lapic *ap= ic, u32 reg, u32 val) if (!apic_x2apic_mode(apic)) kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); else - ret =3D 1; + ret =3D -EINVAL; break; =20 case APIC_DFR: if (!apic_x2apic_mode(apic)) kvm_apic_set_dfr(apic, val | 0x0FFFFFFF); else - ret =3D 1; + ret =3D -EINVAL; break; =20 case APIC_SPIV: { @@ -2470,7 +2469,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic= , u32 reg, u32 val) break; case APIC_ICR2: if (apic_x2apic_mode(apic)) - ret =3D 1; + ret =3D -EINVAL; else kvm_lapic_set_reg(apic, APIC_ICR2, val & 0xff000000); break; @@ -2485,7 +2484,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic= , u32 reg, u32 val) case APIC_LVTCMCI: { u32 index =3D get_lvt_index(reg); if (!kvm_lapic_lvt_supported(apic, index)) { - ret =3D 1; + ret =3D -EINVAL; break; } if (!kvm_apic_sw_enabled(apic)) @@ -2527,7 +2526,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic= , u32 reg, u32 val) } case APIC_ESR: if (apic_x2apic_mode(apic) && val !=3D 0) - ret =3D 1; + ret =3D -EINVAL; break; =20 case APIC_SELF_IPI: @@ -2536,12 +2535,12 @@ static int kvm_lapic_reg_write(struct kvm_lapic *ap= ic, u32 reg, u32 val) * the vector, everything else is reserved. */ if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK)) - ret =3D 1; + ret =3D -EINVAL; else kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0); break; default: - ret =3D 1; + ret =3D -EINVAL; break; } =20 @@ -2599,7 +2598,7 @@ EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_lapic_set_eoi); static int __kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data, bool f= ast) { if (data & X2APIC_ICR_RESERVED_BITS) - return 1; + return -EINVAL; =20 /* * The BUSY bit is reserved on both Intel and AMD in x2APIC mode, but @@ -2804,12 +2803,12 @@ int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 va= lue, bool host_initiated) (guest_cpu_cap_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); =20 if ((value & reserved_bits) !=3D 0 || new_mode =3D=3D LAPIC_MODE_INVALID) - return 1; + return -EINVAL; if (!host_initiated) { if (old_mode =3D=3D LAPIC_MODE_X2APIC && new_mode =3D=3D LAPIC_MODE_XAPI= C) return 1; if (old_mode =3D=3D LAPIC_MODE_DISABLED && new_mode =3D=3D LAPIC_MODE_X2= APIC) - return 1; + return -EINVAL; } =20 __kvm_apic_set_base(vcpu, value); @@ -3438,7 +3437,7 @@ static int kvm_lapic_msr_read(struct kvm_lapic *apic,= u32 reg, u64 *data) } =20 if (kvm_lapic_reg_read(apic, reg, 4, &low)) - return 1; + return -EINVAL; =20 *data =3D low; =20 @@ -3457,7 +3456,7 @@ static int kvm_lapic_msr_write(struct kvm_lapic *apic= , u32 reg, u64 data) =20 /* Bits 63:32 are reserved in all other registers. */ if (data >> 32) - return 1; + return -EINVAL; =20 return kvm_lapic_reg_write(apic, reg, (u32)data); } @@ -3468,7 +3467,7 @@ int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 m= sr, u64 data) u32 reg =3D (msr - APIC_BASE_MSR) << 4; =20 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) - return 1; + return -EINVAL; =20 return kvm_lapic_msr_write(apic, reg, data); } @@ -3479,7 +3478,7 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 ms= r, u64 *data) u32 reg =3D (msr - APIC_BASE_MSR) << 4; =20 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) - return 1; + return -EINVAL; =20 return kvm_lapic_msr_read(apic, reg, data); } @@ -3487,7 +3486,7 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 ms= r, u64 *data) int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) { if (!lapic_in_kernel(vcpu)) - return 1; + return -EINVAL; =20 return kvm_lapic_msr_write(vcpu->arch.apic, reg, data); } @@ -3495,7 +3494,7 @@ int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32= reg, u64 data) int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) { if (!lapic_in_kernel(vcpu)) - return 1; + return -EINVAL; =20 return kvm_lapic_msr_read(vcpu->arch.apic, reg, data); } --=20 2.54.0 From nobody Mon Jun 8 15:36:57 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BCE93E7BDF for ; Thu, 28 May 2026 11:36:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968194; cv=none; b=MyPVu28WI5Cr0qLJvc1I6i0DTqDQd86k55IeCpLPyc0Qlh5qTAhIaz7693h/hfqtaFQTb3MKcQPNkZDcBaMsEr5P5C07zGsGilVTsRKPP39PUOOt/JTuv24ecLJZ/9kJM8cTQw94C/LIKm3Ej0ZWNSL1/uwBJyxGcDBhSpkL6/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968194; c=relaxed/simple; bh=gttg+5qAZWEFQqYHVSIcofNzP8HUzFyz3hUN7CUc1Sw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ueg7yUeDnYLmYOTFiF+i5yCCf9jzT/4VzaKgG7DfJp5oboo1wxLM5Pze+Ui3MXTdMut1B48OemWc9QhSoy2/OK8xhD7I5CkST4MsoRa18d13Ul2dMEtjA74fT1T28CLNTARP+WOe63RNIiAra50GVjwnamU2S7sNspKsSICjd8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 6E00B6AE8D; Thu, 28 May 2026 11:36:28 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 27F205AD77; Thu, 28 May 2026 11:36:28 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id fAymCLwoGGp/SQAAD6G6ig (envelope-from ); Thu, 28 May 2026 11:36:28 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: Juergen Gross , Vitaly Kuznetsov , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 3/6] KVM/x86: Return -errno instead of "1" for Hyper-V related MSR emulation Date: Thu, 28 May 2026 13:36:02 +0200 Message-ID: <20260528113605.267111-4-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260528113605.267111-1-jgross@suse.com> References: <20260528113605.267111-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 6E00B6AE8D X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" Instead of a literal "1" for signalling an error, use a negative errno value in the emulation code of Hyper-V related MSR registers. Signed-off-by: Juergen Gross --- V2: - use -errno instead of KVM_MSR_RET_ERR --- arch/x86/kvm/hyperv.c | 72 +++++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c index 4438ecac9a89..809752a6d0ac 100644 --- a/arch/x86/kvm/hyperv.c +++ b/arch/x86/kvm/hyperv.c @@ -167,7 +167,7 @@ static int synic_set_sint(struct kvm_vcpu_hv_synic *syn= ic, int sint, * allow zero-initing the register from host as well. */ if (vector < HV_SYNIC_FIRST_VALID_VECTOR && !host && !masked) - return 1; + return -EINVAL; /* * Guest may configure multiple SINTs to use the same vector, so * we maintain a bitmap of vectors handled by synic, and a @@ -263,7 +263,7 @@ static int synic_set_msr(struct kvm_vcpu_hv_synic *syni= c, int ret; =20 if (!synic->active && (!host || data)) - return 1; + return -EINVAL; =20 trace_kvm_hv_synic_set_msr(vcpu->vcpu_id, msr, data, host); =20 @@ -276,7 +276,7 @@ static int synic_set_msr(struct kvm_vcpu_hv_synic *syni= c, break; case HV_X64_MSR_SVERSION: if (!host) { - ret =3D 1; + ret =3D -EINVAL; break; } synic->version =3D data; @@ -286,7 +286,7 @@ static int synic_set_msr(struct kvm_vcpu_hv_synic *syni= c, !synic->dont_zero_synic_pages) if (kvm_clear_guest(vcpu->kvm, data & PAGE_MASK, PAGE_SIZE)) { - ret =3D 1; + ret =3D -EFAULT; break; } synic->evt_page =3D data; @@ -298,7 +298,7 @@ static int synic_set_msr(struct kvm_vcpu_hv_synic *syni= c, !synic->dont_zero_synic_pages) if (kvm_clear_guest(vcpu->kvm, data & PAGE_MASK, PAGE_SIZE)) { - ret =3D 1; + ret =3D -EFAULT; break; } synic->msg_page =3D data; @@ -319,7 +319,7 @@ static int synic_set_msr(struct kvm_vcpu_hv_synic *syni= c, ret =3D synic_set_sint(synic, msr - HV_X64_MSR_SINT0, data, host); break; default: - ret =3D 1; + ret =3D -EINVAL; break; } return ret; @@ -365,7 +365,7 @@ static int syndbg_set_msr(struct kvm_vcpu *vcpu, u32 ms= r, u64 data, bool host) struct kvm_hv_syndbg *syndbg =3D to_hv_syndbg(vcpu); =20 if (!kvm_hv_is_syndbg_enabled(vcpu) && !host) - return 1; + return -EINVAL; =20 trace_kvm_hv_syndbg_set_msr(vcpu->vcpu_id, to_hv_vcpu(vcpu)->vp_index, msr, data); @@ -404,7 +404,7 @@ static int syndbg_get_msr(struct kvm_vcpu *vcpu, u32 ms= r, u64 *pdata, bool host) struct kvm_hv_syndbg *syndbg =3D to_hv_syndbg(vcpu); =20 if (!kvm_hv_is_syndbg_enabled(vcpu) && !host) - return 1; + return -EINVAL; =20 switch (msr) { case HV_X64_MSR_SYNDBG_CONTROL: @@ -440,7 +440,7 @@ static int synic_get_msr(struct kvm_vcpu_hv_synic *syni= c, u32 msr, u64 *pdata, int ret; =20 if (!synic->active && !host) - return 1; + return -EINVAL; =20 ret =3D 0; switch (msr) { @@ -463,7 +463,7 @@ static int synic_get_msr(struct kvm_vcpu_hv_synic *syni= c, u32 msr, u64 *pdata, *pdata =3D atomic64_read(&synic->sint[msr - HV_X64_MSR_SINT0]); break; default: - ret =3D 1; + ret =3D -EINVAL; break; } return ret; @@ -695,12 +695,12 @@ static int stimer_set_config(struct kvm_vcpu_hv_stime= r *stimer, u64 config, struct kvm_vcpu_hv_synic *synic =3D to_hv_synic(vcpu); =20 if (!synic->active && (!host || config)) - return 1; + return -EINVAL; =20 if (unlikely(!host && hv_vcpu->enforce_cpuid && new_config.direct_mode && !(hv_vcpu->cpuid_cache.features_edx & HV_STIMER_DIRECT_MODE_AVAILABLE))) - return 1; + return -EINVAL; =20 trace_kvm_hv_stimer_set_config(hv_stimer_to_vcpu(stimer)->vcpu_id, stimer->index, config, host); @@ -724,7 +724,7 @@ static int stimer_set_count(struct kvm_vcpu_hv_stimer *= stimer, u64 count, struct kvm_vcpu_hv_synic *synic =3D to_hv_synic(vcpu); =20 if (!synic->active && (!host || count)) - return 1; + return -EINVAL; =20 trace_kvm_hv_stimer_set_count(hv_stimer_to_vcpu(stimer)->vcpu_id, stimer->index, count, host); @@ -1380,7 +1380,7 @@ static int kvm_hv_set_msr_pw(struct kvm_vcpu *vcpu, u= 32 msr, u64 data, struct kvm_hv *hv =3D to_kvm_hv(kvm); =20 if (unlikely(!host && !hv_check_msr_access(to_hv_vcpu(vcpu), msr))) - return 1; + return -EINVAL; =20 switch (msr) { case HV_X64_MSR_GUEST_OS_ID: @@ -1476,23 +1476,23 @@ static int kvm_hv_set_msr_pw(struct kvm_vcpu *vcpu,= u32 msr, u64 data, break; case HV_X64_MSR_TSC_EMULATION_STATUS: if (data && !host) - return 1; + return -EINVAL; =20 hv->hv_tsc_emulation_status =3D data; break; case HV_X64_MSR_TIME_REF_COUNT: /* read-only, but still ignore it if host-initiated */ if (!host) - return 1; + return -EINVAL; break; case HV_X64_MSR_TSC_INVARIANT_CONTROL: /* Only bit 0 is supported */ if (data & ~HV_EXPOSE_INVARIANT_TSC) - return 1; + return -EINVAL; =20 /* The feature can't be disabled from the guest */ if (!host && hv->hv_invtsc_control && !data) - return 1; + return -EINVAL; =20 hv->hv_invtsc_control =3D data; break; @@ -1501,7 +1501,7 @@ static int kvm_hv_set_msr_pw(struct kvm_vcpu *vcpu, u= 32 msr, u64 data, return syndbg_set_msr(vcpu, msr, data, host); default: kvm_pr_unimpl_wrmsr(vcpu, msr, data); - return 1; + return -EINVAL; } return 0; } @@ -1521,7 +1521,7 @@ static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u32 = msr, u64 data, bool host) struct kvm_vcpu_hv *hv_vcpu =3D to_hv_vcpu(vcpu); =20 if (unlikely(!host && !hv_check_msr_access(hv_vcpu, msr))) - return 1; + return -EINVAL; =20 switch (msr) { case HV_X64_MSR_VP_INDEX: { @@ -1529,7 +1529,7 @@ static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u32 = msr, u64 data, bool host) u32 new_vp_index =3D (u32)data; =20 if (!host || new_vp_index >=3D KVM_MAX_VCPUS) - return 1; + return -EINVAL; =20 if (new_vp_index =3D=3D hv_vcpu->vp_index) return 0; @@ -1555,13 +1555,13 @@ static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u3= 2 msr, u64 data, bool host) if (!(data & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE)) { hv_vcpu->hv_vapic =3D data; if (kvm_lapic_set_pv_eoi(vcpu, 0, 0)) - return 1; + return -EINVAL; break; } gfn =3D data >> HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT; addr =3D kvm_vcpu_gfn_to_hva(vcpu, gfn); if (kvm_is_error_hva(addr)) - return 1; + return -EINVAL; =20 /* * Clear apic_assist portion of struct hv_vp_assist_page @@ -1569,13 +1569,13 @@ static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u3= 2 msr, u64 data, bool host) * to be preserved e.g. on migration. */ if (put_user(0, (u32 __user *)addr)) - return 1; + return -EFAULT; hv_vcpu->hv_vapic =3D data; kvm_vcpu_mark_page_dirty(vcpu, gfn); if (kvm_lapic_set_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED, sizeof(struct hv_vp_assist_page))) - return 1; + return -EINVAL; break; } case HV_X64_MSR_EOI: @@ -1586,7 +1586,7 @@ static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u32 = msr, u64 data, bool host) return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); case HV_X64_MSR_VP_RUNTIME: if (!host) - return 1; + return -EINVAL; hv_vcpu->runtime_offset =3D data - current_task_runtime_100ns(); break; case HV_X64_MSR_SCONTROL: @@ -1618,11 +1618,11 @@ static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u3= 2 msr, u64 data, bool host) case HV_X64_MSR_APIC_FREQUENCY: /* read-only, but still ignore it if host-initiated */ if (!host) - return 1; + return -EINVAL; break; default: kvm_pr_unimpl_wrmsr(vcpu, msr, data); - return 1; + return -EINVAL; } =20 return 0; @@ -1636,7 +1636,7 @@ static int kvm_hv_get_msr_pw(struct kvm_vcpu *vcpu, u= 32 msr, u64 *pdata, struct kvm_hv *hv =3D to_kvm_hv(kvm); =20 if (unlikely(!host && !hv_check_msr_access(to_hv_vcpu(vcpu), msr))) - return 1; + return -EINVAL; =20 switch (msr) { case HV_X64_MSR_GUEST_OS_ID: @@ -1677,7 +1677,7 @@ static int kvm_hv_get_msr_pw(struct kvm_vcpu *vcpu, u= 32 msr, u64 *pdata, return syndbg_get_msr(vcpu, msr, pdata, host); default: kvm_pr_unimpl_rdmsr(vcpu, msr); - return 1; + return -EINVAL; } =20 *pdata =3D data; @@ -1691,7 +1691,7 @@ static int kvm_hv_get_msr(struct kvm_vcpu *vcpu, u32 = msr, u64 *pdata, struct kvm_vcpu_hv *hv_vcpu =3D to_hv_vcpu(vcpu); =20 if (unlikely(!host && !hv_check_msr_access(hv_vcpu, msr))) - return 1; + return -EINVAL; =20 switch (msr) { case HV_X64_MSR_VP_INDEX: @@ -1743,7 +1743,7 @@ static int kvm_hv_get_msr(struct kvm_vcpu *vcpu, u32 = msr, u64 *pdata, break; default: kvm_pr_unimpl_rdmsr(vcpu, msr); - return 1; + return -EINVAL; } *pdata =3D data; return 0; @@ -1754,10 +1754,10 @@ int kvm_hv_set_msr_common(struct kvm_vcpu *vcpu, u3= 2 msr, u64 data, bool host) struct kvm_hv *hv =3D to_kvm_hv(vcpu->kvm); =20 if (!host && !vcpu->arch.hyperv_enabled) - return 1; + return -EINVAL; =20 if (kvm_hv_vcpu_init(vcpu)) - return 1; + return -EINVAL; =20 if (kvm_hv_msr_partition_wide(msr)) { int r; @@ -1775,10 +1775,10 @@ int kvm_hv_get_msr_common(struct kvm_vcpu *vcpu, u3= 2 msr, u64 *pdata, bool host) struct kvm_hv *hv =3D to_kvm_hv(vcpu->kvm); =20 if (!host && !vcpu->arch.hyperv_enabled) - return 1; + return -EINVAL; =20 if (kvm_hv_vcpu_init(vcpu)) - return 1; + return -EINVAL; =20 if (kvm_hv_msr_partition_wide(msr)) { int r; --=20 2.54.0 From nobody Mon Jun 8 15:36:57 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFEDC3E51C7 for ; Thu, 28 May 2026 11:36:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968200; cv=none; b=OTyJC712gj7HwQS9XV17v5Skow0N3q/KZ1cUVI5Bioq0sBDZ3wSDK2KXdZ7pFnXevwIBB9emBC93NREeWI3uBm3D6ZjQR3P/u7G7Ztty1zJ3WW6KehahwNZ5KouHwm03zaXiRaUrkP0G831OchXcL3o6WADfdBZ+3ytO9rSph1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968200; c=relaxed/simple; bh=m9d+7c85/6AA7n1Y3SufmsyrJZT30Ju59L4xiYM0eEA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bBl97YNDLrOJAXo6CJTezWXEIABUs8goLclrnrelm0xqbMFwieE/jcmDm5lSVg/B5HJJzpYyGOF8H8P9+TBBIbVP4ZlfhSwTSw4YGY1ui9sMhSKj9HTAskc8Mf9IkqMDNxsNd9XEp7F57SiA54wZGVnYtJgWHgmH/lNVx2Gt8fw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 117BC6ADE3; Thu, 28 May 2026 11:36:34 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id B7AE45AD79; Thu, 28 May 2026 11:36:33 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id OfWFK8EoGGqvSQAAD6G6ig (envelope-from ); Thu, 28 May 2026 11:36:33 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org, linux-coco@lists.linux.dev Cc: Juergen Gross , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe Subject: [PATCH v2 4/6] KVM/x86: Return -errno instead of "1" for VMX related MSR emulation Date: Thu, 28 May 2026 13:36:03 +0200 Message-ID: <20260528113605.267111-5-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260528113605.267111-1-jgross@suse.com> References: <20260528113605.267111-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 117BC6ADE3 X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" Instead of a literal "1" for signalling an error, use a negative errno value in the emulation code of VMX related MSR registers. Signed-off-by: Juergen Gross --- V2: - use -errno instead of KVM_MSR_RET_ERR --- arch/x86/kvm/vmx/nested.c | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 16 +++--- arch/x86/kvm/vmx/tdx.c | 10 ++-- arch/x86/kvm/vmx/vmx.c | 96 ++++++++++++++++++------------------ 4 files changed, 62 insertions(+), 62 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 3fe88f29be7a..2236f15ffab2 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -1611,7 +1611,7 @@ int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32= msr_index, u64 *pdata) *pdata =3D msrs->vmfunc_controls; break; default: - return 1; + return -EINVAL; } =20 return 0; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 27eb76e6b6a0..4f7e354c4b50 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -362,7 +362,7 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, true)) { break; } - return 1; + return -EINVAL; } =20 return 0; @@ -379,14 +379,14 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, s= truct msr_data *msr_info) switch (msr) { case MSR_CORE_PERF_FIXED_CTR_CTRL: if (data & pmu->fixed_ctr_ctrl_rsvd) - return 1; + return -EINVAL; =20 if (pmu->fixed_ctr_ctrl !=3D data) reprogram_fixed_counters(pmu, data); break; case MSR_IA32_PEBS_ENABLE: if (data & pmu->pebs_enable_rsvd) - return 1; + return -EINVAL; =20 if (pmu->pebs_enable !=3D data) { diff =3D pmu->pebs_enable ^ data; @@ -396,13 +396,13 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, s= truct msr_data *msr_info) break; case MSR_IA32_DS_AREA: if (is_noncanonical_msr_address(data, vcpu)) - return 1; + return -EINVAL; =20 pmu->ds_area =3D data; break; case MSR_PEBS_DATA_CFG: if (data & pmu->pebs_data_cfg_rsvd) - return 1; + return -EINVAL; =20 pmu->pebs_data_cfg =3D data; break; @@ -411,7 +411,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) (pmc =3D get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { if ((msr & MSR_PMC_FULL_WIDTH_BIT) && (data & ~pmu->counter_bitmask[KVM_PMC_GP])) - return 1; + return -EINVAL; =20 if (!msr_info->host_initiated && !(msr & MSR_PMC_FULL_WIDTH_BIT)) @@ -427,7 +427,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED)) reserved_bits ^=3D HSW_IN_TX_CHECKPOINTED; if (data & reserved_bits) - return 1; + return -EINVAL; =20 if (data !=3D pmc->eventsel) { pmc->eventsel =3D data; @@ -439,7 +439,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) break; } /* Not a known PMU MSR. */ - return 1; + return -EINVAL; } =20 return 0; diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 04ce321ebdf3..acc3242af4f4 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -2158,12 +2158,12 @@ int tdx_get_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr) return 0; case MSR_IA32_MCG_EXT_CTL: if (!msr->host_initiated && !(vcpu->arch.mcg_cap & MCG_LMCE_P)) - return 1; + return -EINVAL; msr->data =3D vcpu->arch.mcg_ext_ctl; return 0; default: if (!tdx_has_emulated_msr(msr->index)) - return 1; + return -EACCES; =20 return kvm_get_msr_common(vcpu, msr); } @@ -2175,15 +2175,15 @@ int tdx_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr) case MSR_IA32_MCG_EXT_CTL: if ((!msr->host_initiated && !(vcpu->arch.mcg_cap & MCG_LMCE_P)) || (msr->data & ~MCG_EXT_CTL_LMCE_EN)) - return 1; + return -EINVAL; vcpu->arch.mcg_ext_ctl =3D msr->data; return 0; default: if (tdx_is_read_only_msr(msr->index)) - return 1; + return -EACCES; =20 if (!tdx_has_emulated_msr(msr->index)) - return 1; + return -EACCES; =20 return kvm_set_msr_common(vcpu, msr); } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b9103de01428..2eee599fca30 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2076,7 +2076,7 @@ int vmx_get_feature_msr(u32 msr, u64 *data) switch (msr) { case KVM_FIRST_EMULATED_VMX_MSR ... KVM_LAST_EMULATED_VMX_MSR: if (!nested) - return 1; + return -EINVAL; return vmx_get_vmx_msr(&vmcs_config.nested, msr, data); default: return KVM_MSR_RET_UNSUPPORTED; @@ -2111,18 +2111,18 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) case MSR_IA32_TSX_CTRL: if (!msr_info->host_initiated && !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) - return 1; + return -EINVAL; goto find_uret_msr; case MSR_IA32_UMWAIT_CONTROL: if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) - return 1; + return -EINVAL; =20 msr_info->data =3D vmx->msr_ia32_umwait_control; break; case MSR_IA32_SPEC_CTRL: if (!msr_info->host_initiated && !guest_has_spec_ctrl_msr(vcpu)) - return 1; + return -EINVAL; =20 msr_info->data =3D to_vmx(vcpu)->spec_ctrl; break; @@ -2139,14 +2139,14 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) if (!kvm_mpx_supported() || (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_MPX))) - return 1; + return -EINVAL; msr_info->data =3D vmcs_read64(GUEST_BNDCFGS); break; case MSR_IA32_MCG_EXT_CTL: if (!msr_info->host_initiated && !(vmx->msr_ia32_feature_control & FEAT_CTL_LMCE_ENABLED)) - return 1; + return -EINVAL; msr_info->data =3D vcpu->arch.mcg_ext_ctl; break; case MSR_IA32_FEAT_CTL: @@ -2155,16 +2155,16 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_SGX_LC)) - return 1; + return -EINVAL; msr_info->data =3D to_vmx(vcpu)->msr_ia32_sgxlepubkeyhash [msr_info->index - MSR_IA32_SGXLEPUBKEYHASH0]; break; case KVM_FIRST_EMULATED_VMX_MSR ... KVM_LAST_EMULATED_VMX_MSR: if (!guest_cpu_cap_has(vcpu, X86_FEATURE_VMX)) - return 1; + return -EINVAL; if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, &msr_info->data)) - return 1; + return -EINVAL; #ifdef CONFIG_KVM_HYPERV /* * Enlightened VMCS v1 doesn't have certain VMCS fields but @@ -2180,19 +2180,19 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) break; case MSR_IA32_RTIT_CTL: if (!vmx_pt_mode_is_host_guest()) - return 1; + return -EINVAL; msr_info->data =3D vmx->pt_desc.guest.ctl; break; case MSR_IA32_RTIT_STATUS: if (!vmx_pt_mode_is_host_guest()) - return 1; + return -EINVAL; msr_info->data =3D vmx->pt_desc.guest.status; break; case MSR_IA32_RTIT_CR3_MATCH: if (!vmx_pt_mode_is_host_guest() || !intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) - return 1; + return -EINVAL; msr_info->data =3D vmx->pt_desc.guest.cr3_match; break; case MSR_IA32_RTIT_OUTPUT_BASE: @@ -2201,7 +2201,7 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_dat= a *msr_info) PT_CAP_topa_output) && !intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_single_range_output))) - return 1; + return -EINVAL; msr_info->data =3D vmx->pt_desc.guest.output_base; break; case MSR_IA32_RTIT_OUTPUT_MASK: @@ -2210,14 +2210,14 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) PT_CAP_topa_output) && !intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_single_range_output))) - return 1; + return -EINVAL; msr_info->data =3D vmx->pt_desc.guest.output_mask; break; case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: index =3D msr_info->index - MSR_IA32_RTIT_ADDR0_A; if (!vmx_pt_mode_is_host_guest() || (index >=3D 2 * vmx->pt_desc.num_address_ranges)) - return 1; + return -EINVAL; if (index % 2) msr_info->data =3D vmx->pt_desc.guest.addr_b[index / 2]; else @@ -2359,7 +2359,7 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_dat= a *msr_info) break; case MSR_IA32_DEBUGCTLMSR: if (!vmx_is_valid_debugctl(vcpu, data, msr_info->host_initiated)) - return 1; + return -EINVAL; =20 data &=3D vmx_get_supported_debugctl(vcpu, msr_info->host_initiated); =20 @@ -2377,10 +2377,10 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) if (!kvm_mpx_supported() || (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_MPX))) - return 1; + return -EINVAL; if (is_noncanonical_msr_address(data & PAGE_MASK, vcpu) || (data & MSR_IA32_BNDCFGS_RSVD)) - return 1; + return -EINVAL; =20 if (is_guest_mode(vcpu) && ((vmx->nested.msrs.entry_ctls_high & VM_ENTRY_LOAD_BNDCFGS) || @@ -2391,21 +2391,21 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) break; case MSR_IA32_UMWAIT_CONTROL: if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) - return 1; + return -EINVAL; =20 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) - return 1; + return -EINVAL; =20 vmx->msr_ia32_umwait_control =3D data; break; case MSR_IA32_SPEC_CTRL: if (!msr_info->host_initiated && !guest_has_spec_ctrl_msr(vcpu)) - return 1; + return -EINVAL; =20 if (kvm_spec_ctrl_test_value(data)) - return 1; + return -EINVAL; =20 vmx->spec_ctrl =3D data; if (!data) @@ -2430,9 +2430,9 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_dat= a *msr_info) case MSR_IA32_TSX_CTRL: if (!msr_info->host_initiated && !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) - return 1; + return -EINVAL; if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) - return 1; + return -EINVAL; goto find_uret_msr; case MSR_IA32_CR_PAT: ret =3D kvm_set_msr_common(vcpu, msr_info); @@ -2451,12 +2451,12 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) !(to_vmx(vcpu)->msr_ia32_feature_control & FEAT_CTL_LMCE_ENABLED)) || (data & ~MCG_EXT_CTL_LMCE_EN)) - return 1; + return -EINVAL; vcpu->arch.mcg_ext_ctl =3D data; break; case MSR_IA32_FEAT_CTL: if (!is_vmx_feature_control_msr_valid(vmx, msr_info)) - return 1; + return -EINVAL; =20 vmx->msr_ia32_feature_control =3D data; if (msr_info->host_initiated && data =3D=3D 0) @@ -2481,70 +2481,70 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) (!guest_cpu_cap_has(vcpu, X86_FEATURE_SGX_LC) || ((vmx->msr_ia32_feature_control & FEAT_CTL_LOCKED) && !(vmx->msr_ia32_feature_control & FEAT_CTL_SGX_LC_ENABLED)))) - return 1; + return -EINVAL; vmx->msr_ia32_sgxlepubkeyhash [msr_index - MSR_IA32_SGXLEPUBKEYHASH0] =3D data; break; case KVM_FIRST_EMULATED_VMX_MSR ... KVM_LAST_EMULATED_VMX_MSR: if (!msr_info->host_initiated) - return 1; /* they are read-only */ + return -EINVAL; /* they are read-only */ if (!guest_cpu_cap_has(vcpu, X86_FEATURE_VMX)) - return 1; + return -EINVAL; return vmx_set_vmx_msr(vcpu, msr_index, data); case MSR_IA32_RTIT_CTL: if (!vmx_pt_mode_is_host_guest() || vmx_rtit_ctl_check(vcpu, data) || vmx->nested.vmxon) - return 1; + return -EINVAL; vmcs_write64(GUEST_IA32_RTIT_CTL, data); vmx->pt_desc.guest.ctl =3D data; pt_update_intercept_for_msr(vcpu); break; case MSR_IA32_RTIT_STATUS: if (!pt_can_write_msr(vmx)) - return 1; + return -EINVAL; if (data & MSR_IA32_RTIT_STATUS_MASK) - return 1; + return -EINVAL; vmx->pt_desc.guest.status =3D data; break; case MSR_IA32_RTIT_CR3_MATCH: if (!pt_can_write_msr(vmx)) - return 1; + return -EINVAL; if (!intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) - return 1; + return -EINVAL; vmx->pt_desc.guest.cr3_match =3D data; break; case MSR_IA32_RTIT_OUTPUT_BASE: if (!pt_can_write_msr(vmx)) - return 1; + return -EINVAL; if (!intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output) && !intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_single_range_output)) - return 1; + return -EINVAL; if (!pt_output_base_valid(vcpu, data)) - return 1; + return -EINVAL; vmx->pt_desc.guest.output_base =3D data; break; case MSR_IA32_RTIT_OUTPUT_MASK: if (!pt_can_write_msr(vmx)) - return 1; + return -EINVAL; if (!intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output) && !intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_single_range_output)) - return 1; + return -EINVAL; vmx->pt_desc.guest.output_mask =3D data; break; case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: if (!pt_can_write_msr(vmx)) - return 1; + return -EINVAL; index =3D msr_info->index - MSR_IA32_RTIT_ADDR0_A; if (index >=3D 2 * vmx->pt_desc.num_address_ranges) - return 1; + return -EINVAL; if (is_noncanonical_msr_address(data, vcpu)) - return 1; + return -EINVAL; if (index % 2) vmx->pt_desc.guest.addr_b[index / 2] =3D data; else @@ -2563,20 +2563,20 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) if (data & PERF_CAP_LBR_FMT) { if ((data & PERF_CAP_LBR_FMT) !=3D (kvm_caps.supported_perf_cap & PERF_CAP_LBR_FMT)) - return 1; + return -EINVAL; if (!cpuid_model_is_consistent(vcpu)) - return 1; + return -EINVAL; } if (data & PERF_CAP_PEBS_FORMAT) { if ((data & PERF_CAP_PEBS_MASK) !=3D (kvm_caps.supported_perf_cap & PERF_CAP_PEBS_MASK)) - return 1; + return -EINVAL; if (!guest_cpu_cap_has(vcpu, X86_FEATURE_DS)) - return 1; + return -EINVAL; if (!guest_cpu_cap_has(vcpu, X86_FEATURE_DTES64)) - return 1; + return -EINVAL; if (!cpuid_model_is_consistent(vcpu)) - return 1; + return -EINVAL; } ret =3D kvm_set_msr_common(vcpu, msr_info); break; --=20 2.54.0 From nobody Mon Jun 8 15:36:57 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 661353E3DB6 for ; Thu, 28 May 2026 11:36:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968206; cv=none; b=tDxuiwR+fEPH1NwAqOzLrGUcqcfP8DpocS1enV1Jieek5L/DB38D2ntSUNcuze2eL5M7wY8Kj7FgXTeZ2CK7TFskuzV9Pvizhhljyz94rDdTDQaPK88dvJViO6ozHc/FKlLYDMpU5IFF1oTqicKzIy5hPcAniWPqfnzoTTsjko4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968206; c=relaxed/simple; bh=7f5srVmH0Xx0XEVGgWQLheUGHQMkiUXvXlV4c4bqp74=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cXlevD8DlsEsKzSe70fHl/QgFVhU5ds0XgxJSQ9vt/xw/BE9ks+fJy4g6AELvLewcw8njdWhrlvYi/3uXH5GSu5GhEXAvnBgG1uVg2mEKE173C2Lxa2E/jWl1blu1pdrYCdTXQ0ViqmLYxfu4dnQvBp+v4kGnX64hKPEtOcaRQ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=bMc6zICu; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=bMc6zICu; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="bMc6zICu"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="bMc6zICu" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 9BA2B6AE1C; Thu, 28 May 2026 11:36:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1779968199; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MAdbQ14wwNd5QTrRHnWRpm3W34C4IvV7gYCGkiD+Grs=; b=bMc6zICujgwDn7wQ1D8kIA/BzoXvf9kyMMTtPK0FOYMQ0ZEl4NRaMKmq9gmNubnJz7X5dC SdhNy9OOvu8g0v5huh0tbat6kr3d7JtvzOfZipliajfcEQhca5tgGp2a/a0W9rvQd5KxCI 2/d1nAEEOmX7hK84guFngaGQm4ZdnQ4= Authentication-Results: smtp-out1.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1779968199; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MAdbQ14wwNd5QTrRHnWRpm3W34C4IvV7gYCGkiD+Grs=; b=bMc6zICujgwDn7wQ1D8kIA/BzoXvf9kyMMTtPK0FOYMQ0ZEl4NRaMKmq9gmNubnJz7X5dC SdhNy9OOvu8g0v5huh0tbat6kr3d7JtvzOfZipliajfcEQhca5tgGp2a/a0W9rvQd5KxCI 2/d1nAEEOmX7hK84guFngaGQm4ZdnQ4= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 5DD9F5AD77; Thu, 28 May 2026 11:36:39 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id vRO9FccoGGrqSQAAD6G6ig (envelope-from ); Thu, 28 May 2026 11:36:39 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: Juergen Gross , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 5/6] KVM/x86: Return -errno instead of "1" for SVM related MSR emulation Date: Thu, 28 May 2026 13:36:04 +0200 Message-ID: <20260528113605.267111-6-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260528113605.267111-1-jgross@suse.com> References: <20260528113605.267111-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.998]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] Content-Type: text/plain; charset="utf-8" Instead of a literal "1" for signalling an error, use a negative errno value in the emulation code of SVM related MSR registers. Signed-off-by: Juergen Gross --- V2: - use -errno instead of KVM_MSR_RET_ERR --- arch/x86/kvm/svm/pmu.c | 4 ++-- arch/x86/kvm/svm/svm.c | 36 ++++++++++++++++++------------------ 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 7aa298eeb072..1c325d602baa 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -144,7 +144,7 @@ static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) return 0; } =20 - return 1; + return -EINVAL; } =20 static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_inf= o) @@ -173,7 +173,7 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) return 0; } =20 - return 1; + return -EINVAL; } =20 static void amd_pmu_refresh(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e02a38da5296..f8d9df822ab3 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -2791,7 +2791,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) case MSR_AMD64_TSC_RATIO: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_TSCRATEMSR)) - return 1; + return -EINVAL; msr_info->data =3D svm->tsc_ratio_msr; break; case MSR_STAR: @@ -2860,7 +2860,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) case MSR_IA32_SPEC_CTRL: if (!msr_info->host_initiated && !guest_has_spec_ctrl_msr(vcpu)) - return 1; + return -EINVAL; =20 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL)) msr_info->data =3D svm->vmcb->save.spec_ctrl; @@ -2870,7 +2870,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) case MSR_AMD64_VIRT_SPEC_CTRL: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_VIRT_SSBD)) - return 1; + return -EINVAL; =20 msr_info->data =3D svm->virt_spec_ctrl; break; @@ -2907,7 +2907,7 @@ static int svm_complete_emulated_msr(struct kvm_vcpu = *vcpu, int err) return kvm_complete_insn_gp(vcpu, err); =20 svm_vmgexit_inject_exception(svm, X86_TRAP_GP); - return 1; + return -EINVAL; } =20 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) @@ -2916,7 +2916,7 @@ static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 d= ata) int svm_dis, chg_mask; =20 if (data & ~SVM_VM_CR_VALID_MASK) - return 1; + return -EINVAL; =20 chg_mask =3D SVM_VM_CR_VALID_MASK; =20 @@ -2930,7 +2930,7 @@ static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 d= ata) =20 /* check for svm_disable while efer.svme is set */ if (svm_dis && (vcpu->arch.efer & EFER_SVME)) - return 1; + return -EINVAL; =20 return 0; } @@ -2952,7 +2952,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr) if (!guest_cpu_cap_has(vcpu, X86_FEATURE_TSCRATEMSR)) { =20 if (!msr->host_initiated) - return 1; + return -EINVAL; /* * In case TSC scaling is not enabled, always * leave this MSR at the default value. @@ -2962,12 +2962,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr) * Ignore this value as well. */ if (data !=3D 0 && data !=3D svm->tsc_ratio_msr) - return 1; + return -EINVAL; break; } =20 if (data & SVM_TSC_RATIO_RSVD) - return 1; + return -EINVAL; =20 svm->tsc_ratio_msr =3D data; =20 @@ -2989,10 +2989,10 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr) case MSR_IA32_SPEC_CTRL: if (!msr->host_initiated && !guest_has_spec_ctrl_msr(vcpu)) - return 1; + return -EINVAL; =20 if (kvm_spec_ctrl_test_value(data)) - return 1; + return -EINVAL; =20 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL)) svm->vmcb->save.spec_ctrl =3D data; @@ -3017,10 +3017,10 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr) case MSR_AMD64_VIRT_SPEC_CTRL: if (!msr->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_VIRT_SSBD)) - return 1; + return -EINVAL; =20 if (data & ~SPEC_CTRL_SSBD) - return 1; + return -EINVAL; =20 svm->virt_spec_ctrl =3D data; break; @@ -3115,7 +3115,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr) } =20 if (data & DEBUGCTL_RESERVED_BITS) - return 1; + return -EINVAL; =20 if (svm->vmcb->save.dbgctl =3D=3D data) break; @@ -3131,7 +3131,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr) if (!lbrv) return KVM_MSR_RET_UNSUPPORTED; if (!msr->host_initiated) - return 1; + return -EINVAL; *svm_vmcb_lbr(svm, ecx) =3D data; vmcb_mark_dirty(svm->vmcb, VMCB_LBR); break; @@ -3143,7 +3143,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr) * originating from those kernels. */ if (!msr->host_initiated && !page_address_valid(vcpu, data)) - return 1; + return -EINVAL; =20 svm->nested.hsave_msr =3D data & PAGE_MASK; break; @@ -3156,10 +3156,10 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr) u64 supported_de_cfg; =20 if (svm_get_feature_msr(ecx, &supported_de_cfg)) - return 1; + return -EINVAL; =20 if (data & ~supported_de_cfg) - return 1; + return -EINVAL; =20 svm->msr_decfg =3D data; break; --=20 2.54.0 From nobody Mon Jun 8 15:36:57 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0C193E5A26 for ; Thu, 28 May 2026 11:36:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968208; cv=none; b=k+4bQSS5t003JuzGi/ml6qLMYokkTic7ImZSXGBl7TdQDrrzV4jQ8nlWcM522gNbQUH61TSsMCSA1p7XkdwH9N8NqnWLIAxhHXs4h5N/IaDKMiho+rUWsO6atPT6Q/JVdC9eVSMsNxyJkpxuZQCo9sCNlZCFA0IDdT0VDFj0eUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779968208; c=relaxed/simple; bh=D5HALjg+7SU7Og/xkW3ZLo9f3TpFGJncAcMxgUD/Os4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I3FyWdqd9e3OfpN1thn2bavg47W9wpTQdFH4Z5dpDhPeCtAj/uT3XVrwm55653HCuWDk0F0w5aMXpvsdwg8DyKC0R9G2Na3F7elWUL3PGrRRJ0xOatrg1W9ib2l7d40ws7vISx7p0WyUBKOw/Gru3MAEzEft7DBRa5wb4geM8RQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 3EF6566D81; Thu, 28 May 2026 11:36:45 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id E93BF5AD78; Thu, 28 May 2026 11:36:44 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id uBLeN8woGGqPSgAAD6G6ig (envelope-from ); Thu, 28 May 2026 11:36:44 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: Juergen Gross , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , David Woodhouse , Paul Durrant Subject: [PATCH v2 6/6] KVM/x86: Return -errno instead of "1" for common MSR emulation Date: Thu, 28 May 2026 13:36:05 +0200 Message-ID: <20260528113605.267111-7-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260528113605.267111-1-jgross@suse.com> References: <20260528113605.267111-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 3EF6566D81 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Rspamd-Action: no action X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spam-Score: -4.00 X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" Instead of a literal "1" for signalling an error, use a negative errno value in the common emulation code of MSR registers. Signed-off-by: Juergen Gross --- V2: - use -errno instead of KVM_MSR_RET_ERR --- arch/x86/kvm/mtrr.c | 6 +-- arch/x86/kvm/pmu.c | 8 ++-- arch/x86/kvm/x86.c | 102 ++++++++++++++++++++++---------------------- arch/x86/kvm/xen.c | 10 ++--- 4 files changed, 63 insertions(+), 63 deletions(-) diff --git a/arch/x86/kvm/mtrr.c b/arch/x86/kvm/mtrr.c index 6f74e2b27c1e..57c7cfa74a35 100644 --- a/arch/x86/kvm/mtrr.c +++ b/arch/x86/kvm/mtrr.c @@ -99,10 +99,10 @@ int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u6= 4 data) =20 mtrr =3D find_mtrr(vcpu, msr); if (!mtrr) - return 1; + return -EINVAL; =20 if (!kvm_mtrr_valid(vcpu, msr, data)) - return 1; + return -EINVAL; =20 *mtrr =3D data; return 0; @@ -126,7 +126,7 @@ int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u6= 4 *pdata) =20 mtrr =3D find_mtrr(vcpu, msr); if (!mtrr) - return 1; + return -EINVAL; =20 *pdata =3D *mtrr; return 0; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index e218352e3423..bc7273106f32 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -857,7 +857,7 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) switch (msr) { case MSR_CORE_PERF_GLOBAL_STATUS: if (!msr_info->host_initiated) - return 1; /* RO MSR */ + return -EINVAL; /* RO MSR */ fallthrough; case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: /* Per PPR, Read-only MSR. Writes are ignored. */ @@ -865,7 +865,7 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) break; =20 if (data & pmu->global_status_rsvd) - return 1; + return -EINVAL; =20 pmu->global_status =3D data; break; @@ -874,7 +874,7 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) fallthrough; case MSR_CORE_PERF_GLOBAL_CTRL: if (!kvm_valid_perf_global_ctrl(pmu, data)) - return 1; + return -EINVAL; =20 if (pmu->global_ctrl !=3D data) { diff =3D pmu->global_ctrl ^ data; @@ -894,7 +894,7 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_d= ata *msr_info) * GLOBAL_STATUS, and so the set of reserved bits is the same. */ if (data & pmu->global_status_rsvd) - return 1; + return -EINVAL; fallthrough; case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: if (!msr_info->host_initiated) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c1a72d749084..edb620631672 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -683,7 +683,7 @@ int kvm_set_user_return_msr(unsigned slot, u64 value, u= 64 mask) return 0; err =3D wrmsrq_safe(kvm_uret_msrs_list[slot], value); if (err) - return 1; + return -EINVAL; =20 msrs->values[slot].curr =3D value; kvm_user_return_register_notifier(msrs); @@ -1859,7 +1859,7 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 i= ndex, u64 data, case MSR_CSTAR: case MSR_LSTAR: if (is_noncanonical_msr_address(data, vcpu)) - return 1; + return -EINVAL; break; case MSR_IA32_SYSENTER_EIP: case MSR_IA32_SYSENTER_ESP: @@ -1879,12 +1879,12 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32= index, u64 data, break; case MSR_TSC_AUX: if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) - return 1; + return -EINVAL; =20 if (!host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_RDTSCP) && !guest_cpu_cap_has(vcpu, X86_FEATURE_RDPID)) - return 1; + return -EINVAL; =20 /* * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has @@ -1896,7 +1896,7 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 i= ndex, u64 data, * provide consistent behavior for the guest. */ if (guest_cpuid_is_intel_compatible(vcpu) && (data >> 32) !=3D 0) - return 1; + return -EINVAL; =20 data =3D (u32)data; break; @@ -1906,11 +1906,11 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32= index, u64 data, !guest_cpu_cap_has(vcpu, X86_FEATURE_IBT)) return KVM_MSR_RET_UNSUPPORTED; if (!kvm_is_valid_u_s_cet(vcpu, data)) - return 1; + return -EINVAL; break; case MSR_KVM_INTERNAL_GUEST_SSP: if (!host_initiated) - return 1; + return -EINVAL; fallthrough; /* * Note that the MSR emulation here is flawed when a vCPU @@ -1933,10 +1933,10 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32= index, u64 data, if (index =3D=3D MSR_IA32_INT_SSP_TAB && !guest_cpu_cap_has(vcpu, X86_FE= ATURE_LM)) return KVM_MSR_RET_UNSUPPORTED; if (is_noncanonical_msr_address(data, vcpu)) - return 1; + return -EINVAL; /* All SSP MSRs except MSR_IA32_INT_SSP_TAB must be 4-byte aligned */ if (index !=3D MSR_IA32_INT_SSP_TAB && !IS_ALIGNED(data, 4)) - return 1; + return -EINVAL; break; } =20 @@ -1975,12 +1975,12 @@ static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32= index, u64 *data, switch (index) { case MSR_TSC_AUX: if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) - return 1; + return -EINVAL; =20 if (!host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_RDTSCP) && !guest_cpu_cap_has(vcpu, X86_FEATURE_RDPID)) - return 1; + return -EINVAL; break; case MSR_IA32_U_CET: case MSR_IA32_S_CET: @@ -1990,7 +1990,7 @@ static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 i= ndex, u64 *data, break; case MSR_KVM_INTERNAL_GUEST_SSP: if (!host_initiated) - return 1; + return -EINVAL; fallthrough; case MSR_IA32_PL0_SSP ... MSR_IA32_INT_SSP_TAB: if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK)) @@ -3944,7 +3944,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) return KVM_MSR_RET_UNSUPPORTED; =20 if (data & ~kvm_caps.supported_perf_cap) - return 1; + return -EINVAL; =20 /* * Note, this is not just a performance optimization! KVM @@ -3963,7 +3963,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) =20 if (!msr_info->host_initiated) { if ((!guest_has_pred_cmd_msr(vcpu))) - return 1; + return -EINVAL; =20 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) && !guest_cpu_cap_has(vcpu, X86_FEATURE_AMD_IBPB)) @@ -3980,7 +3980,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) reserved_bits |=3D PRED_CMD_SBPB; =20 if (data & reserved_bits) - return 1; + return -EINVAL; =20 if (!data) break; @@ -3991,10 +3991,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) case MSR_IA32_FLUSH_CMD: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_FLUSH_L1D)) - return 1; + return -EINVAL; =20 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH)) - return 1; + return -EINVAL; if (!data) break; =20 @@ -4014,19 +4014,19 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) */ if (data & ~(BIT_ULL(18) | BIT_ULL(24))) { kvm_pr_unimpl_wrmsr(vcpu, msr, data); - return 1; + return -EINVAL; } vcpu->arch.msr_hwcr =3D data; break; case MSR_FAM10H_MMIO_CONF_BASE: if (data !=3D 0) { kvm_pr_unimpl_wrmsr(vcpu, msr, data); - return 1; + return -EINVAL; } break; case MSR_IA32_CR_PAT: if (!kvm_pat_valid(data)) - return 1; + return -EINVAL; =20 vcpu->arch.pat =3D data; break; @@ -4059,7 +4059,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) if (!msr_info->host_initiated) { /* RO bits */ if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK) - return 1; + return -EINVAL; =20 /* R bits, i.e. writes are ignored, but don't fault. */ data =3D data & ~MSR_IA32_MISC_ENABLE_EMON; @@ -4069,7 +4069,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) = && ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { if (!guest_cpu_cap_has(vcpu, X86_FEATURE_XMM3)) - return 1; + return -EINVAL; vcpu->arch.ia32_misc_enable_msr =3D data; vcpu->arch.cpuid_dynamic_bits_dirty =3D true; } else { @@ -4079,7 +4079,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) } case MSR_IA32_SMBASE: if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) - return 1; + return -EINVAL; vcpu->arch.smbase =3D data; break; case MSR_IA32_POWER_CTL: @@ -4099,7 +4099,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) return KVM_MSR_RET_UNSUPPORTED; =20 if (data & ~vcpu->arch.guest_supported_xss) - return 1; + return -EINVAL; if (vcpu->arch.ia32_xss =3D=3D data) break; vcpu->arch.ia32_xss =3D data; @@ -4107,7 +4107,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) break; case MSR_SMI_COUNT: if (!msr_info->host_initiated) - return 1; + return -EINVAL; vcpu->arch.smi_count =3D data; break; case MSR_KVM_WALL_CLOCK_NEW: @@ -4141,14 +4141,14 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) return KVM_MSR_RET_UNSUPPORTED; =20 if (kvm_pv_enable_async_pf(vcpu, data)) - return 1; + return -EINVAL; break; case MSR_KVM_ASYNC_PF_INT: if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) return KVM_MSR_RET_UNSUPPORTED; =20 if (kvm_pv_enable_async_pf_int(vcpu, data)) - return 1; + return -EINVAL; break; case MSR_KVM_ASYNC_PF_ACK: if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) @@ -4168,10 +4168,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) return KVM_MSR_RET_UNSUPPORTED; =20 if (unlikely(!sched_info_on())) - return 1; + return -EINVAL; =20 if (data & KVM_STEAL_RESERVED_MASK) - return 1; + return -EINVAL; =20 vcpu->arch.st.msr_val =3D data; =20 @@ -4186,7 +4186,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) return KVM_MSR_RET_UNSUPPORTED; =20 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) - return 1; + return -EINVAL; break; =20 case MSR_KVM_POLL_CONTROL: @@ -4195,7 +4195,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) =20 /* only enable bit supported */ if (data & (-1ULL << 1)) - return 1; + return -EINVAL; =20 vcpu->arch.msr_kvm_poll_control =3D data; break; @@ -4248,44 +4248,44 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) break; case MSR_AMD64_OSVW_ID_LENGTH: if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW)) - return 1; + return -EINVAL; vcpu->arch.osvw.length =3D data; break; case MSR_AMD64_OSVW_STATUS: if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW)) - return 1; + return -EINVAL; vcpu->arch.osvw.status =3D data; break; case MSR_PLATFORM_INFO: if (!msr_info->host_initiated) - return 1; + return -EINVAL; vcpu->arch.msr_platform_info =3D data; break; case MSR_MISC_FEATURES_ENABLES: if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && !supports_cpuid_fault(vcpu))) - return 1; + return -EINVAL; vcpu->arch.msr_misc_features_enables =3D data; break; #ifdef CONFIG_X86_64 case MSR_IA32_XFD: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_XFD)) - return 1; + return -EINVAL; =20 if (data & ~kvm_guest_supported_xfd(vcpu)) - return 1; + return -EINVAL; =20 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); break; case MSR_IA32_XFD_ERR: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_XFD)) - return 1; + return -EINVAL; =20 if (data & ~kvm_guest_supported_xfd(vcpu)) - return 1; + return -EINVAL; =20 vcpu->arch.guest_fpu.xfd_err =3D data; break; @@ -4321,7 +4321,7 @@ static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr= , u64 *pdata, bool host) break; case MSR_IA32_MCG_CTL: if (!(mcg_cap & MCG_CTL_P) && !host) - return 1; + return -EINVAL; data =3D vcpu->arch.mcg_ctl; break; case MSR_IA32_MCG_STATUS: @@ -4330,10 +4330,10 @@ static int get_msr_mce(struct kvm_vcpu *vcpu, u32 m= sr, u64 *pdata, bool host) case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: last_msr =3D MSR_IA32_MCx_CTL2(bank_num) - 1; if (msr > last_msr) - return 1; + return -EINVAL; =20 if (!(mcg_cap & MCG_CMCI_P) && !host) - return 1; + return -EINVAL; offset =3D array_index_nospec(msr - MSR_IA32_MC0_CTL2, last_msr + 1 - MSR_IA32_MC0_CTL2); data =3D vcpu->arch.mci_ctl2_banks[offset]; @@ -4341,14 +4341,14 @@ static int get_msr_mce(struct kvm_vcpu *vcpu, u32 m= sr, u64 *pdata, bool host) case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: last_msr =3D MSR_IA32_MCx_CTL(bank_num) - 1; if (msr > last_msr) - return 1; + return -EINVAL; =20 offset =3D array_index_nospec(msr - MSR_IA32_MC0_CTL, last_msr + 1 - MSR_IA32_MC0_CTL); data =3D vcpu->arch.mce_banks[offset]; break; default: - return 1; + return -EINVAL; } *pdata =3D data; return 0; @@ -4475,7 +4475,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) break; case MSR_IA32_SMBASE: if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) - return 1; + return -EINVAL; msr_info->data =3D vcpu->arch.smbase; break; case MSR_SMI_COUNT: @@ -4562,7 +4562,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) case MSR_IA32_XSS: if (!msr_info->host_initiated && !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) - return 1; + return -EINVAL; msr_info->data =3D vcpu->arch.ia32_xss; break; case MSR_K7_CLK_CTL: @@ -4607,18 +4607,18 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) break; case MSR_AMD64_OSVW_ID_LENGTH: if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW)) - return 1; + return -EINVAL; msr_info->data =3D vcpu->arch.osvw.length; break; case MSR_AMD64_OSVW_STATUS: if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW)) - return 1; + return -EINVAL; msr_info->data =3D vcpu->arch.osvw.status; break; case MSR_PLATFORM_INFO: if (!msr_info->host_initiated && !vcpu->kvm->arch.guest_can_read_msr_platform_info) - return 1; + return -EINVAL; msr_info->data =3D vcpu->arch.msr_platform_info; break; case MSR_MISC_FEATURES_ENABLES: @@ -4631,14 +4631,14 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) case MSR_IA32_XFD: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_XFD)) - return 1; + return -EINVAL; =20 msr_info->data =3D vcpu->arch.guest_fpu.fpstate->xfd; break; case MSR_IA32_XFD_ERR: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_XFD)) - return 1; + return -EINVAL; =20 msr_info->data =3D vcpu->arch.guest_fpu.xfd_err; break; diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c index 91fd3673c09a..d7bcd59603f7 100644 --- a/arch/x86/kvm/xen.c +++ b/arch/x86/kvm/xen.c @@ -1291,7 +1291,7 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcp= u, u64 data) */ if (kvm->arch.xen.shinfo_cache.active && kvm_xen_shared_info_init(kvm)) - r =3D 1; + r =3D -EINVAL; } mutex_unlock(&kvm->arch.xen.xen_lock); =20 @@ -1309,7 +1309,7 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcp= u, u64 data) int i; =20 if (page_num) - return 1; + return -EINVAL; =20 /* mov imm32, %eax */ instructions[0] =3D 0xb8; @@ -1328,7 +1328,7 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcp= u, u64 data) if (kvm_vcpu_write_guest(vcpu, page_addr + (i * sizeof(instructions)), instructions, sizeof(instructions))) - return 1; + return -EFAULT; } } else { /* @@ -1343,7 +1343,7 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcp= u, u64 data) int ret; =20 if (page_num >=3D blob_size) - return 1; + return -EINVAL; =20 blob_addr +=3D page_num * PAGE_SIZE; =20 @@ -1354,7 +1354,7 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcp= u, u64 data) ret =3D kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE); kfree(page); if (ret) - return 1; + return -EFAULT; } return 0; } --=20 2.54.0