From nobody Mon Jun 8 16:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6A3F366072; Thu, 28 May 2026 08:04:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955493; cv=none; b=MhmqyrHA0cdyHg4Irj/NHvNfh7gI3kBEntuO8+Mg8Y3z5agBaxPnCXEa7ztZEx+LriFYI37q+Y1cjKwyz3F/Yr8jVO/cEXLs0WGOi77cm3r/GJ91J0SwXd1+Q7sH3ULnkezg4l4g5lTHpLBr6tgZmWF6veM1KAe09gMr8Rf2s7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955493; c=relaxed/simple; bh=zolK2oG5xNFmuVZGOh6oVCzas8YjEVDSW701MpnAMKc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o+Q2P4mj1uQT/RKRZXtaWPI6OD2SkWsLAJebnbn4rQNh6FnKbptENcS5ZeQwYxWJgtKz3O8cs14QVZ0GEEaWvzYDaiY2Ku4yYb/e1gq96UnoXM9mePcDBvbwKxwhDO0qlh3RzEEbE4zV1H02iq+cHrxLnTUX6AnZArDQX9ElWIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jlE2Uvqe; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jlE2Uvqe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2EBB61F00A3A; Thu, 28 May 2026 08:04:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779955491; bh=Vurpefvu+YHMOkHImZQPG2a13ySBXId/U1SSogn8GUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=jlE2Uvqe9J3edh7uCmN0GKa8UL4kpF+IY4XQQ1g/a7ItT01zP5l1ZlJ6nilIm4Q1A G7t2hruHSW88BoLCqh7dHPfsxAN/TtL83lug5Sdhc0kwrTcoO0mic5RG6uRqqKFcOG MvBVgX+v31d0402dx5StFKkrfM0fmayhiV3zXalJe01la/4sbSZtNkXwexnWTT/qlW Cy3HeCwmTVTxD2POO/2L9TP6LHe/LSZtI265CIIUUSn8ehSJDDwkb7cUmhTLDDm44W r/Q2XfLZOW8yN5tYcV7HL5MQKapvcytCvf352ZrfJux9H/JL/lhVb4g16sfIXPdKFh 5xuKV8od2xT6w== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 1/7] pinctrl: renesas: rzg2l: Generalize the power source code Date: Thu, 28 May 2026 11:04:33 +0300 Message-ID: <20260528080439.615958-2-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528080439.615958-1-claudiu.beznea@kernel.org> References: <20260528080439.615958-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The current functions used to get/set the pin power source check the OTHER_POC register, which is specific to the RZ/G3L SoC only. To allow the code to be extended for other power source functionalities (e.g. I3C on RZ/G3S), generalize the functions used to get/set the pin power source. For this, introduce the struct rzg2l_register_masks data structure whose purpose is to store SoC specific register bit masks. The members of this structure are then used in rzg2l_caps_to_pwr_reg() to retrieve the bitmask corresponding to a SoC specific power source capability. The conversion between HW specific power source values and SW specific power source values is now handled through rzg2l_pwr_reg_val_to_ps() and rzg2l_ps_to_pwr_reg_val(). Finally, to keep the code generic, the register update in rzg2l_set_power_source() was changed to a read-modify-write approach to cover all cases. Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang --- Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 177 +++++++++++++++--------- 1 file changed, 112 insertions(+), 65 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index ac42093fc579..a648d75a2bd2 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -186,6 +186,7 @@ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >=3D 3.3V */ +#define PVDD_MASK 0x3 =20 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ @@ -268,6 +269,23 @@ struct rzg2l_register_offsets { u16 other_poc; }; =20 +/** + * struct rzg2l_register_masks - Masks for different RZ/G2L pinctrl functi= onalities + * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask + * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask + * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + */ +struct rzg2l_register_masks { + union { + /* RZ/G3L masks */ + struct { + u8 other_poc_pvdd1833_oth_awo_poc; + u8 other_poc_pvdd1833_oth_iso_poc; + u8 other_poc_wdtovf_n_poc; + }; + }; +}; + /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source @@ -288,6 +306,8 @@ enum rzg2l_iolh_index { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @masks: hardware specific masks for various functionalities available in + * the registers described by regs * @iolh_groupa_ua: IOLH group A uA specific values * @iolh_groupb_ua: IOLH group B uA specific values * @iolh_groupc_ua: IOLH group C uA specific values @@ -301,6 +321,7 @@ enum rzg2l_iolh_index { */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + const struct rzg2l_register_masks masks; u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; @@ -1047,27 +1068,73 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinct= rl *pctrl, u32 offset, } =20 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, - u32 caps, u8 *mask) + const struct rzg2l_register_masks *masks, + u32 caps, u16 *offset, u8 *mask) { - if (caps & PIN_CFG_IO_VMC_SD0) - return SD_CH(regs->sd_ch, 0); - if (caps & PIN_CFG_IO_VMC_SD1) - return SD_CH(regs->sd_ch, 1); - if (caps & PIN_CFG_IO_VMC_ETH0) - return ETH_POC(regs->eth_poc, 0); - if (caps & PIN_CFG_IO_VMC_ETH1) - return ETH_POC(regs->eth_poc, 1); - if (caps & PIN_CFG_IO_VMC_QSPI) - return QSPI; + *mask =3D PVDD_MASK; + + if (caps & PIN_CFG_IO_VMC_SD0) { + *offset =3D SD_CH(regs->sd_ch, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_SD1) { + *offset =3D SD_CH(regs->sd_ch, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH0) { + *offset =3D ETH_POC(regs->eth_poc, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH1) { + *offset =3D ETH_POC(regs->eth_poc, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_QSPI) { + *offset =3D regs->qspi; + return 0; + } if (caps & PIN_CFG_OTHER_POC_MASK) { + *offset =3D regs->other_poc; if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) - *mask =3D BIT(0); + *mask =3D masks->other_poc_pvdd1833_oth_awo_poc; else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) - *mask =3D BIT(1); + *mask =3D masks->other_poc_pvdd1833_oth_iso_poc; else - *mask =3D BIT(2); + *mask =3D masks->other_poc_wdtovf_n_poc; + return 0; + } =20 - return OTHER_POC; + return -EINVAL; +} + +static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) +{ + switch (val) { + case PVDD_1800: + return 1800; + case PVDD_2500: + return 2500; + case PVDD_3300: + return 3300; + } + + return -EINVAL; +} + +static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps) +{ + switch (ps) { + case 1800: + *val =3D PVDD_1800; + return 0; + case 2500: + if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) + return -EINVAL; + *val =3D PVDD_2500; + return 0; + case 3300: + *val =3D PVDD_3300; + return 0; } =20 return -EINVAL; @@ -1077,76 +1144,51 @@ static int rzg2l_get_power_source(struct rzg2l_pinc= trl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - u8 val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; + u8 mask, val; + u16 offset; + int ret; =20 if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; =20 - pwr_reg =3D rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + ret =3D rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; =20 - val =3D readb(pctrl->base + pwr_reg); - if (pwr_reg =3D=3D OTHER_POC) - val =3D field_get(mask, val); + val =3D readb(pctrl->base + offset); =20 - switch (val) { - case PVDD_1800: - return 1800; - case PVDD_2500: - return 2500; - case PVDD_3300: - return 3300; - default: - /* Should not happen. */ - return -EINVAL; - } + return rzg2l_pwr_reg_val_to_ps(field_get(mask, val), caps); } =20 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u3= 2 caps, u32 ps) { const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - u8 poc_val, val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; + u8 mask, val; + u16 offset; + int ret; =20 if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source =3D ps; return 0; } =20 - switch (ps) { - case 1800: - poc_val =3D PVDD_1800; - break; - case 2500: - if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) - return -EINVAL; - poc_val =3D PVDD_2500; - break; - case 3300: - poc_val =3D PVDD_3300; - break; - default: - return -EINVAL; - } + ret =3D rzg2l_ps_to_pwr_reg_val(&val, ps, caps); + if (ret) + return ret; + + ret =3D rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; =20 - pwr_reg =3D rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + scoped_guard(raw_spinlock, &pctrl->lock) { + u8 tmp =3D readb(pctrl->base + offset); =20 - if (pwr_reg =3D=3D OTHER_POC) { - scoped_guard(raw_spinlock, &pctrl->lock) { - val =3D readb(pctrl->base + pwr_reg); - if (poc_val) - val |=3D mask; - else - val &=3D ~mask; - writeb(val, pctrl->base + pwr_reg); - } - } else { - writeb(poc_val, pctrl->base + pwr_reg); + tmp &=3D ~mask; + tmp |=3D field_prep(mask, val); + writeb(tmp, pctrl->base + offset); } =20 pctrl->settings[pin].power_source =3D ps; @@ -3795,6 +3837,11 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .oen =3D 0x3018, .other_poc =3D OTHER_POC, }, + .masks =3D { + .other_poc_pvdd1833_oth_awo_poc =3D BIT(0), + .other_poc_pvdd1833_oth_iso_poc =3D BIT(1), + .other_poc_wdtovf_n_poc =3D BIT(2), + }, .iolh_groupa_ua =3D { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, --=20 2.43.0 From nobody Mon Jun 8 16:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4010D367B8C; Thu, 28 May 2026 08:04:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779955496; bh=IpNkcRyrbtHE0i7ymqh8hO4uiycSt7wtY+zaW32miTM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=LQTLTsj2Gr5HXXOlVvV+0g983TAnosR3MjP9w5U+39QQ5A86bnRHsDV43h83oka10 DzUFrpubRVIO1vV5H1h2JltEd2CjvahAz6xXQ9Fmm/kZLa/ltqaTiyCir/WJoTeca6 R+SEM16W/MB/yAftZbkYRvpUagp+SpWYFualITrWr4GyxP9nvJSYG7LmsQ0/rvx/RA KknL78Z7KWh7WTqmSDb3UxJF9sQNznUO32Ucc3HPk7GwncyQY4CbncQW5Y5z9rtsOn mfr+sjHll/u3ra1vMrSK/1zOItLPT0UCX5VccnoU5E6bwVt0TvTpFlyh42Ovl/Ypnn rjMugpp7pOhOA== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 2/7] pinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfg Date: Thu, 28 May 2026 11:04:34 +0300 Message-ID: <20260528080439.615958-3-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528080439.615958-1-claudiu.beznea@kernel.org> References: <20260528080439.615958-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Drop the QSPI and OTHER_POC register defines, which are SoC specific and accessible through struct rzg2l_hwcfg::{qspi, other_poc}. Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang --- Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index a648d75a2bd2..77443cf1f431 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -180,8 +180,6 @@ #define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ -#define OTHER_POC (0x3028) /* known on RZ/G3L only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -3816,9 +3814,9 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { .regs =3D { .pwpr =3D 0x3014, .sd_ch =3D 0x3000, + .qspi =3D 0x3008, .eth_poc =3D 0x300c, .oen =3D 0x3018, - .qspi =3D QSPI, }, .iolh_groupa_ua =3D { /* 3v3 power source */ @@ -3835,7 +3833,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, .oen =3D 0x3018, - .other_poc =3D OTHER_POC, + .other_poc =3D 0x3028, }, .masks =3D { .other_poc_pvdd1833_oth_awo_poc =3D BIT(0), --=20 2.43.0 From nobody Mon Jun 8 16:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27B50367298; Thu, 28 May 2026 08:05:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955502; cv=none; b=Nerr37J9DxRd/5vSIggFKsRONCHdhS64M95sbwfqYH5etfvneVyCRM0PD8nHQGSedc3ddT4bsu13d/24895rt35tMd15sqeetQWVitSm5QFP3tabk8RCeRiDgNbiorBmssbZ42znnbokzU4m3qaVdo0Sn3K9aoKWVf8dX/NZbjU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955502; c=relaxed/simple; bh=d+9dPpoQT2mYvlFwzMY+LFDAB/OxOOLHqzr1Xd7eo5Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WJBlns+Rj5PMROonivzIUMf5FCmK3TXgrVp9722crtbxGCYQVEn3pZnFQTTc3C3wXaTBNPIvhD9PgX0a3PPMoI0fsAVnfE89Vn2bIr4pVvjDPPwjk9ur4A5PNyGtItIMAd8wS9/5GzvKz4XHX5F8ZZ3SbeGDnI8OtwjjiCZAj8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J+fv2Zkl; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J+fv2Zkl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 711EB1F00A3A; Thu, 28 May 2026 08:04:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779955500; bh=ay6gDYre614iH/Ln6/W4oneHyqGUkuOe32mdQBoj+TY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=J+fv2ZklkYR7YxgIM2/yH6NcQb8ObC7ao9raqn0e51NVLXekv8eGlW7O2ndfmgaR9 cDAsU3lSAVUaofFtq4r3yRrGJqYtiVMgDJtd7m9SVceTonyX9g42ryMsJUwQsq/eZb Q37Y0TXQBzFQBVL/Lng+0rNtxfXBzof8xsoMbL4MerJKCTdOgY95+fJkY3+uXJux1u NLNK7rM9UTKorZYOtXeVUEgL2n2S+Gr8UNE0ZdNuWyq80oTOssmXLmFwK9pJxvR9Pb 2cUun1iMBUBa5rYyeHDR/bnZd8dd2WkcV3TqmkojXBnHQojtmBT9sFca2Z/ARW/shK iooeF3BWKMD9A== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 3/7] pinctrl: renesas: rzg2l: Keep member documentation aligned Date: Thu, 28 May 2026 11:04:35 +0300 Message-ID: <20260528080439.615958-4-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528080439.615958-1-claudiu.beznea@kernel.org> References: <20260528080439.615958-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Keep the documentation for struct rzg2l_pinctrl_reg_cache members aligned with the struct member order. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang --- Changes in v2: - collected tags drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 77443cf1f431..b1ffdc133987 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -380,16 +380,16 @@ struct rzg2l_pinctrl_pin_settings { * @pmc: PMC registers cache * @pfc: PFC registers cache * @iolh: IOLH registers cache - * @pupd: PUPD registers cache * @ien: IEN registers cache + * @pupd: PUPD registers cache * @smt: SMT registers cache * @sr: SR registers cache * @nod: NOD registers cache * @clone: Clone register cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache - * @other_poc: OTHER_POC register cache * @oen: Output Enable register cache + * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache */ struct rzg2l_pinctrl_reg_cache { --=20 2.43.0 From nobody Mon Jun 8 16:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FDFA367B81; Thu, 28 May 2026 08:05:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955506; cv=none; b=VZfytPmjtWiOD1G+NmSd+Ct2foM4DRvQEfzZWWkJ9z5DpLmBm2SZpJTT/SHrEXMfIVaqig7ZJOTPkbNR93bxgYK20LHAHs2umutu5yaRH6eAJBuu/Gf958DDcLb2bUtkEdm8fk3rDpVXhVEsh47bo+L/TL2nYi2e3Yv/GAoU2V4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955506; c=relaxed/simple; bh=A+jYPVD0GUndrlTynbeuAmrJJfgoYOtq14VG0REN8t8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=itzk7UPjusPIKA7nTfkV//biKGB0hMOsEi7UYf44qu2hcZyYYGAypKrLSVHotPxLir5yeQvnpCi4HQ3fR/VTgGHSxw00NjxTRbR8GFFJy2eQeh7zD8t0wb9GiOahHvxGjiatq1r2niejurU35l/C3xhJ9D3PLZVEJf2APDE8Pc8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nDoPlLsx; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nDoPlLsx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A1431F00A3C; Thu, 28 May 2026 08:05:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779955505; bh=eEzAmMzCpBQHbj7s6U/8LxCHRyiO5fN0Btf+dk43Ea8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=nDoPlLsxQNwBKorAFUWeh4ncjpgu4UmPBqtQKnyIW6y7AVOnR0otanq0Am+C0uSOV edaVRyEoV9JNNdQwopnTFki5HyAUHgu8EgmM1IU1QzS6pwsIIUcqdfQrF+S+Ae7cmQ Is3IpUu6Kq3yFpPEm8ScNf+0SMLRRAXlJgppQgsjiFJjQmXdA7Ej4rHELRaJkJ4+y7 Cxu9T1E1lN97xGX3rNmuFaD+m3V6iGmqpT4Sgkeu0A7LwqrWF07DXOXO9ecnNWSu16 JDjpLkNQcJiB040GSfju57aUBPLvhqfPY03WrlHFPbaAse2cibSJiBtGbcGSr4lRt9 J17gnqBQsl/6Q== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 4/7] pinctrl: renesas: rzg2l: Use tab instead of spaces Date: Thu, 28 May 2026 11:04:36 +0300 Message-ID: <20260528080439.615958-5-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528080439.615958-1-claudiu.beznea@kernel.org> References: <20260528080439.615958-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use tab instead of spaces to follow the same coding style. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang --- Changes in v2: - collected tags=20 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index b1ffdc133987..517001145bd0 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -407,7 +407,7 @@ struct rzg2l_pinctrl_reg_cache { u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; - u8 other_poc; + u8 other_poc; u8 qspi; }; =20 --=20 2.43.0 From nobody Mon Jun 8 16:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5530D367F3C; Thu, 28 May 2026 08:05:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955511; cv=none; b=erCHfUHt8Fr9FXMzL5DExeI702re7XGiVIhhnDd+WbD+OwhPXlMgxCl9ru/GYJyz67aPHvBRR6HaZrQfWL5I8Iv//VNNNIHDvEeRWL1CRM9jcj2W1WwIQfGiaBmuuqFaNKUw9cQP5GBt0qpZPmlnAhe/o/3N5UdGePy6eS6TAcs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955511; c=relaxed/simple; bh=xirvXHtC/ArjiPqJRmGy6rCPiWrM/ucwQYnWScSrVZo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PJzIlLThykaWDP7B43KUorNJL8OIXHYoWlyj5S88gQNUO9Gub9YiZsfkhNvVkqKimganXOAmXiXxyj3dFWxwpBqtCwkA3vL0AVqXJlCYzE7hzp/I6Qv3NvY/Mij2S6rzSQROV2C65ENYGQz0Y81x2SMPUeoEoTc5fWPkgk0PF4k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J+ykfSWx; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J+ykfSWx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CCD261F000E9; Thu, 28 May 2026 08:05:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779955510; bh=SeNY6NLp3JOsBY+IVTny8zrODmZcrg5z5df04xZGriM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=J+ykfSWxJ4qtxp12Jf5+bR4T9y41K0vA9pK4ymkxkwzME+8OdnONQdZL68RRMyAGQ 6xHIY4zbPXMe/3jKhws/WPPR16AajBncCeO3P6S3bh8QZ56pT9TPMnGeVKwPGzOwFa LLBACPh9aLxCv96Ll2Iof+DJevlQF1CEKruin8XsT2culFtKRrfmq7vU5oardg6ruV 5HS9hk1NAx5wGIPLemS38fvpsy5qv8ONIaEJaoTs13lhwxP2r5s7C7DYzpzk77lXfp gxPaeQiDcIwmS9yVRnbYHKgaj5rlZTaWHD844YdgnpV1gjJR+KnWxFA3qSGYgBE+PW hp5a/LzGJtvYg== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Conor Dooley Subject: [PATCH v2 5/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the missing I3C power source option Date: Thu, 28 May 2026 11:04:37 +0300 Message-ID: <20260528080439.615958-6-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528080439.615958-1-claudiu.beznea@kernel.org> References: <20260528080439.615958-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The I3C pins on the Renesas RZ/G3S SoC can be powered at either 1.2V or 1.8V. Document the missing 1.2V power source option. Acked-by: Conor Dooley Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang --- Changes in v2: - collected tags .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index fb1fe1ea759f..32864c9add4a 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -129,7 +129,7 @@ additionalProperties: enum: [ 33, 50, 66, 100 ] power-source: description: I/O voltage in millivolt. - enum: [ 1800, 2500, 3300 ] + enum: [ 1200, 1800, 2500, 3300 ] slew-rate: true gpio-hog: true gpios: true --=20 2.43.0 From nobody Mon Jun 8 16:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2C2B35E1BA; Thu, 28 May 2026 08:05:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955520; cv=none; b=lZ/vnfF9E8hQN1NDg85WV3kIhYVYg+f/wn3FvyT6bSZM+TZKrwBn9opk+iP8sjAE5ZcyvaJ8opidZN/qv6gO8tU6Z8ONWJp6Zp4aLsAvL9qbnuhwk3N4Yhnu6HURqYL2NSrlsjc4CDv+OGVz5hfNSBxIqQJeaGHTbraRUXPNZpU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779955520; c=relaxed/simple; bh=zS0lJ0OfCR3pconmHwSVqLpPgxKwnfhez0N8CRD5N14=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f6W9AjqM5oqfaamovEAHfJZPuqMdFiL5LPPXJdmVqMF8dgQqkcw0Fip1xfANVoOxgT8oMgCNxk/QeQDHg30ddZu8Stz/Cov5Wp6G0udqTqN7OM+Ihopz7X4+Wku1ZsMTtdaB+vq3vNECj9TRQplBGO6quI1Zdo38v3i04S6A4qc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ta7YrQRc; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ta7YrQRc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85A0B1F00A3A; Thu, 28 May 2026 08:05:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779955514; bh=W9b5OaxFwZGIe6NN2bPs6FOi8xA4qK8HSCIxEq57fXc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Ta7YrQRciM18s5HUGj10E4ImE0KOuT7OViBcsgw2JlJzSA2a5O4DJEuJQ1pgCKNgJ O3RSH1tfEawLObgfKbQKDcmijrmACQGxMMTKbELA/kPOsxKIr+jIoYI+u7vcfKPUvK NEXxFeTy4GLX0FD8ps4kovm6iNJ/6/rmhl8/y27/hDEP2Qy/3RCTEuWUd5/ENpIpi/ 36J22W5Hqre68dK2ZTb54z1T/RpNJzSaOrupdifYuqZbrspk58dEz0IYlQpNPit1Sf IairYnVZUke7iz7XZxgzHFpjhUEXmuKdESnRQCRg4ADPTt9yMroVJ83hKhzzSN0/Jm HjTk6WgrWxQYA== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 6/7] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source Date: Thu, 28 May 2026 11:04:38 +0300 Message-ID: <20260528080439.615958-7-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528080439.615958-1-claudiu.beznea@kernel.org> References: <20260528080439.615958-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The pin controller provides a register to select between these two options. Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang --- Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 517001145bd0..68329b6c6649 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -69,6 +69,7 @@ #define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ +#define PIN_CFG_IO_VMC_I3C BIT(22) =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -186,6 +187,9 @@ #define PVDD_3300 0 /* I/O domain voltage >=3D 3.3V */ #define PVDD_MASK 0x3 =20 +#define PVDD_I3C_1200 1 /* I3C I/O domain voltage 1.2V */ +#define PVDD_I3C_1800 0 /* I3C I/O domain voltage 1.8V */ + #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2= H(P) */ @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_= items[] =3D { * @oen: OEN register offset * @qspi: QSPI register offset * @other_poc: OTHER_POC register offset + * @i3c_set: I3C_SET register offset */ struct rzg2l_register_offsets { u16 pwpr; @@ -265,6 +270,7 @@ struct rzg2l_register_offsets { u16 oen; u16 qspi; u16 other_poc; + u16 i3c_set; }; =20 /** @@ -272,6 +278,7 @@ struct rzg2l_register_offsets { * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + * @i3c_set_poc: I3C_SET_POC mask */ struct rzg2l_register_masks { union { @@ -281,6 +288,11 @@ struct rzg2l_register_masks { u8 other_poc_pvdd1833_oth_iso_poc; u8 other_poc_wdtovf_n_poc; }; + + /* RZ/G3S masks */ + struct { + u8 i3c_set_poc; + }; }; }; =20 @@ -391,6 +403,7 @@ struct rzg2l_pinctrl_pin_settings { * @oen: Output Enable register cache * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache + * @i3c_set: I3C_SET register cache */ struct rzg2l_pinctrl_reg_cache { u8 *p; @@ -409,6 +422,7 @@ struct rzg2l_pinctrl_reg_cache { u8 oen; u8 other_poc; u8 qspi; + u8 i3c_set; }; =20 struct rzg2l_pinctrl { @@ -441,6 +455,7 @@ struct rzg2l_pinctrl { }; =20 static const u16 available_ps[] =3D { 1800, 2500, 3300 }; +static const u16 available_i3c_ps[] =3D { 1200, 1800 }; =20 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, u64 pincfg, @@ -1101,12 +1116,28 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l= _register_offsets *regs, *mask =3D masks->other_poc_wdtovf_n_poc; return 0; } + if (caps & PIN_CFG_IO_VMC_I3C) { + *offset =3D regs->i3c_set; + *mask =3D masks->i3c_set_poc; + return 0; + } =20 return -EINVAL; } =20 static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) { + if (caps & PIN_CFG_IO_VMC_I3C) { + switch (val) { + case PVDD_I3C_1200: + return 1200; + case PVDD_I3C_1800: + return 1800; + } + + return -EINVAL; + } + switch (val) { case PVDD_1800: return 1800; @@ -1121,6 +1152,19 @@ static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) =20 static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps) { + if (caps & PIN_CFG_IO_VMC_I3C) { + switch (ps) { + case 1200: + *val =3D PVDD_I3C_1200; + return 0; + case 1800: + *val =3D PVDD_I3C_1800; + return 0; + } + + return -EINVAL; + } + switch (ps) { case 1800: *val =3D PVDD_1800; @@ -1194,12 +1238,21 @@ static int rzg2l_set_power_source(struct rzg2l_pinc= trl *pctrl, u32 pin, u32 caps return 0; } =20 -static bool rzg2l_ps_is_supported(u16 ps) +static bool rzg2l_ps_is_supported(u16 ps, u32 caps) { - unsigned int i; + unsigned int i, len; + const u16 *array; =20 - for (i =3D 0; i < ARRAY_SIZE(available_ps); i++) { - if (available_ps[i] =3D=3D ps) + if (caps & PIN_CFG_IO_VMC_I3C) { + array =3D available_i3c_ps; + len =3D ARRAY_SIZE(available_i3c_ps); + } else { + array =3D available_ps; + len =3D ARRAY_SIZE(available_ps); + } + + for (i =3D 0; i < len; i++) { + if (array[i] =3D=3D ps) return true; } =20 @@ -1800,7 +1853,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, =20 /* Apply power source. */ if (settings.power_source !=3D pctrl->settings[_pin].power_source) { - ret =3D rzg2l_ps_is_supported(settings.power_source); + ret =3D rzg2l_ps_is_supported(settings.power_source, cfg); if (!ret) return -EINVAL; =20 @@ -2498,6 +2551,8 @@ static const struct rzg2l_dedicated_configs rzg3s_ded= icated_pins[] =3D { { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_C= FG_SOFT_PS) }, + { "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, + { "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_= VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN= | PIN_CFG_IO_VMC_SD0)) }, @@ -3717,6 +3772,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); if (regs->other_poc) cache->other_poc =3D readb(pctrl->base + regs->other_poc); + if (regs->i3c_set) + cache->i3c_set =3D readb(pctrl->base + regs->i3c_set); =20 if (pctrl->syscon) { int ret; @@ -3759,6 +3816,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) writeb(cache->qspi, pctrl->base + regs->qspi); if (regs->other_poc) writeb(cache->other_poc, pctrl->base + regs->other_poc); + if (regs->i3c_set) + writeb(cache->i3c_set, pctrl->base + regs->i3c_set); =20 raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3871,8 +3930,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .pwpr =3D 0x3000, .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, + .i3c_set =3D 0x301c, .oen =3D 0x3018, }, + .masks =3D { + .i3c_set_poc =3D BIT(2), + }, .iolh_groupa_ua =3D { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, --=20 2.43.0 From nobody Mon Jun 8 16:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C530136A37C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ip7gm32Z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DAD4D1F000E9; Thu, 28 May 2026 08:05:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779955518; bh=YwuM/0kb/7SjJbumekNnRVt6BwOm0F+PoXL/ynyf1MY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Ip7gm32ZLfEIACEZjJo9ydg0l3f1uHL+rXDNHKUqnepOnRXGyRuPgj7YsZ7Ie8rhY 09MWF8uNFJGCNaCUugikuM5HZpo/F9FGYXLcMUwOUVuly/mkm2AzCpkigiwnwT4HQK CmKsfelRT2I47EHRvHQKRCXwTm5ZAYPJPv3lCcgVHaResfKYcWWGaUTuvfZGyhmkaP hAyqiVSewkNwnT/TtP7eFBrrOxVjlRA/bJ/eryCDlGuCfugd1nioVfErN8uVD+iO7o u9Tqxk/2cNwy+xPFIpJIDROP7FhER+LiHNP3+bMeaCTEoUltMTVvC8QwRaUYjxNvN/ lBqseOTLS3iQw== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 7/7] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C Date: Thu, 28 May 2026 11:04:39 +0300 Message-ID: <20260528080439.615958-8-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528080439.615958-1-claudiu.beznea@kernel.org> References: <20260528080439.615958-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SMARC SoM board has a connector for I3C interface. Enable I3C. Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang --- Changes in v2: - dropped pinctrl sleep state .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 18 ++++++++++++++++++ .../boot/dts/renesas/rzg3s-smarc-switches.h | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index b45acfe6288a..af7357fe4655 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -168,6 +168,14 @@ a0 80 30 30 9c }; }; =20 +&i3c { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i3c_pins>; + i2c-scl-hz =3D <400000>; + i3c-scl-hz =3D <12500000>; + status =3D "okay"; +}; + &pcie_port0 { clocks =3D <&versa3 5>; clock-names =3D "ref"; @@ -302,6 +310,16 @@ mux { }; }; =20 + i3c_pins: i3c { + pins =3D "I3C_SDA", "I3C_SCL"; +#if SW_CONFIG4 =3D=3D SW_ON + power-source =3D <1200>; +#else + power-source =3D <1800>; +#endif + input-enable; + }; + sdhi0_pins: sd0 { data { pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm6= 4/boot/dts/renesas/rzg3s-smarc-switches.h index bbf908a5322c..9cccc87da057 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -25,9 +25,13 @@ * @SW_CONFIG3: * SW_OFF - SD2 is connected to SoC * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + * @SW_CONFIG4: + * SW_OFF - I3C voltage is 1.8V + * SW_ON - I3C voltage is 1.2V */ #define SW_CONFIG2 SW_OFF #define SW_CONFIG3 SW_ON +#define SW_CONFIG4 SW_OFF =20 /* * SW_OPT_MUX[x] switches' states: --=20 2.43.0