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Thu, 28 May 2026 03:07:28 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36b7e38af60sm575296a91.1.2026.05.28.03.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:07:28 -0700 (PDT) From: Imran Shaik Date: Thu, 28 May 2026 15:37:02 +0530 Subject: [PATCH v2 1/5] clk: qcom: gcc-qcm2290: Drop modelling of critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-shikra-dispcc-gpucc-v2-1-953f246a0fbb@oss.qualcomm.com> References: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> In-Reply-To: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: 2rT2KYpxOGxPh8OY14Vg3tfbZ5GqYP4g X-Authority-Analysis: v=2.4 cv=JMYLdcKb c=1 sm=1 tr=0 ts=6a1813e2 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=wO6r28kiU9IfGTHmw08A:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: 2rT2KYpxOGxPh8OY14Vg3tfbZ5GqYP4g X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwMiBTYWx0ZWRfX8jquxteFx9yM mg0XOHinD0aWaqpZfJfYbei4Ueu48ewwvOsd0PGEwjX1U2nZrlkygbR7TagS+nn9xWrVq/AW/Do bvjZDP/8DYSZMMojJwUBozj4FShpBzusd9fzqfrvMOwyn01sKOcwh2uoYqyX1DXoBdre2L29sE7 fqziQJzJ16ISPseqa0CBQUS+efbmUc5QXuETTt73WBGvOjWJTcQydeZ/85ciIXORqLOGJ3wHkJT vX+vQmVNaqvMawY9s8vPQ8gxkR/99fUgSV8DVW208Zs3kfVWHNA+53+KOOMdRozDvD7aFevh0tI OQIw0mZthUXO5EWSrGqa9D1YILQkGMIl+2p3L8cGdxk7hWv9pA6+Am07RhmUjV08acnWvQB0mux 8DrEH8/4ZFWFzy1enAItpOVNI18CBQY9yup9fHQKA4s+jdSt7q+6wB2zIr8wcwgp+avSar6yT4X 0OIiAuK4RMW2lo6x94A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 adultscore=0 phishscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280102 Drop the modelling of critical GCC clocks on QCM2290 SoC, and keep them enabled from probe as per the latest convention. This helps to drop the pm_clk handling in QCM2290 GPUCC driver, and the same can be re-used for Shikra SoC. Signed-off-by: Imran Shaik --- drivers/clk/qcom/gcc-qcm2290.c | 153 +++----------------------------------= ---- 1 file changed, 11 insertions(+), 142 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 6684cab63ae1160848631d1f8cd3c9cb691ff4ec..937db68a45b17b190aca7f3164e= 0dad8deabbfc8 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -1397,36 +1397,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk =3D= { }, }; =20 -static struct clk_branch gcc_camera_ahb_clk =3D { - .halt_reg =3D 0x17008, - .halt_check =3D BRANCH_HALT_DELAY, - .hwcg_reg =3D 0x17008, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x17008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk =3D { - .halt_reg =3D 0x17028, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x17028, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk =3D { .halt_reg =3D 0x58044, .halt_check =3D BRANCH_HALT, @@ -1825,22 +1795,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_c= lk =3D { }, }; =20 -static struct clk_branch gcc_disp_ahb_clk =3D { - .halt_reg =3D 0x1700c, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x1700c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x1700c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src =3D { .reg =3D 0x17058, .shift =3D 0, @@ -1899,20 +1853,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = =3D { }, }; =20 -static struct clk_branch gcc_disp_xo_clk =3D { - .halt_reg =3D 0x1702c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1702c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk =3D { .halt_reg =3D 0x4d000, .halt_check =3D BRANCH_HALT, @@ -1964,22 +1904,6 @@ static struct clk_branch gcc_gp3_clk =3D { }, }; =20 -static struct clk_branch gcc_gpu_cfg_ahb_clk =3D { - .halt_reg =3D 0x36004, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x36004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x36004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_cfg_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src =3D { .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { @@ -2012,19 +1936,6 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = =3D { }, }; =20 -static struct clk_branch gcc_gpu_iref_clk =3D { - .halt_reg =3D 0x36100, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x36100, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_iref_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_memnoc_gfx_clk =3D { .halt_reg =3D 0x3600c, .halt_check =3D BRANCH_VOTED, @@ -2439,22 +2350,6 @@ static struct clk_branch gcc_sdcc2_apps_clk =3D { }, }; =20 -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk =3D { - .halt_reg =3D 0x2b06c, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x2b06c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x79004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sys_noc_cpuss_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk =3D { .halt_reg =3D 0x1a080, .halt_check =3D BRANCH_HALT, @@ -2605,21 +2500,6 @@ static struct clk_branch gcc_venus_ctl_axi_clk =3D { }, }; =20 -static struct clk_branch gcc_video_ahb_clk =3D { - .halt_reg =3D 0x17004, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x17004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x17004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_video_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_video_axi0_clk =3D { .halt_reg =3D 0x1701c, .halt_check =3D BRANCH_HALT, @@ -2686,19 +2566,6 @@ static struct clk_branch gcc_video_venus_ctl_clk =3D= { }, }; =20 -static struct clk_branch gcc_video_xo_clk =3D { - .halt_reg =3D 0x17024, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x17024, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_video_xo_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct gdsc gcc_camss_top_gdsc =3D { .gdscr =3D 0x58004, .pd =3D { @@ -2775,8 +2642,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] =3D { [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] =3D &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] =3D &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] =3D &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] =3D &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] =3D &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] =3D &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] =3D &gcc_camss_camnoc_atb_clk.clkr, @@ -2817,22 +2682,18 @@ static struct clk_regmap *gcc_qcm2290_clocks[] =3D { [GCC_CAMSS_TOP_AHB_CLK] =3D &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] =3D &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_DISP_AHB_CLK] =3D &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] =3D &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] =3D &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] =3D &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] =3D &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] =3D &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &gcc_gpu_gpll0_div_clk_src.clkr, - [GCC_GPU_IREF_CLK] =3D &gcc_gpu_iref_clk.clkr, [GCC_GPU_MEMNOC_GFX_CLK] =3D &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] =3D &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_GPU_THROTTLE_CORE_CLK] =3D &gcc_gpu_throttle_core_clk.clkr, @@ -2870,7 +2731,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] =3D { [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] =3D &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, @@ -2887,13 +2747,11 @@ static struct clk_regmap *gcc_qcm2290_clocks[] =3D { [GCC_VCODEC0_AXI_CLK] =3D &gcc_vcodec0_axi_clk.clkr, [GCC_VENUS_AHB_CLK] =3D &gcc_venus_ahb_clk.clkr, [GCC_VENUS_CTL_AXI_CLK] =3D &gcc_venus_ctl_axi_clk.clkr, - [GCC_VIDEO_AHB_CLK] =3D &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] =3D &gcc_video_axi0_clk.clkr, [GCC_VIDEO_THROTTLE_CORE_CLK] =3D &gcc_video_throttle_core_clk.clkr, [GCC_VIDEO_VCODEC0_SYS_CLK] =3D &gcc_video_vcodec0_sys_clk.clkr, [GCC_VIDEO_VENUS_CLK_SRC] =3D &gcc_video_venus_clk_src.clkr, [GCC_VIDEO_VENUS_CTL_CLK] =3D &gcc_video_venus_ctl_clk.clkr, - [GCC_VIDEO_XO_CLK] =3D &gcc_video_xo_clk.clkr, [GPLL0] =3D &gpll0.clkr, [GPLL0_OUT_AUX2] =3D &gpll0_out_aux2.clkr, [GPLL1] =3D &gpll1.clkr, @@ -2990,6 +2848,17 @@ static int gcc_qcm2290_probe(struct platform_device = *pdev) if (ret) return ret; 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Thu, 28 May 2026 03:07:34 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36b7e38af60sm575296a91.1.2026.05.28.03.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:07:33 -0700 (PDT) From: Imran Shaik Date: Thu, 28 May 2026 15:37:03 +0530 Subject: [PATCH v2 2/5] dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-shikra-dispcc-gpucc-v2-2-953f246a0fbb@oss.qualcomm.com> References: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> In-Reply-To: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=VeXH+lp9 c=1 sm=1 tr=0 ts=6a1813e7 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=CblTgZ0dn44HXzuTGlIA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwMiBTYWx0ZWRfX5Wl+d7ZLnNed fTqgIvi3dR1cP7S1rGJiN6UPWPcUQqOm5k8OoIrRYq21nKb4QZgGbxqxO6cIcw5aGyCON9NpE8Y iDA/I/oY/M42XMRKRQ2n2Dr20kpqxQhREtXO7nILeMqlaI3JbAIpCszN0y72s81ZFe4AJXAkPl/ s+H4iMyJ29LzRnzb+AX1IfoCC+/AOxQD3hyQvDvBccd43IjOxkVh2LPNhSMoyUqwfiKKTKj3fj4 lPqUpLGow6SavdN5G2f4xb83JEdMsLrkQ07VFFPqmEHETaALj/SX0ouqeir7WuaCQpOZW3mX3Jm q5ccTmThxQlTu8IYAJW4NijkzJ+7AS7rhfzyOUURWolIHN/sPcmTgB0+pba9Zj4iH7z42SadjX3 Jg958HOo18j4iKxhaQzgUZm2Ao7ed6rS1GMHcFe8hOeELvN5i+KP9B6XFun677uYBbSPmZHG2t9 AUd85zgzNw3XA557zwQ== X-Proofpoint-GUID: Q9_MvvPYrrVXZ4TGhzAimeEBr4Vm635V X-Proofpoint-ORIG-GUID: Q9_MvvPYrrVXZ4TGhzAimeEBr4Vm635V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280102 The Qualcomm Shikra Display clock controller reuses the QCM2290 DISPCC, but has minor differences with the number of input clocks. Update the existing QCM2290 DISPCC bindings using conditional schema so that the QCM2290 requirements remain unchanged while accommodating the additional clocks required for Shikra. Signed-off-by: Imran Shaik --- .../bindings/clock/qcom,qcm2290-dispcc.yaml | 75 +++++++++++++++++-= ---- 1 file changed, 60 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml index 4a533b45eec2d8e7b866c3436bfe6f80fcd714fb..b24095814d9e67a355321d9013e= 144f245077322 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml @@ -17,25 +17,21 @@ description: | =20 properties: compatible: - const: qcom,qcm2290-dispcc + oneOf: + - items: + - enum: + - qcom,shikra-dispcc + - const: qcom,qcm2290-dispcc + - enum: + - qcom,qcm2290-dispcc =20 clocks: - items: - - description: Board XO source - - description: Board active-only XO source - - description: GPLL0 source from GCC - - description: GPLL0 div source from GCC - - description: Byte clock from DSI PHY - - description: Pixel clock from DSI PHY + minItems: 6 + maxItems: 9 =20 clock-names: - items: - - const: bi_tcxo - - const: bi_tcxo_ao - - const: gcc_disp_gpll0_clk_src - - const: gcc_disp_gpll0_div_clk_src - - const: dsi0_phy_pll_out_byteclk - - const: dsi0_phy_pll_out_dsiclk + minItems: 6 + maxItems: 9 =20 required: - compatible @@ -45,6 +41,55 @@ required: =20 allOf: - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + const: qcom,shikra-dispcc + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board active-only XO source + - description: GPLL0 source from GCC + - description: GPLL0 div source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Board sleep clock + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: gcc_disp_gpll0_clk_src + - const: gcc_disp_gpll0_div_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dsi1_phy_pll_out_byteclk + - const: dsi1_phy_pll_out_dsiclk + - const: sleep_clk + else: + properties: + clocks: + items: + - description: Board XO source + - description: Board active-only XO source + - description: GPLL0 source from GCC + - description: GPLL0 div source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: gcc_disp_gpll0_clk_src + - const: gcc_disp_gpll0_div_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk =20 unevaluatedProperties: false =20 --=20 2.34.1 From nobody Mon Jun 8 15:41:30 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FB913ADB9A for ; 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Thu, 28 May 2026 03:07:39 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36b7e38af60sm575296a91.1.2026.05.28.03.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:07:38 -0700 (PDT) From: Imran Shaik Date: Thu, 28 May 2026 15:37:04 +0530 Subject: [PATCH v2 3/5] dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-shikra-dispcc-gpucc-v2-3-953f246a0fbb@oss.qualcomm.com> References: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> In-Reply-To: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwMiBTYWx0ZWRfX/DIrtC9USCbX CXzqG8ZoUkLDZRLhuQWg0Xbqo2VCbKcn/Pq6pwoZYre5Cl63/v1TVRi2UjLUum7sYr6V9v/T6Ph yhTIGK70tIfLyjzrbkhPJhzwkWXB/K4MtqRSFtuyXCMyn1PFXG6Wkronr8GkoO/Kjh1rdlHgLHn r97s2/tRhhbawod2rXwmNf4FubWKubxSEKZvTsmOT8PaU6nZtr+pSSSULsGk6stHx2gRN06kmNn MW/PnGTnQbKHBAtCr/sdwfGIeE1NX1FRrKNNTxgU2rQHrvgozX843hmOKo4dNBbok6HLbyU0mnL mkHKFLTZjBBRqVGaFPrhEtNyW0uW8oAzGWMMoYi1cWC0beiBRon8AsBAN8YR6baQ14raljsHwBq DjlvTisHta5NOCFr0mwMKJmqLK0QuAZSRasb6TT/3TZmiQnBRKTh50M/PJD7CBA2wmH2YiqI3bc RFJhxFXtmfkWLor1fKg== X-Authority-Analysis: v=2.4 cv=PLo/P/qC c=1 sm=1 tr=0 ts=6a1813ec cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=tQxzmpfZ-Uf8aLjc2qgA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: TMTfrLe7gn3rFyzA9hKrs0JMAuz_5QwY X-Proofpoint-ORIG-GUID: TMTfrLe7gn3rFyzA9hKrs0JMAuz_5QwY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280102 The Qualcomm Shikra GPU clock controller is similar to QCM2290 GPUCC hardware block, with minor differences. Hence, reuse the QCM2290 GPUCC bindings for Qualcomm Shikra SoC. Signed-off-by: Imran Shaik --- Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yam= l b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml index 734880805c1b981a1c899d85435f83f4f3dd3ea9..1bd70d091fcd7b6d7805ac090aa= f840a415c123b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml @@ -18,7 +18,9 @@ description: | =20 properties: compatible: - const: qcom,qcm2290-gpucc + enum: + - qcom,qcm2290-gpucc + - qcom,shikra-gpucc =20 reg: maxItems: 1 --=20 2.34.1 From nobody Mon Jun 8 15:41:30 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61F2B3ADB9A for ; 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Update the parent data of mdss ahb/mdp clocks accordingly to the hardware clock plan and correct the GDSC *_wait_val and flags which are applicable for both QCM2290 and Shikra SoC, and add the support for DSI1 PHY source. Signed-off-by: Imran Shaik --- drivers/clk/qcom/dispcc-qcm2290.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qc= m2290.c index 6d88d067337fa132114b0d8666931b449f86de17..19c997f3fe9f197d2c252a9dd1e= 8169947200f5f 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021, Linaro Ltd. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include @@ -32,6 +33,8 @@ enum { P_GPLL0_OUT_DIV, P_GPLL0_OUT_MAIN, P_SLEEP_CLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, }; =20 static const struct pll_vco spark_vco[] =3D { @@ -84,7 +87,7 @@ static const struct clk_parent_data disp_cc_parent_data_1= [] =3D { =20 static const struct parent_map disp_cc_parent_map_2[] =3D { { P_BI_TCXO_AO, 0 }, - { P_GPLL0_OUT_DIV, 4 }, + { P_GPLL0_OUT_MAIN, 4 }, }; =20 static const struct clk_parent_data disp_cc_parent_data_2[] =3D { @@ -101,17 +104,19 @@ static const struct parent_map disp_cc_parent_map_3[]= =3D { static const struct clk_parent_data disp_cc_parent_data_3[] =3D { { .fw_name =3D "bi_tcxo" }, { .hw =3D &disp_cc_pll0.clkr.hw }, - { .fw_name =3D "gcc_disp_gpll0_clk_src" }, + { .fw_name =3D "gcc_disp_gpll0_div_clk_src" }, }; =20 static const struct parent_map disp_cc_parent_map_4[] =3D { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, }; =20 static const struct clk_parent_data disp_cc_parent_data_4[] =3D { { .fw_name =3D "bi_tcxo" }, { .fw_name =3D "dsi0_phy_pll_out_dsiclk" }, + { .fw_name =3D "dsi1_phy_pll_out_dsiclk" }, }; =20 static const struct parent_map disp_cc_parent_map_5[] =3D { @@ -153,8 +158,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk= _src =3D { =20 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] =3D { F(19200000, P_BI_TCXO_AO, 1, 0, 0), - F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0), - F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), { } }; =20 @@ -450,11 +455,14 @@ static const struct qcom_reset_map disp_cc_qcm2290_re= sets[] =3D { =20 static struct gdsc mdss_gdsc =3D { .gdscr =3D 0x3000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, .pd =3D { .name =3D "mdss_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D HW_CTRL, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; 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Thu, 28 May 2026 03:07:50 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36b7e38af60sm575296a91.1.2026.05.28.03.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:07:49 -0700 (PDT) From: Imran Shaik Date: Thu, 28 May 2026 15:37:06 +0530 Subject: [PATCH v2 5/5] clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-shikra-dispcc-gpucc-v2-5-953f246a0fbb@oss.qualcomm.com> References: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> In-Reply-To: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwMiBTYWx0ZWRfXyXurf+CyDQKQ YBQQnkLMIt97UXPdrG9ZE7vax5A688BDrl6HnasuVER0uIPz8JLQ1KFxU3STwNzIy4Sg3WiaCXg CY5uSA5SIT2qcZE5Q29+xbTEnV1tUd9l+hiyAMBWOFl4UQbMCPxaiYJ4pCtvIkp3j6xbCVOqxJD ErDZu0XXn6bXG9JG6Y7F+ZtH1S6p237rpndbiFPw4wFDY6fxdzFAO3Q4qjuiWTK5jPuuFCRx5JQ Ldxyz3r1LVcD7ecUaSZZLFuWoeAoKuoJ2K1vH+hdftZ4SAFHEhgyYLxSijNR5X5V45TNY9XTfob EqdArzxBgGHrzKKb9ErxiE3zWFL34UGaQ6v6P1xGaGS6MF1hgb9oFuzTZ5QZdJMsFgC87/tL6qD ncXrAfvj9mSAqshWQrKLBhF/IEW6pOfylixjFUalHXLSrC9goGAjU6ewP768ozHiGAyDxJBfZuc 5SZlPImvjtk3hKf2zIQ== X-Authority-Analysis: v=2.4 cv=PLo/P/qC c=1 sm=1 tr=0 ts=6a1813f7 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=h4tiyZWTG5MJAiqrTW8A:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: hQkccWnI-SFMH2a8-7EwsnDg51rO-LqA X-Proofpoint-ORIG-GUID: hQkccWnI-SFMH2a8-7EwsnDg51rO-LqA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280102 The Qualcomm Shikra GPU clock controller is similar to QCM2290 GPUCC hardware block, with minor differences. Drop modelling of critical clocks and keep them enabled at probe time, update the QCM2290 GPUCC driver to align with the latest common qcom_cc_probe() model. Update the GDSC *_wait_val and flags which are applicable for both QCM2290 and Shikra. Signed-off-by: Imran Shaik --- drivers/clk/qcom/gpucc-qcm2290.c | 174 +++++++++++++++++------------------= ---- 1 file changed, 74 insertions(+), 100 deletions(-) diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2= 290.c index dc369dff882e69a8c0acd260953d5fcae9453120..296afcbfe0c9e4e147dcbd8bca8= 07e8e4c50e185 100644 --- a/drivers/clk/qcom/gpucc-qcm2290.c +++ b/drivers/clk/qcom/gpucc-qcm2290.c @@ -2,14 +2,13 @@ /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2024, Linaro Limited + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include #include #include #include -#include -#include #include =20 #include @@ -20,7 +19,7 @@ #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" -#include "clk-regmap-phy-mux.h" +#include "common.h" #include "gdsc.h" #include "reset.h" =20 @@ -46,6 +45,7 @@ static const struct pll_vco huayra_vco[] =3D { { 600000000, 2200000000, 1 }, }; =20 +/* 710.4 MHz Configuration */ static const struct alpha_pll_config gpu_cc_pll0_config =3D { .l =3D 0x25, .config_ctl_val =3D 0x200d4828, @@ -57,11 +57,12 @@ static const struct alpha_pll_config gpu_cc_pll0_config= =3D { =20 static struct clk_alpha_pll gpu_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, .vco_table =3D huayra_vco, .num_vco =3D ARRAY_SIZE(huayra_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], .clkr =3D { - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_pll0", .parent_data =3D &(const struct clk_parent_data) { .index =3D DT_BI_TCXO, @@ -80,10 +81,10 @@ static const struct parent_map gpu_cc_parent_map_0[] = =3D { }; =20 static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { - { .index =3D DT_BI_TCXO, }, - { .hw =3D &gpu_cc_pll0.clkr.hw, }, - { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC, }, - { .index =3D DT_GCC_GPU_GPLL0_DIV_CLK_SRC, }, + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index =3D DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, }; =20 static const struct parent_map gpu_cc_parent_map_1[] =3D { @@ -95,11 +96,11 @@ static const struct parent_map gpu_cc_parent_map_1[] = =3D { }; =20 static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { - { .index =3D DT_BI_TCXO, }, - { .hw =3D &gpu_cc_pll0.clkr.hw, }, - { .hw =3D &gpu_cc_pll0.clkr.hw, }, - { .hw =3D &gpu_cc_pll0.clkr.hw, }, - { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC, }, + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC }, }; =20 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { @@ -113,7 +114,8 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { .hid_width =3D 5, .parent_map =3D gpu_cc_parent_map_0, .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_gmu_clk_src", .parent_data =3D gpu_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), @@ -133,32 +135,30 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk= _src[] =3D { { } }; =20 +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src_shikra[] =3D { + F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(537600000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1142400000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src =3D { .cmd_rcgr =3D 0x101c, .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D gpu_cc_parent_map_1, .freq_tbl =3D ftbl_gpu_cc_gx_gfx3d_clk_src, - .clkr.hw.init =3D &(struct clk_init_data){ + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_gx_gfx3d_clk_src", .parent_data =3D gpu_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, - }, -}; - -static struct clk_branch gpu_cc_ahb_clk =3D { - .halt_reg =3D 0x1078, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x1078, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpu_cc_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -168,7 +168,7 @@ static struct clk_branch gpu_cc_crc_ahb_clk =3D { .clkr =3D { .enable_reg =3D 0x107c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_crc_ahb_clk", .ops =3D &clk_branch2_ops, }, @@ -181,10 +181,10 @@ static struct clk_branch gpu_cc_cx_gfx3d_clk =3D { .clkr =3D { .enable_reg =3D 0x10a4, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_cx_gfx3d_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -199,10 +199,10 @@ static struct clk_branch gpu_cc_cx_gmu_clk =3D { .clkr =3D { .enable_reg =3D 0x1098, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_cx_gmu_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gpu_cc_gmu_clk_src.clkr.hw, + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -217,33 +217,20 @@ static struct clk_branch gpu_cc_cx_snoc_dvm_clk =3D { .clkr =3D { .enable_reg =3D 0x108c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_cx_snoc_dvm_clk", .ops =3D &clk_branch2_ops, }, }, }; =20 -static struct clk_branch gpu_cc_cxo_aon_clk =3D { - .halt_reg =3D 0x1004, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x1004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpu_cc_cxo_aon_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_cxo_clk =3D { .halt_reg =3D 0x109c, .halt_check =3D BRANCH_HALT, .clkr =3D { .enable_reg =3D 0x109c, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_cxo_clk", .ops =3D &clk_branch2_ops, }, @@ -256,10 +243,10 @@ static struct clk_branch gpu_cc_gx_gfx3d_clk =3D { .clkr =3D { .enable_reg =3D 0x1054, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_gx_gfx3d_clk", - .parent_data =3D &(const struct clk_parent_data){ - .hw =3D &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -270,11 +257,11 @@ static struct clk_branch gpu_cc_gx_gfx3d_clk =3D { =20 static struct clk_branch gpu_cc_sleep_clk =3D { .halt_reg =3D 0x1090, - .halt_check =3D BRANCH_VOTED, + .halt_check =3D BRANCH_HALT_VOTED, .clkr =3D { .enable_reg =3D 0x1090, .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ + .hw.init =3D &(const struct clk_init_data) { .name =3D "gpu_cc_sleep_clk", .ops =3D &clk_branch2_ops, }, @@ -297,11 +284,14 @@ static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_c= lk =3D { static struct gdsc gpu_cx_gdsc =3D { .gdscr =3D 0x106c, .gds_hw_ctrl =3D 0x1540, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, .pd =3D { .name =3D "gpu_cx_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D VOTABLE, + .flags =3D RETAIN_FF_ENABLE | VOTABLE, }; =20 static struct gdsc gpu_gx_gdsc =3D { @@ -309,21 +299,22 @@ static struct gdsc gpu_gx_gdsc =3D { .clamp_io_ctrl =3D 0x1508, .resets =3D (unsigned int []){ GPU_GX_BCR }, .reset_count =3D 1, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, .pd =3D { .name =3D "gpu_gx_gdsc", }, .parent =3D &gpu_cx_gdsc.pd, .pwrsts =3D PWRSTS_OFF_ON, - .flags =3D CLAMP_IO | AON_RESET | SW_RESET, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | SW_RESET | CLAMP_IO | AON_= RESET, }; =20 static struct clk_regmap *gpu_cc_qcm2290_clocks[] =3D { - [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] =3D &gpu_cc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, - [GPU_CC_CXO_AON_CLK] =3D &gpu_cc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, [GPU_CC_GX_GFX3D_CLK] =3D &gpu_cc_gx_gfx3d_clk.clkr, @@ -342,14 +333,30 @@ static struct gdsc *gpu_cc_qcm2290_gdscs[] =3D { [GPU_GX_GDSC] =3D &gpu_gx_gdsc, }; =20 +static struct clk_alpha_pll *gpu_cc_qcm2290_plls[] =3D { + &gpu_cc_pll0, +}; + +static const u32 gpu_cc_qcm2290_critical_cbcrs[] =3D { + 0x1078, /* GPU_CC_AHB_CLK */ + 0x1004, /* GPU_CC_CXO_AON_CLK */ + 0x1060, /* GPU_CC_GX_CXO_CLK */ +}; + static const struct regmap_config gpu_cc_qcm2290_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, .val_bits =3D 32, - .max_register =3D 0x9000, + .max_register =3D 0x7008, .fast_io =3D true, }; =20 +static const struct qcom_cc_driver_data gpu_cc_qcm2290_driver_data =3D { + .alpha_plls =3D gpu_cc_qcm2290_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_qcm2290_plls), + .clk_cbcrs =3D gpu_cc_qcm2290_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_qcm2290_critical_cbcrs), +}; =20 static const struct qcom_cc_desc gpu_cc_qcm2290_desc =3D { .config =3D &gpu_cc_qcm2290_regmap_config, @@ -359,55 +366,22 @@ static const struct qcom_cc_desc gpu_cc_qcm2290_desc = =3D { .num_resets =3D ARRAY_SIZE(gpu_cc_qcm2290_resets), .gdscs =3D gpu_cc_qcm2290_gdscs, .num_gdscs =3D ARRAY_SIZE(gpu_cc_qcm2290_gdscs), + .driver_data =3D &gpu_cc_qcm2290_driver_data, }; =20 static const struct of_device_id gpu_cc_qcm2290_match_table[] =3D { { .compatible =3D "qcom,qcm2290-gpucc" }, + { .compatible =3D "qcom,shikra-gpucc" }, { } }; MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table); =20 static int gpu_cc_qcm2290_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - regmap =3D qcom_cc_map(pdev, &gpu_cc_qcm2290_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D devm_pm_clk_create(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_clk_add(&pdev->dev, NULL); - if (ret < 0) { - dev_err(&pdev->dev, "failed to acquire ahb clock\n"); - return ret; - } - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - clk_huayra_2290_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); - - regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK = */ - - ret =3D qcom_cc_really_probe(&pdev->dev, &gpu_cc_qcm2290_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register display clock controller\n"); - goto out_pm_runtime_put; - } - -out_pm_runtime_put: - pm_runtime_put_sync(&pdev->dev); + if (device_is_compatible(&pdev->dev, "qcom,shikra-gpucc")) + gpu_cc_gx_gfx3d_clk_src.freq_tbl =3D ftbl_gpu_cc_gx_gfx3d_clk_src_shikra; =20 - return 0; + return qcom_cc_probe(pdev, &gpu_cc_qcm2290_desc); } =20 static struct platform_driver gpu_cc_qcm2290_driver =3D { --=20 2.34.1