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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-914f86fffddsm755148485a.12.2026.05.28.03.40.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:40:40 -0700 (PDT) From: Yongxing Mou Date: Thu, 28 May 2026 18:40:22 +0800 Subject: [PATCH v5 01/15] drm/msm/dp: remove cached drm_edid from panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-dp_mstclean-v5-1-a9221c1f1f3b@oss.qualcomm.com> References: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> In-Reply-To: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779964831; l=9149; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=8rfPXgL2BDNk/0IgYx87Y5lmOO0Suqj9LvpJBpt8Zac=; b=PjrvVBFjAgP+CuRRq8BAJEdz2CiqOt3sHEShuEBwMlFYyTvt/XXlcv+NpFv2bmqNsbfEyXWum PjiDSY+0RQDA2cvCH8HbLcaAXgWnKnaAMv3glHLWUVYGCJxMknUieLW X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwNiBTYWx0ZWRfX9jZNms3Z+l2V wy4Kgq/5Jd6nrumumsOaUerGOW+JWYPgOOO2kztsVIYTdcAOuHkIC9NZBuc42iLSQpNoBTCNUvh KeptAlyj+7G9ORM4Fg1Vj8WIP0j/b0ZHH/N4BvuMSCnhjYwd93c01uVprhSlGRmKnr4s+TP+hkY /hzktvkOYjiO+Uzs48wYS6lfh6sqPbQdfSp1LeNOqxfvLdXU7+8EKeIAeO9d92nlugY4UQFW4iD UMbE2807W7E8i6i9gDmI9opBao4FZULI6QwWUqNVnngxKT5ov9fnkaHkqpFd9wjO9oKnL2jllHv s/LtsWQC0p3Nt4GJwSS60UpccVfjAnXm5LwBGcps5fTdam6kFz4AqwYPpN6YPXRfEg+YiqaZ6Gf U7EmhrYXQNoPxDXKffDICCbPlJu3tylgv4mRoWjAiIVZDoYhbfvm3ecrbIOGwIyeU0ZvalpaRtW BqPWAO7+JEU1sRCG3tA== X-Authority-Analysis: v=2.4 cv=PLo/P/qC c=1 sm=1 tr=0 ts=6a181baa cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=yBxTOPed86Cp7mhl67IA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: AJq1UDy57-B35zu-6Hm3ye8ub4pGSL0g X-Proofpoint-ORIG-GUID: AJq1UDy57-B35zu-6Hm3ye8ub4pGSL0g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280106 The cached drm_edid seems unnecessary here. Use the drm_edid pointer directly in the plug stage instead of caching it. Remove the cached drm_edid and the corresponding oneliner to simplify the code. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 28 +++++++++++------- drivers/gpu/drm/msm/dp/dp_panel.c | 57 ++++-----------------------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 13 +++------ 3 files changed, 27 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 6800c628adb4..e3682c4d6077 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -269,6 +269,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) const struct drm_display_info *info =3D &connector->display_info; int rc =3D 0; u8 dpcd[DP_RECEIVER_CAP_SIZE]; + const struct drm_edid *drm_edid =3D NULL; =20 rc =3D drm_dp_read_dpcd_caps(dp->aux, dpcd); if (rc) @@ -276,10 +277,20 @@ static int msm_dp_display_process_hpd_high(struct msm= _dp_display_private *dp) =20 dp->link->lttpr_count =3D msm_dp_display_lttpr_init(dp, dpcd); =20 - rc =3D msm_dp_panel_read_sink_caps(dp->panel, connector); + rc =3D msm_dp_panel_read_link_caps(dp->panel, connector); if (rc) goto end; =20 + drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); + + if (!drm_edid) { + DRM_ERROR("panel edid read failed\n"); + /* check edid read fail is due to unplug */ + if (!msm_dp_aux_is_link_connected(dp->aux)) + return -ETIMEDOUT; + } + msm_dp_link_process_request(dp->link); =20 if (!dp->msm_dp_display.is_edp) @@ -291,7 +302,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) dp->msm_dp_display.psr_supported =3D dp->panel->psr_cap.version && psr_en= abled; =20 dp->audio_supported =3D info->has_audio; - msm_dp_panel_handle_sink_request(dp->panel); + msm_dp_panel_handle_sink_request(dp->panel, drm_edid); =20 /* * set sink to normal operation mode -- D0 @@ -302,6 +313,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) msm_dp_link_reset_phy_params_vx_px(dp->link); =20 end: + drm_edid_free(drm_edid); return rc; } =20 @@ -453,7 +465,7 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_displ= ay_private *dp) =20 /* Don't forget modes for eDP */ if (!dp->msm_dp_display.is_edp) - msm_dp_panel_unplugged(dp->panel, dp->msm_dp_display.connector); + drm_edid_connector_update(dp->msm_dp_display.connector, NULL); =20 /* triggered by irq_hdp with sink_count =3D 0 */ if (dp->link->sink_count =3D=3D 0) @@ -515,7 +527,6 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_= private *dp) static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_privat= e *dp) { msm_dp_audio_put(dp->audio); - msm_dp_panel_put(dp->panel); msm_dp_aux_put(dp->aux); } =20 @@ -566,7 +577,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); dp->ctrl =3D NULL; - goto error_ctrl; + goto error_link; } =20 dp->audio =3D msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base); @@ -574,13 +585,11 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) rc =3D PTR_ERR(dp->audio); pr_err("failed to initialize audio, rc =3D %d\n", rc); dp->audio =3D NULL; - goto error_ctrl; + goto error_link; } =20 return rc; =20 -error_ctrl: - msm_dp_panel_put(dp->panel); error_link: msm_dp_aux_put(dp->aux); error: @@ -744,8 +753,7 @@ int msm_dp_display_get_modes(struct msm_dp *dp) =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 - return msm_dp_panel_get_modes(msm_dp_display->panel, - dp->connector); + return drm_edid_connector_add_modes(msm_dp_display->panel->connector); } =20 bool msm_dp_display_check_video_test(struct msm_dp *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 6bb021820d7c..bde4a772d22c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -232,8 +232,8 @@ static u32 msm_dp_panel_get_supported_bpp(struct msm_dp= _panel *msm_dp_panel, return min_supported_bpp; } =20 -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector) { int rc, bw_code; int count; @@ -271,36 +271,9 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *m= sm_dp_panel, =20 rc =3D drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, msm_dp_panel->downstream_ports); - if (rc) - return rc; - - drm_edid_free(msm_dp_panel->drm_edid); - - msm_dp_panel->drm_edid =3D drm_edid_read_ddc(connector, &panel->aux->ddc); - - drm_edid_connector_update(connector, msm_dp_panel->drm_edid); - - if (!msm_dp_panel->drm_edid) { - DRM_ERROR("panel edid read failed\n"); - /* check edid read fail is due to unplug */ - if (!msm_dp_aux_is_link_connected(panel->aux)) { - rc =3D -ETIMEDOUT; - goto end; - } - } - -end: return rc; } =20 -void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - drm_edid_connector_update(connector, NULL); - drm_edid_free(msm_dp_panel->drm_edid); - msm_dp_panel->drm_edid =3D NULL; -} - u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_edid_bpp, u32 mode_pclk_khz) { @@ -324,20 +297,6 @@ u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm= _dp_panel, return bpp; } =20 -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - if (!msm_dp_panel) { - DRM_ERROR("invalid input\n"); - return -EINVAL; - } - - if (msm_dp_panel->drm_edid) - return drm_edid_connector_add_modes(connector); - - return 0; -} - static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) { edid +=3D edid->extensions; @@ -345,7 +304,8 @@ static u8 msm_dp_panel_get_edid_checksum(const struct e= did *edid) return edid->checksum; } =20 -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid) { struct msm_dp_panel_private *panel; =20 @@ -358,7 +318,7 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_pan= el *msm_dp_panel) =20 if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { /* FIXME: get rid of drm_edid_raw() */ - const struct edid *edid =3D drm_edid_raw(msm_dp_panel->drm_edid); + const struct edid *edid =3D drm_edid_raw(drm_edid); u8 checksum; =20 if (edid) @@ -755,10 +715,3 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *d= ev, struct drm_dp_aux *aux return msm_dp_panel; } =20 -void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel) -{ - if (!msm_dp_panel) - return; - - drm_edid_free(msm_dp_panel->drm_edid); -} diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 9173e90a5053..53b7b4463551 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -33,7 +33,6 @@ struct msm_dp_panel { u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; =20 struct msm_dp_link_info link_info; - const struct drm_edid *drm_edid; struct drm_connector *connector; struct msm_dp_display_mode msm_dp_mode; struct msm_dp_panel_psr psr_cap; @@ -47,15 +46,12 @@ struct msm_dp_panel { int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_b= us_en); -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); -void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector); u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_= max_bpp, u32 mode_pclk_khz); -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid); void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e); =20 void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel); @@ -94,5 +90,4 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev,= struct drm_dp_aux *aux struct msm_dp_link *link, void __iomem *link_base, void __iomem *p0_base); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-914f86fffddsm755148485a.12.2026.05.28.03.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:40:45 -0700 (PDT) From: Yongxing Mou Date: Thu, 28 May 2026 18:40:23 +0800 Subject: [PATCH v5 02/15] drm/msm/dp: drop deprecated .mode_set() and use .atomic_enable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-dp_mstclean-v5-2-a9221c1f1f3b@oss.qualcomm.com> References: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> In-Reply-To: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779964831; l=8155; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=HuWHEfgETeqeFInaSeDlkVr7MomHzKqKAmZIdQ6wMSs=; b=gHkSlwsNKGcvvmq9q0F1pynj7w6t1SL+SYP4oaAUT7blSsyEKHc0w5L+cmEtMgVdo2DJdRTRj akWuviaWo6mCPCiWaHZbmGb+B77sAD8MzGYyzVJwYbSoVIKoM8f2iY4 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: F8iDHdWDWmKg0-8vLicNDILf5hiBiVO7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwNiBTYWx0ZWRfX4ozCvG28CfPg +E0Qn0YSKX8MjcmJRB2DkkOuln0V4Z/O3QjR/EZ6z69LNiAg2AxPQD7cpewX9MK6Pj0UTqQrOsS 0HPnldjhFd55yGCW6OposiU9wjQpk8gGJobnPD7WfKI77+LYc2BVw5IdVZ8LUn2c95MBlUDf4Vl Vx75JyoaMTUCHvQgmuEh6e3Zmm/v+VMKkA7ycMusFBJt1NM61BX2mcBUmYMv/j4NfcBjs2XvWRQ t1sCceinZVU47ojmcxNApdPEoGluDC7ckcFu2vRUCEcmcHKG8tQkmHQBp6UUatkXdf6rm9afMK7 WodMuPiCF5fdDC3/KcApVr6+1LA02UHSoFu9ok0MZwqWfR2cGeEB6cbvt+dbwoP8VZ4wmlzP7If dgfFu2W+GoVJhp8Z75XjxuwyOke+jTAryyQPY43MR05Fiz/Iyqk6FiI7Yf2xYRTHw1mCAftQ4nG rtZ/yiv7moX9Wb+HkYQ== X-Proofpoint-ORIG-GUID: F8iDHdWDWmKg0-8vLicNDILf5hiBiVO7 X-Authority-Analysis: v=2.4 cv=Eo7iaycA c=1 sm=1 tr=0 ts=6a181baf cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=ohAeICWEHyx3i1rom8gA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280106 The bridge .mode_set() callback is deprecated. Remove it and move all mode setup logic to .atomic_enable(), where the adjusted_mode is available from the atomic CRTC state. Drop msm_dp_mode from msm_dp_display_private and store the mode directly in the panel, as it was only used as a temporary cache. Both changes are limited to msm_dp_display_set_mode and are kept in a single patch. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 81 ++++++++++++++-------------------= ---- drivers/gpu/drm/msm/dp/dp_drm.c | 2 - drivers/gpu/drm/msm/dp/dp_drm.h | 3 -- 3 files changed, 31 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e3682c4d6077..181d238addfc 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -63,7 +63,6 @@ struct msm_dp_display_private { struct msm_dp_panel *panel; struct msm_dp_ctrl *ctrl; =20 - struct msm_dp_display_mode msm_dp_mode; struct msm_dp msm_dp_display; =20 /* wait for audio signaling */ @@ -597,16 +596,33 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) } =20 static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, - struct msm_dp_display_mode *mode) + const struct drm_display_mode *adjusted_mode, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *dp; + u32 bpp; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - drm_mode_copy(&dp->panel->msm_dp_mode.drm_mode, &mode->drm_mode); - dp->panel->msm_dp_mode.bpp =3D mode->bpp; - dp->panel->msm_dp_mode.out_fmt_is_yuv_420 =3D mode->out_fmt_is_yuv_420; - msm_dp_panel_init_panel_info(dp->panel); + drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); + if (msm_dp_display_check_video_test(msm_dp_display)) + bpp =3D msm_dp_display_get_test_bpp(msm_dp_display); + else + bpp =3D msm_dp_panel->connector->display_info.bpc * 3; + + msm_dp_panel->msm_dp_mode.bpp =3D bpp ? bpp : 24; /* Default bpp */ + msm_dp_panel->msm_dp_mode.v_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); + msm_dp_panel->msm_dp_mode.h_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 =3D + drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mo= de) && + msm_dp_panel->vsc_sdp_supported; + msm_dp_panel_init_panel_info(msm_dp_panel); + + /* populate wide_bus_support to different layers */ + dp->ctrl->wide_bus_en =3D + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 ? false : dp->wide_bus_supp= orted; return 0; } =20 @@ -1309,7 +1325,7 @@ bool msm_dp_wide_bus_available(const struct msm_dp *m= sm_dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - if (dp->msm_dp_mode.out_fmt_is_yuv_420) + if (dp->panel->msm_dp_mode.out_fmt_is_yuv_420) return false; =20 return dp->wide_bus_supported; @@ -1365,15 +1381,19 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; int rc =3D 0; struct msm_dp_display_private *msm_dp_display; bool force_link_train =3D false; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - if (!msm_dp_display->msm_dp_mode.drm_mode.clock) { - DRM_ERROR("invalid params\n"); + + crtc =3D drm_atomic_get_new_crtc_for_encoder(state, + drm_bridge->encoder); + if (!crtc) return; - } + crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); =20 if (dp->is_edp) msm_dp_hpd_plug_handle(msm_dp_display); @@ -1386,7 +1406,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *d= rm_bridge, if (msm_dp_display->link->sink_count =3D=3D 0) return; =20 - rc =3D msm_dp_display_set_mode(dp, &msm_dp_display->msm_dp_mode); + rc =3D msm_dp_display_set_mode(dp, &crtc_state->adjusted_mode, msm_dp_dis= play->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); return; @@ -1446,45 +1466,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_br= idge *drm_bridge, pm_runtime_put_sync(&dp->pdev->dev); } =20 -void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; - struct msm_dp_display_private *msm_dp_display; - struct msm_dp_panel *msm_dp_panel; - - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - msm_dp_panel =3D msm_dp_display->panel; - - memset(&msm_dp_display->msm_dp_mode, 0x0, sizeof(struct msm_dp_display_mo= de)); - - if (msm_dp_display_check_video_test(dp)) - msm_dp_display->msm_dp_mode.bpp =3D msm_dp_display_get_test_bpp(dp); - else /* Default num_components per pixel =3D 3 */ - msm_dp_display->msm_dp_mode.bpp =3D dp->connector->display_info.bpc * 3; - - if (!msm_dp_display->msm_dp_mode.bpp) - msm_dp_display->msm_dp_mode.bpp =3D 24; /* Default bpp */ - - drm_mode_copy(&msm_dp_display->msm_dp_mode.drm_mode, adjusted_mode); - - msm_dp_display->msm_dp_mode.v_active_low =3D - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); - - msm_dp_display->msm_dp_mode.h_active_low =3D - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); - - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 =3D - drm_mode_is_420_only(&dp->connector->display_info, adjusted_mode) && - msm_dp_panel->vsc_sdp_supported; - - /* populate wide_bus_support to different layers */ - msm_dp_display->ctrl->wide_bus_en =3D - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display-= >wide_bus_supported; -} - void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(bridge); diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index b659d22f5f28..6ac5bac903d9 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -56,7 +56,6 @@ static const struct drm_bridge_funcs msm_dp_bridge_ops = =3D { .atomic_enable =3D msm_dp_bridge_atomic_enable, .atomic_disable =3D msm_dp_bridge_atomic_disable, .atomic_post_disable =3D msm_dp_bridge_atomic_post_disable, - .mode_set =3D msm_dp_bridge_mode_set, .mode_valid =3D msm_dp_bridge_mode_valid, .get_modes =3D msm_dp_bridge_get_modes, .detect =3D msm_dp_bridge_detect, @@ -233,7 +232,6 @@ static const struct drm_bridge_funcs msm_edp_bridge_ops= =3D { .atomic_enable =3D msm_edp_bridge_atomic_enable, .atomic_disable =3D msm_edp_bridge_atomic_disable, .atomic_post_disable =3D msm_edp_bridge_atomic_post_disable, - .mode_set =3D msm_dp_bridge_mode_set, .mode_valid =3D msm_edp_bridge_mode_valid, .atomic_reset =3D drm_atomic_helper_bridge_reset, .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_dr= m.h index 041aa026ae2e..4bd788ea05d5 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -36,9 +36,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge = *drm_bridge, enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode); 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Pass adjusted_mode and bpp as parameters to msm_dp_panel_init_panel_info() and move the assignments inside it. Suggested-by: Dmitry Baryshkov Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 11 +---------- drivers/gpu/drm/msm/dp/dp_panel.c | 18 +++++++++++++++--- drivers/gpu/drm/msm/dp/dp_panel.h | 4 +++- 3 files changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 181d238addfc..f33c754b83c3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -604,21 +604,12 @@ static int msm_dp_display_set_mode(struct msm_dp *msm= _dp_display, =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); if (msm_dp_display_check_video_test(msm_dp_display)) bpp =3D msm_dp_display_get_test_bpp(msm_dp_display); else bpp =3D msm_dp_panel->connector->display_info.bpc * 3; =20 - msm_dp_panel->msm_dp_mode.bpp =3D bpp ? bpp : 24; /* Default bpp */ - msm_dp_panel->msm_dp_mode.v_active_low =3D - !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); - msm_dp_panel->msm_dp_mode.h_active_low =3D - !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); - msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 =3D - drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mo= de) && - msm_dp_panel->vsc_sdp_supported; - msm_dp_panel_init_panel_info(msm_dp_panel); + msm_dp_panel_init_panel_info(msm_dp_panel, adjusted_mode, bpp ? bpp : 24); =20 /* populate wide_bus_support to different layers */ dp->ctrl->wide_bus_en =3D diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index bde4a772d22c..e76dad0f6663 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -647,15 +647,27 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_= dp_panel, bool wide_bus_en) return 0; } =20 -int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) +int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel, + const struct drm_display_mode *adjusted_mode, + u32 bpp) { struct drm_display_mode *drm_mode; struct msm_dp_panel_private *panel; =20 - drm_mode =3D &msm_dp_panel->msm_dp_mode.drm_mode; - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); =20 + drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); + msm_dp_panel->msm_dp_mode.bpp =3D bpp; + msm_dp_panel->msm_dp_mode.v_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); + msm_dp_panel->msm_dp_mode.h_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 =3D + drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mo= de) && + msm_dp_panel->vsc_sdp_supported; + + drm_mode =3D &msm_dp_panel->msm_dp_mode.drm_mode; + /* * print resolution info as this is a result * of user initiated action of cable connection diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 53b7b4463551..4519ac374220 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -43,7 +43,9 @@ struct msm_dp_panel { u32 max_bw_code; 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Currently, msm_dp_ctrl_config_ctrl() configures all of them together. Separate the configuration into link parts and stream parts to support MST. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 47 +++++++++++++++++++++++++++---------= ---- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 86ef8c89ad44..cc00e8d2d6c7 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -388,26 +388,45 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp= _ctrl) drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); } =20 -static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ct= rl, + struct msm_dp_panel *msm_dp_panel) { u32 config =3D 0, tbd; + + /* + * RMW: in SST, config_ctrl_link and config_ctrl_streams are called + * sequentially on the same thread. In MST, caller holds mst_lock. + */ + config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) + config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ + + tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, + msm_dp_panel->msm_dp_mode.bpp); + + config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; + + if (msm_dp_panel->psr_cap.version) + config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; + + drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); + + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); +} + +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) +{ + u32 config =3D 0; const u8 *dpcd =3D ctrl->panel->dpcd; =20 /* Default-> LSCLK DIV: 1/4 LCLK */ config |=3D (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); =20 - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) - config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ - /* Scrambler reset enable */ if (drm_dp_alternate_scrambler_reset_cap(dpcd)) config |=3D DP_CONFIGURATION_CTRL_ASSR; =20 - tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, - ctrl->panel->msm_dp_mode.bpp); - - config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; - /* Num of Lanes */ config |=3D ((ctrl->link->link_params.num_lanes - 1) << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); @@ -421,10 +440,7 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl= _private *ctrl) config |=3D DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; config |=3D DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; =20 - if (ctrl->panel->psr_cap.version) - config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; - - drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", config); + drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=3D0x%x\n", config); =20 msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } @@ -450,7 +466,8 @@ static void msm_dp_ctrl_configure_source_params(struct = msm_dp_ctrl_private *ctrl msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); =20 - msm_dp_ctrl_config_ctrl(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); 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Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index cc00e8d2d6c7..d4f48669541a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -459,17 +459,13 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ct= rl_private *ctrl) ln_mapping); } =20 -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctr= l, + struct msm_dp_panel *msm_dp_panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; =20 - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl_link(ctrl); - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); - - test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); 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Move the link setup out of it so MST can program link and stream settings separately. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index d4f48669541a..b22b3a0df313 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -483,10 +483,6 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_= dp_ctrl_private *ctrl, =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) { - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl_link(ctrl); msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); =20 msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); @@ -2552,6 +2548,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, bool force_link_train */ reinit_completion(&ctrl->video_comp); =20 + msm_dp_ctrl_lane_mapping(ctrl); + msm_dp_setup_peripheral_flush(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); 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Move it into individual helpers so that the helpers can be called wherever necessary. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 81 +++++++++++++++++++++---------------= ---- 1 file changed, 42 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index b22b3a0df313..d502ddbc4bdf 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2172,6 +2172,42 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct= msm_dp_ctrl_private *ctrl) return success; } =20 +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate) +{ + int ret; + + ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + if (ret) { + DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); + return ret; + } + + if (ctrl->stream_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); + } else { + ret =3D clk_prepare_enable(ctrl->pixel_clk); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); + return ret; + } + ctrl->stream_clks_on =3D true; + } + + return ret; +} + +static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (ctrl->stream_clks_on) { + clk_disable_unprepare(ctrl->pixel_clk); + ctrl->stream_clks_on =3D false; + } +} + static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private= *ctrl) { int ret; @@ -2197,22 +2233,7 @@ static int msm_dp_ctrl_process_phy_test_request(stru= ct msm_dp_ctrl_private *ctrl } =20 pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); - return ret; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - return ret; - } - ctrl->stream_clks_on =3D true; - } + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); =20 msm_dp_ctrl_send_phy_test_pattern(ctrl); =20 @@ -2515,26 +2536,13 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); if (ret) { DRM_ERROR("Failed to start link clocks. ret=3D%d\n", ret); - goto end; + return ret; } } =20 - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); - goto end; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - goto end; - } - ctrl->stream_clks_on =3D true; - } + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + if (ret) + return ret; =20 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) msm_dp_ctrl_link_retrain(ctrl); @@ -2573,7 +2581,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, bool force_link_train drm_dbg_dp(ctrl->drm_dev, "mainlink %s\n", mainlink_ready ? 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Split these two parts into prepare/enable APIs, to support MST bridges_enable insert the MST payloads funcs between enable stream_clks and program register. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 48 +++++++++++------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 105 +++++++++++++++++++++++---------= ---- 3 files changed, 102 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index d502ddbc4bdf..d8297ebf7d56 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2506,27 +2506,19 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ct= rl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train) +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) { int ret =3D 0; - bool mainlink_ready =3D false; struct msm_dp_ctrl_private *ctrl; - unsigned long pixel_rate; - unsigned long pixel_rate_orig; =20 if (!msm_dp_ctrl) return -EINVAL; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate =3D pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.cloc= k; - - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) - pixel_rate >>=3D 1; - - drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%lu\n", - ctrl->link->link_params.rate, - ctrl->link->link_params.num_lanes, pixel_rate); + drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d\n", + ctrl->link->link_params.rate, + ctrl->link->link_params.num_lanes); =20 drm_dbg_dp(ctrl->drm_dev, "core_clk_on=3D%d link_clk_on=3D%d stream_clk_on=3D%d\n", @@ -2540,16 +2532,40 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train } } =20 - ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); - if (ret) - return ret; - if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) msm_dp_ctrl_link_retrain(ctrl); =20 /* stop txing train pattern to end link training */ msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); =20 + return ret; +} + +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +{ + int ret =3D 0; + bool mainlink_ready =3D false; + struct msm_dp_ctrl_private *ctrl; + unsigned long pixel_rate; + unsigned long pixel_rate_orig; + + if (!msm_dp_ctrl) + return -EINVAL; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate =3D pixel_rate_orig; + + if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + pixel_rate >>=3D 1; + + drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); + + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + if (ret) + return ret; + /* * Set up transfer unit values and set controller state to send * video. diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index f68bee62713f..1497f1a8fc2f 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index f33c754b83c3..cf859f880943 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -617,7 +617,40 @@ static int msm_dp_display_set_mode(struct msm_dp *msm_= dp_display, return 0; } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp, bool f= orce_link_train) +static int msm_dp_display_prepare_link(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + int rc =3D 0; + bool force_link_train =3D false; + + drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); + + if (msm_dp_display->is_edp) + msm_dp_hpd_plug_handle(dp); + + rc =3D pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); + if (rc) { + DRM_ERROR("failed to pm_runtime_resume\n"); + return rc; + } + + if (dp->link->sink_count =3D=3D 0) + return rc; + + if (!msm_dp_display->power_on) { + msm_dp_display_host_phy_init(dp); + force_link_train =3D true; + } + + rc =3D msm_dp_ctrl_on_link(dp->ctrl); + if (rc) + DRM_ERROR("Failed link training (rc=3D%d)\n", rc); + // TODO: schedule drm_connector_set_link_status_property() + + return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); +} + +static int msm_dp_display_enable(struct msm_dp_display_private *dp) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -628,7 +661,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp, bool force_l return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, force_link_train); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -658,13 +691,10 @@ static int msm_dp_display_post_enable(struct msm_dp *= msm_dp_display) return 0; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static void msm_dp_display_audio_notify_disable(struct msm_dp_display_priv= ate *dp) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 - if (!msm_dp_display->power_on) - return 0; - /* wait only if audio was enabled */ if (msm_dp_display->audio_enabled) { /* signal the disconnect event */ @@ -675,6 +705,14 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp) } =20 msm_dp_display->audio_enabled =3D false; +} + +static int msm_dp_display_disable(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + if (!msm_dp_display->power_on) + return 0; =20 if (dp->link->sink_count =3D=3D 0) { /* @@ -1371,14 +1409,13 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, struct drm_atomic_commit *state) { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; + struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int rc =3D 0; - struct msm_dp_display_private *msm_dp_display; - bool force_link_train =3D false; + struct msm_dp_display_private *dp; =20 - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 crtc =3D drm_atomic_get_new_crtc_for_encoder(state, drm_bridge->encoder); @@ -1386,44 +1423,29 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, return; crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); =20 - if (dp->is_edp) - msm_dp_hpd_plug_handle(msm_dp_display); - - if (pm_runtime_resume_and_get(&dp->pdev->dev)) { - DRM_ERROR("failed to pm_runtime_resume\n"); - return; - } - - if (msm_dp_display->link->sink_count =3D=3D 0) - return; - - rc =3D msm_dp_display_set_mode(dp, &crtc_state->adjusted_mode, msm_dp_dis= play->panel); + rc =3D msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode= , dp->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); return; } =20 - if (!dp->power_on) { - msm_dp_display_host_phy_init(msm_dp_display); - force_link_train =3D true; - } - - rc =3D msm_dp_ctrl_on_link(msm_dp_display->ctrl); + rc =3D msm_dp_display_prepare_link(dp); if (rc) { - DRM_ERROR("Failed link training (rc=3D%d)\n", rc); - // TODO: schedule drm_connector_set_link_status_property() + DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); return; } =20 - msm_dp_display_enable(msm_dp_display, force_link_train); + rc =3D msm_dp_display_enable(dp); + if (rc) + DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 - rc =3D msm_dp_display_post_enable(dp); + rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(msm_dp_display); + msm_dp_display_disable(dp); } =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); + drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -1438,6 +1460,15 @@ void msm_dp_bridge_atomic_disable(struct drm_bridge = *drm_bridge, msm_dp_ctrl_push_idle(msm_dp_display->ctrl); } =20 +static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + pm_runtime_put_sync(&msm_dp_display->pdev->dev); + + drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); +} + void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, struct drm_atomic_commit *state) { @@ -1450,11 +1481,11 @@ void msm_dp_bridge_atomic_post_disable(struct drm_b= ridge *drm_bridge, if (dp->is_edp) msm_dp_hpd_unplug_handle(msm_dp_display); =20 - msm_dp_display_disable(msm_dp_display); + msm_dp_display_audio_notify_disable(msm_dp_display); =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); 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However with a slight rework this can still be handled by keeping common paths same for regular and special case. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 19 +------------------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 3 files changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index d8297ebf7d56..fcce67df4660 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2600,7 +2600,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl) return ret; } =20 -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2608,23 +2608,6 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl = *msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(ctrl->panel); - - /* set dongle to D3 (power off) mode */ - msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); - - msm_dp_ctrl_mainlink_disable(ctrl); - - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on =3D false; - } - - dev_pm_opp_set_rate(ctrl->dev, 0); - msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); - - phy_power_off(phy); - /* aux channel down, reinit phy */ phy_exit(phy); phy_init(phy); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 1497f1a8fc2f..5d615f50d13b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,6 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); @@ -46,4 +45,5 @@ void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm= _dp_ctrl); void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); =20 +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index cf859f880943..b8dab3f8a7c2 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -714,12 +714,20 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) if (!msm_dp_display->power_on) return 0; =20 + msm_dp_panel_disable_vsc_sdp(dp->panel); + + /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) { /* * irq_hpd with sink_count =3D 0 * hdmi unplugged out of dongle */ - msm_dp_ctrl_off_link_stream(dp->ctrl); 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Drop the cache and pass panel explicitly to all stream-related dp_ctrl APIs. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 208 ++++++++++++++++++++------------= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 28 +++-- drivers/gpu/drm/msm/dp/dp_display.c | 24 ++--- 3 files changed, 146 insertions(+), 114 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index fcce67df4660..88b6f4b8a598 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -114,7 +114,6 @@ struct msm_dp_ctrl_private { struct drm_device *drm_dev; struct device *dev; struct drm_dp_aux *aux; - struct msm_dp_panel *panel; struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; @@ -202,7 +201,8 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux = *aux, /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ -void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); @@ -219,7 +219,7 @@ void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl) =20 if (!ctrl->hw_revision) { ctrl->hw_revision =3D msm_dp_read_ahb(ctrl, REG_DP_HW_VERSION); - ctrl->panel->hw_revision =3D ctrl->hw_revision; + panel->hw_revision =3D ctrl->hw_revision; } } =20 @@ -389,7 +389,7 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_c= trl) } =20 static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ct= rl, - struct msm_dp_panel *msm_dp_panel) + struct msm_dp_panel *panel) { u32 config =3D 0, tbd; =20 @@ -399,15 +399,15 @@ static void msm_dp_ctrl_config_ctrl_streams(struct ms= m_dp_ctrl_private *ctrl, */ config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); =20 - if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) + if (panel->msm_dp_mode.out_fmt_is_yuv_420) config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ =20 tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, - msm_dp_panel->msm_dp_mode.bpp); + panel->msm_dp_mode.bpp); =20 config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; =20 - if (msm_dp_panel->psr_cap.version) + if (panel->psr_cap.version) config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; =20 drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); @@ -415,10 +415,11 @@ static void msm_dp_ctrl_config_ctrl_streams(struct ms= m_dp_ctrl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } =20 -static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) { u32 config =3D 0; - const u8 *dpcd =3D ctrl->panel->dpcd; + const u8 *dpcd =3D panel->dpcd; =20 /* Default-> LSCLK DIV: 1/4 LCLK */ config |=3D (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); @@ -460,12 +461,12 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ct= rl_private *ctrl) } =20 static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctr= l, - struct msm_dp_panel *msm_dp_panel) + struct msm_dp_panel *panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; =20 test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, - msm_dp_panel->msm_dp_mode.bpp); + panel->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); =20 misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); @@ -481,13 +482,14 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm= _dp_ctrl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); } =20 -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, + struct msm_dp_panel *panel) { - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); + msm_dp_ctrl_config_ctrl_streams(ctrl, panel); =20 - msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); + msm_dp_ctrl_config_misc1_misc0(ctrl, panel); =20 - msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); + msm_dp_panel_timing_cfg(panel, ctrl->msm_dp_ctrl.wide_bus_en); } =20 /* @@ -1257,20 +1259,21 @@ static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_pri= vate *ctrl, } =20 static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctr= l, + struct msm_dp_panel *panel, struct msm_dp_vc_tu_mapping_table *tu_table) { struct msm_dp_tu_calc_input in; - struct drm_display_mode *drm_mode; + const struct drm_display_mode *drm_mode; =20 - drm_mode =3D &ctrl->panel->msm_dp_mode.drm_mode; + drm_mode =3D &panel->msm_dp_mode.drm_mode; =20 in.lclk =3D ctrl->link->link_params.rate / 1000; in.pclk_khz =3D drm_mode->clock; in.hactive =3D drm_mode->hdisplay; in.hporch =3D drm_mode->htotal - drm_mode->hdisplay; in.nlanes =3D ctrl->link->link_params.num_lanes; - in.bpp =3D ctrl->panel->msm_dp_mode.bpp; - in.pixel_enc =3D ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; + in.bpp =3D panel->msm_dp_mode.bpp; + in.pixel_enc =3D panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; in.dsc_en =3D 0; in.async_en =3D 0; in.fec_en =3D 0; @@ -1280,14 +1283,15 @@ static void msm_dp_ctrl_calc_tu_parameters(struct m= sm_dp_ctrl_private *ctrl, _dp_ctrl_calc_tu(ctrl, &in, tu_table); } =20 -static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) { u32 msm_dp_tu =3D 0x0; u32 valid_boundary =3D 0x0; u32 valid_boundary2 =3D 0x0; struct msm_dp_vc_tu_mapping_table tu_calc_table; =20 - msm_dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); + msm_dp_ctrl_calc_tu_parameters(ctrl, panel, &tu_calc_table); =20 msm_dp_tu |=3D tu_calc_table.tu_size_minus1; valid_boundary |=3D tu_calc_table.valid_boundary_link; @@ -1439,6 +1443,7 @@ static int msm_dp_ctrl_set_pattern_state_bit(struct m= sm_dp_ctrl_private *ctrl, } =20 static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step, enum drm_dp_phy dp_phy) { int delay_us; @@ -1447,7 +1452,7 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_ctr= l_private *ctrl, int const maximum_retries =3D 4; =20 delay_us =3D drm_dp_read_clock_recovery_delay(ctrl->aux, - ctrl->panel->dpcd, dp_phy, false); + panel->dpcd, dp_phy, false); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 @@ -1533,14 +1538,15 @@ static int msm_dp_ctrl_link_rate_down_shift(struct = msm_dp_ctrl_private *ctrl) return ret; } =20 -static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ct= rl) +static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ct= rl, + struct msm_dp_panel *panel) { =20 if (ctrl->link->link_params.num_lanes =3D=3D 1) return -1; =20 ctrl->link->link_params.num_lanes /=3D 2; - ctrl->link->link_params.rate =3D ctrl->panel->link_info.rate; + ctrl->link->link_params.rate =3D panel->link_info.rate; =20 ctrl->link->phy_params.p_level =3D 0; ctrl->link->phy_params.v_level =3D 0; @@ -1549,6 +1555,7 @@ static int msm_dp_ctrl_link_lane_down_shift(struct ms= m_dp_ctrl_private *ctrl) } =20 static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private = *ctrl, + struct msm_dp_panel *panel, enum drm_dp_phy dp_phy) { int delay_us; @@ -1556,11 +1563,12 @@ static void msm_dp_ctrl_clear_training_pattern(stru= ct msm_dp_ctrl_private *ctrl, msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE, dp_phy); =20 delay_us =3D drm_dp_read_channel_eq_delay(ctrl->aux, - ctrl->panel->dpcd, dp_phy, false); + panel->dpcd, dp_phy, false); fsleep(delay_us); } =20 static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step, enum drm_dp_phy dp_phy) { int delay_us; @@ -1571,16 +1579,16 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_c= trl_private *ctrl, u8 link_status[DP_LINK_STATUS_SIZE]; =20 delay_us =3D drm_dp_read_channel_eq_delay(ctrl->aux, - ctrl->panel->dpcd, dp_phy, false); + panel->dpcd, dp_phy, false); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_2; =20 - if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { + if (drm_dp_tps4_supported(panel->dpcd)) { pattern =3D DP_TRAINING_PATTERN_4; state_ctrl_bit =3D 4; - } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { + } else if (drm_dp_tps3_supported(panel->dpcd)) { pattern =3D DP_TRAINING_PATTERN_3; state_ctrl_bit =3D 3; } else { @@ -1617,18 +1625,19 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_c= trl_private *ctrl, } =20 static int msm_dp_ctrl_link_train_1_2(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step, enum drm_dp_phy dp_phy) { int ret; =20 - ret =3D msm_dp_ctrl_link_train_1(ctrl, training_step, dp_phy); + ret =3D msm_dp_ctrl_link_train_1(ctrl, panel, training_step, dp_phy); if (ret) { DRM_ERROR("link training #1 on phy %d failed. ret=3D%d\n", dp_phy, ret); return ret; } drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_p= hy); =20 - ret =3D msm_dp_ctrl_link_train_2(ctrl, training_step, dp_phy); + ret =3D msm_dp_ctrl_link_train_2(ctrl, panel, training_step, dp_phy); if (ret) { DRM_ERROR("link training #2 on phy %d failed. ret=3D%d\n", dp_phy, ret); return ret; @@ -1639,16 +1648,17 @@ static int msm_dp_ctrl_link_train_1_2(struct msm_dp= _ctrl_private *ctrl, } =20 static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step) { int i; int ret =3D 0; - const u8 *dpcd =3D ctrl->panel->dpcd; + const u8 *dpcd =3D panel->dpcd; u8 encoding[] =3D { 0, DP_SET_ANSI_8B10B }; u8 assr; struct msm_dp_link_info link_info =3D {0}; =20 - msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl, panel); =20 link_info.num_lanes =3D ctrl->link->link_params.num_lanes; link_info.rate =3D ctrl->link->link_params.rate; @@ -1671,8 +1681,8 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, for (i =3D ctrl->link->lttpr_count - 1; i >=3D 0; i--) { enum drm_dp_phy dp_phy =3D DP_PHY_LTTPR(i); =20 - ret =3D msm_dp_ctrl_link_train_1_2(ctrl, training_step, dp_phy); - msm_dp_ctrl_clear_training_pattern(ctrl, dp_phy); + ret =3D msm_dp_ctrl_link_train_1_2(ctrl, panel, training_step, dp_phy); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, dp_phy); =20 if (ret) break; @@ -1683,7 +1693,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, goto end; } =20 - ret =3D msm_dp_ctrl_link_train_1_2(ctrl, training_step, DP_PHY_DPRX); + ret =3D msm_dp_ctrl_link_train_1_2(ctrl, panel, training_step, DP_PHY_DPR= X); if (ret) { DRM_ERROR("link training on sink failed. ret=3D%d\n", ret); goto end; @@ -1696,6 +1706,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, } =20 static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step) { int ret =3D 0; @@ -1711,7 +1722,7 @@ static int msm_dp_ctrl_setup_main_link(struct msm_dp_= ctrl_private *ctrl, * a link training pattern, we have to first do soft reset. */ =20 - ret =3D msm_dp_ctrl_link_train(ctrl, training_step); + ret =3D msm_dp_ctrl_link_train(ctrl, panel, training_step); =20 return ret; } @@ -1810,11 +1821,12 @@ static void msm_dp_ctrl_link_clk_disable(struct msm= _dp_ctrl *msm_dp_ctrl) str_on_off(ctrl->core_clks_on)); } =20 -static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *= ctrl) +static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *= ctrl, + struct msm_dp_panel *panel) { int ret =3D 0; struct phy *phy =3D ctrl->phy; - const u8 *dpcd =3D ctrl->panel->dpcd; + const u8 *dpcd =3D panel->dpcd; =20 ctrl->phy_opts.dp.lanes =3D ctrl->link->link_params.num_lanes; ctrl->phy_opts.dp.link_rate =3D ctrl->link->link_params.rate / 100; @@ -1866,13 +1878,14 @@ static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl= _private *ctrl) msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); } =20 -void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); u32 cfg; =20 - if (!ctrl->panel->psr_cap.version) + if (!panel->psr_cap.version) return; =20 /* enable PSR1 function */ @@ -1887,12 +1900,13 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm= _dp_ctrl) drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); } =20 -void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter) +void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel, bool enter) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); =20 - if (!ctrl->panel->psr_cap.version) + if (!panel->psr_cap.version) return; =20 /* @@ -1962,7 +1976,8 @@ void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_= ctrl) phy_exit(phy); } =20 -static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *c= trl) +static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *c= trl, + struct msm_dp_panel *panel) { struct phy *phy =3D ctrl->phy; int ret =3D 0; @@ -1983,7 +1998,7 @@ static int msm_dp_ctrl_reinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) /* hw recommended delay before re-enabling clocks */ msleep(20); =20 - ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); + ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); if (ret) { DRM_ERROR("Failed to enable mainlink clks. ret=3D%d\n", ret); return ret; @@ -1992,7 +2007,8 @@ static int msm_dp_ctrl_reinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) return ret; } =20 -static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *c= trl) +static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *c= trl, + struct msm_dp_panel *panel) { struct phy *phy; =20 @@ -2000,7 +2016,7 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); =20 dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); @@ -2014,7 +2030,8 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) return 0; } =20 -static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) +static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) { int ret =3D 0; int training_step =3D DP_TRAINING_NONE; @@ -2024,11 +2041,11 @@ static int msm_dp_ctrl_link_maintenance(struct msm_= dp_ctrl_private *ctrl) ctrl->link->phy_params.p_level =3D 0; ctrl->link->phy_params.v_level =3D 0; =20 - ret =3D msm_dp_ctrl_setup_main_link(ctrl, &training_step); + ret =3D msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); if (ret) goto end; =20 - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 @@ -2208,7 +2225,8 @@ static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_c= trl *msm_dp_ctrl) } } =20 -static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private= *ctrl) +static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private= *ctrl, + struct msm_dp_panel *panel) { int ret; unsigned long pixel_rate; @@ -2224,15 +2242,15 @@ static int msm_dp_ctrl_process_phy_test_request(str= uct msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off(&ctrl->msm_dp_ctrl, panel); =20 - ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); + ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, panel); if (ret) { DRM_ERROR("failed to enable DP link controller\n"); return ret; } =20 - pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate =3D panel->msm_dp_mode.drm_mode.clock; ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); =20 msm_dp_ctrl_send_phy_test_pattern(ctrl); @@ -2240,7 +2258,8 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl return 0; } =20 -void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl; u32 sink_request =3D 0x0; @@ -2255,14 +2274,14 @@ void msm_dp_ctrl_handle_sink_request(struct msm_dp_= ctrl *msm_dp_ctrl) =20 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); - if (msm_dp_ctrl_process_phy_test_request(ctrl)) { + if (msm_dp_ctrl_process_phy_test_request(ctrl, panel)) { DRM_ERROR("process phy_test_req failed\n"); return; } } =20 if (sink_request & DP_LINK_STATUS_UPDATED) { - if (msm_dp_ctrl_link_maintenance(ctrl)) { + if (msm_dp_ctrl_link_maintenance(ctrl, panel)) { DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); return; } @@ -2270,7 +2289,7 @@ void msm_dp_ctrl_handle_sink_request(struct msm_dp_ct= rl *msm_dp_ctrl) =20 if (sink_request & DP_TEST_LINK_TRAINING) { msm_dp_link_send_test_response(ctrl->link); - if (msm_dp_ctrl_link_maintenance(ctrl)) { + if (msm_dp_ctrl_link_maintenance(ctrl, panel)) { DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); return; } @@ -2306,7 +2325,8 @@ static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_c= trl_private *ctrl) return drm_dp_channel_eq_ok(link_status, num_lanes); } =20 -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { int rc =3D 0; struct msm_dp_ctrl_private *ctrl; @@ -2322,8 +2342,8 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - rate =3D ctrl->panel->link_info.rate; - pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + rate =3D panel->link_info.rate; + pixel_rate =3D panel->msm_dp_mode.drm_mode.clock; =20 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); =20 @@ -2335,8 +2355,8 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) } else { ctrl->link->link_params.rate =3D rate; ctrl->link->link_params.num_lanes =3D - ctrl->panel->link_info.num_lanes; - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) + panel->link_info.num_lanes; + if (panel->msm_dp_mode.out_fmt_is_yuv_420) pixel_rate >>=3D 1; } =20 @@ -2344,13 +2364,13 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, pixel_rate); =20 - rc =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); + rc =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); if (rc) return rc; =20 while (--link_train_max_retries) { training_step =3D DP_TRAINING_NONE; - rc =3D msm_dp_ctrl_setup_main_link(ctrl, &training_step); + rc =3D msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); if (rc =3D=3D 0) { /* training completed successfully */ break; @@ -2369,7 +2389,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) * some lanes are ready, * reduce lane number */ - rc =3D msm_dp_ctrl_link_lane_down_shift(ctrl); + rc =3D msm_dp_ctrl_link_lane_down_shift(ctrl, panel); if (rc < 0) { /* lane =3D=3D 1 already */ /* end with failure */ break; @@ -2390,7 +2410,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) ctrl->link->link_params.num_lanes)) rc =3D msm_dp_ctrl_link_rate_down_shift(ctrl); else - rc =3D msm_dp_ctrl_link_lane_down_shift(ctrl); + rc =3D msm_dp_ctrl_link_lane_down_shift(ctrl, panel); =20 if (rc < 0) { /* end with failure */ @@ -2398,10 +2418,10 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_= ctrl) } =20 /* stop link training before start re training */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); } =20 - rc =3D msm_dp_ctrl_reinitialize_mainlink(ctrl); + rc =3D msm_dp_ctrl_reinitialize_mainlink(ctrl, panel); if (rc) { DRM_ERROR("Failed to reinitialize mainlink. rc=3D%d\n", rc); break; @@ -2422,20 +2442,21 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_= ctrl) * link training failed * end txing train pattern here */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); =20 - msm_dp_ctrl_deinitialize_mainlink(ctrl); + msm_dp_ctrl_deinitialize_mainlink(ctrl, panel); rc =3D -ECONNRESET; } =20 return rc; } =20 -static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl) +static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) { int training_step =3D DP_TRAINING_NONE; =20 - return msm_dp_ctrl_setup_main_link(ctrl, &training_step); + return msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); } =20 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, @@ -2506,7 +2527,9 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl= _private *ctrl, msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } =20 -int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel, + bool force_link_train) { int ret =3D 0; struct msm_dp_ctrl_private *ctrl; @@ -2525,7 +2548,7 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl = *msm_dp_ctrl, bool force_li ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); =20 if (!ctrl->link_clks_on) { /* link clk is off */ - ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); + ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); if (ret) { DRM_ERROR("Failed to start link clocks. ret=3D%d\n", ret); return ret; @@ -2533,15 +2556,15 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctr= l *msm_dp_ctrl, bool force_li } =20 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) - msm_dp_ctrl_link_retrain(ctrl); + msm_dp_ctrl_link_retrain(ctrl, panel); =20 /* stop txing train pattern to end link training */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); =20 return ret; } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *panel) { int ret =3D 0; bool mainlink_ready =3D false; @@ -2554,10 +2577,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate_orig =3D panel->msm_dp_mode.drm_mode.clock; pixel_rate =3D pixel_rate_orig; =20 - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + if (msm_dp_ctrl->wide_bus_en || panel->msm_dp_mode.out_fmt_is_yuv_420) pixel_rate >>=3D 1; =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); @@ -2574,18 +2597,18 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl) =20 msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); - msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl, panel); =20 - msm_dp_ctrl_configure_source_params(ctrl); + msm_dp_ctrl_configure_source_params(ctrl, panel); =20 msm_dp_ctrl_config_msa(ctrl, ctrl->link->link_params.rate, pixel_rate_orig, - ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); + panel->msm_dp_mode.out_fmt_is_yuv_420); =20 - msm_dp_panel_clear_dsc_dto(ctrl->panel); + msm_dp_panel_clear_dsc_dto(panel); =20 - msm_dp_ctrl_setup_tr_unit(ctrl); + msm_dp_ctrl_setup_tr_unit(ctrl, panel); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 @@ -2613,7 +2636,8 @@ void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_d= p_ctrl) phy_init(phy); } =20 -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2621,11 +2645,11 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctr= l) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(ctrl->panel); + msm_dp_panel_disable_vsc_sdp(panel); =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); =20 msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); @@ -2634,7 +2658,8 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) phy_power_off(phy); } =20 -irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl) +irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl; u32 isr; @@ -2645,7 +2670,7 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_d= p_ctrl) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - if (ctrl->panel->psr_cap.version) { + if (panel->psr_cap.version) { isr =3D msm_dp_ctrl_get_psr_interrupt(ctrl); =20 if (isr) @@ -2734,7 +2759,7 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *m= sm_dp_ctrl) } =20 struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link= *link, - struct msm_dp_panel *panel, struct drm_dp_aux *aux, + struct drm_dp_aux *aux, struct phy *phy, void __iomem *ahb_base, void __iomem *link_base) @@ -2742,7 +2767,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link struct msm_dp_ctrl_private *ctrl; int ret; =20 - if (!dev || !panel || !aux || !link) { + if (!dev || !aux || !link) { DRM_ERROR("invalid input\n"); return ERR_PTR(-EINVAL); } @@ -2770,7 +2795,6 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link init_completion(&ctrl->video_comp); =20 /* in parameters */ - ctrl->panel =3D panel; ctrl->aux =3D aux; ctrl->link =3D link; ctrl->dev =3D dev; diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 5d615f50d13b..00b430392a52 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -16,28 +16,36 @@ struct msm_dp_ctrl { =20 struct phy; =20 -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *panel); +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel, + bool force_link_train); +void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); -irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); -void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); +irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); +void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, - struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, void __iomem *ahb_base, void __iomem *link_base); =20 -void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_irq_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); =20 -void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enable); -void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel, bool enable); +void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); =20 int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index b8dab3f8a7c2..230e14615a23 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -359,7 +359,7 @@ static void msm_dp_display_host_init(struct msm_dp_disp= lay_private *dp) dp->phy_initialized); =20 msm_dp_ctrl_core_clk_enable(dp->ctrl); - msm_dp_ctrl_reset(dp->ctrl); + msm_dp_ctrl_reset(dp->ctrl, dp->panel); msm_dp_ctrl_enable_irq(dp->ctrl); msm_dp_aux_init(dp->aux); dp->core_initialized =3D true; @@ -371,7 +371,7 @@ static void msm_dp_display_host_deinit(struct msm_dp_di= splay_private *dp) dp->msm_dp_display.connector_type, dp->core_initialized, dp->phy_initialized); =20 - msm_dp_ctrl_reset(dp->ctrl); + msm_dp_ctrl_reset(dp->ctrl, dp->panel); msm_dp_ctrl_disable_irq(dp->ctrl); msm_dp_aux_deinit(dp->aux); msm_dp_ctrl_core_clk_disable(dp->ctrl); @@ -392,7 +392,7 @@ static int msm_dp_display_handle_irq_hpd(struct msm_dp_= display_private *dp) =20 drm_dbg_dp(dp->drm_dev, "%d\n", sink_request); =20 - msm_dp_ctrl_handle_sink_request(dp->ctrl); + msm_dp_ctrl_handle_sink_request(dp->ctrl, dp->panel); =20 if (sink_request & DP_TEST_LINK_VIDEO_PATTERN) msm_dp_display_handle_video_request(dp); @@ -570,7 +570,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, + dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->aux, phy, dp->ahb_base, dp->link_base); if (IS_ERR(dp->ctrl)) { rc =3D PTR_ERR(dp->ctrl); @@ -642,12 +642,12 @@ static int msm_dp_display_prepare_link(struct msm_dp_= display_private *dp) force_link_train =3D true; } =20 - rc =3D msm_dp_ctrl_on_link(dp->ctrl); + rc =3D msm_dp_ctrl_on_link(dp->ctrl, dp->panel); if (rc) DRM_ERROR("Failed link training (rc=3D%d)\n", rc); // TODO: schedule drm_connector_set_link_status_property() =20 - return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); + return msm_dp_ctrl_prepare_stream_on(dp->ctrl, dp->panel, force_link_trai= n); } =20 static int msm_dp_display_enable(struct msm_dp_display_private *dp) @@ -661,7 +661,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp) return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -686,7 +686,7 @@ static int msm_dp_display_post_enable(struct msm_dp *ms= m_dp_display) msm_dp_display_handle_plugged_change(msm_dp_display, true); =20 if (msm_dp_display->psr_supported) - msm_dp_ctrl_config_psr(dp->ctrl); + msm_dp_ctrl_config_psr(dp->ctrl, dp->panel); =20 return 0; } @@ -725,7 +725,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off(dp->ctrl); + msm_dp_ctrl_off(dp->ctrl, dp->panel); /* re-init the PHY so that we can listen to Dongle disconnect */ msm_dp_ctrl_reinit_phy(dp->ctrl); } else { @@ -733,7 +733,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) * unplugged interrupt * dongle unplugged out of DUT */ - msm_dp_ctrl_off(dp->ctrl); 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 +++++----- drivers/gpu/drm/msm/dp/dp_ctrl.h | 5 +++-- drivers/gpu/drm/msm/dp/dp_display.c | 7 ++++--- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 88b6f4b8a598..6e78dd62fc1a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2213,7 +2213,7 @@ static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctr= l_private *ctrl, unsigned l return ret; } =20 -static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; =20 @@ -2242,7 +2242,8 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off(&ctrl->msm_dp_ctrl, panel); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl, panel); =20 ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, panel); if (ret) { @@ -2636,8 +2637,8 @@ void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_d= p_ctrl) phy_init(phy); } =20 -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, - struct msm_dp_panel *panel) +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2651,7 +2652,6 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); =20 - msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 00b430392a52..5902cf7e746a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -22,8 +22,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl= , struct msm_dp_panel * int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel, bool force_link_train); -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, - struct msm_dp_panel *panel); +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 230e14615a23..8f472633da82 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -725,15 +725,16 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off(dp->ctrl, dp->panel); - /* re-init the PHY so that we can listen to Dongle disconnect */ + msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_link(dp->ctrl, dp->panel); msm_dp_ctrl_reinit_phy(dp->ctrl); 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No functional change intended. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 8f472633da82..63e5b191f95c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -716,27 +716,19 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 msm_dp_panel_disable_vsc_sdp(dp->panel); =20 - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count =3D=3D 0) { - /* - * irq_hpd with sink_count =3D 0 - * hdmi unplugged out of dongle - */ + msm_dp_ctrl_off_pixel_clk(dp->ctrl); =20 - /* set dongle to D3 (power off) mode */ + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count =3D=3D 0) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off_pixel_clk(dp->ctrl); - msm_dp_ctrl_off_link(dp->ctrl, dp->panel); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-914f86fffddsm755148485a.12.2026.05.28.03.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:41:38 -0700 (PDT) From: Yongxing Mou Date: Thu, 28 May 2026 18:40:34 +0800 Subject: [PATCH v5 13/15] drm/msm/dp: make bridge helpers use dp_display to allow re-use Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-dp_mstclean-v5-13-a9221c1f1f3b@oss.qualcomm.com> References: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> In-Reply-To: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779964831; l=8509; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=js7Ds0kDP3MA2PA3qJwTal/QoxqVBRyKdoKt/vuLT7c=; b=qPbwZc4gkkLq2J/drxcqZeHRgvRIK7bXezYuhoXiVSce0PUFJVrh+/KiZ4BZfdHP6vL/6so12 OWCx52CHBhTCercqMZWXZjeg7E912Xd0582a/kYZIU/yBgig2ecIPrk X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: TYyMCeM2QdclMFzwXP1Ts8swtZ0LsNOs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwOCBTYWx0ZWRfX0Bb8sUvj6nf2 lr9V4dngmswUy16WWusMRQwgjjlnfArwNt8ba8+nBbICpPUc/kDsaI/s6r2Ng6AlpGsmvX+CyIf cqh/5N+4+ctDrzaJ6qwALGyf3+BtnpI21IRZTRYCbzx5dq693IP8VyR9vCo1lomEYyyajE+rZiD MWI4bq4AiIRIUiDP6Ov5HHTOGPMvd3spEudPYZ8Bq/LEZkDuW8cG4bCZt8hl7FM3jY5RC8JHzsl o2d928/NTfJEdGy1+UXgXDiRI4uFtF/68AH50Hhz4+yI9AWcLFY1SFl9Pc1ekLit/kFGKOpQmGQ SPPrL2Jex184qrJLzvUs7owByWopIBrt2OLWD3+cs4OURQQYKV5yCaAEWLWhRk43tmM8lKzM7Um 7aTjGDEraJxE9B9pNVuKKJ92otw2FPFTHglT/DOUv921vkmBX+m8o0BqRj2/CQQnkpMpMPXbZ8N 2p87XB3o5A0cWT6teUA== X-Proofpoint-ORIG-GUID: TYyMCeM2QdclMFzwXP1Ts8swtZ0LsNOs X-Authority-Analysis: v=2.4 cv=G8gs1dk5 c=1 sm=1 tr=0 ts=6a181be4 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=LmD7BKvqrCyCckpIDn8A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 clxscore=1015 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280108 From: Abhinav Kumar dp_bridge helpers take drm_bridge as an input and extract the dp_display object to be used in the dp_display module. Rather than doing it in a roundabout way, directly pass the dp_display object to these helpers so that the MST bridge can also re-use the same helpers. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 29 +++++++++------------------ drivers/gpu/drm/msm/dp/dp_display.h | 7 +++++++ drivers/gpu/drm/msm/dp/dp_drm.c | 39 +++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_drm.h | 9 --------- 4 files changed, 54 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 63e5b191f95c..2d5ef087648c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -738,24 +738,21 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 /** * msm_dp_bridge_mode_valid - callback to determine if specified mode is v= alid - * @bridge: Pointer to drm bridge structure + * @dp: Pointer to dp display structure * @info: display info * @mode: Pointer to drm mode structure * Returns: Validity status for specified mode */ -enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode) { const u32 num_components =3D 3, default_bpp =3D 24; struct msm_dp_display_private *msm_dp_display; struct msm_dp_link_info *link_info; u32 mode_rate_khz =3D 0, supported_rate_khz =3D 0, mode_bpp =3D 0; - struct msm_dp *dp; int mode_pclk_khz =3D mode->clock; =20 - dp =3D to_dp_bridge(bridge)->msm_dp_display; - if (!dp || !mode_pclk_khz || !dp->connector) { DRM_ERROR("invalid params\n"); return -EINVAL; @@ -1406,11 +1403,9 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_displa= y, struct drm_device *dev, return 0; } =20 -void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, + struct drm_atomic_commit *state) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int rc =3D 0; @@ -1419,7 +1414,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *d= rm_bridge, dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 crtc =3D drm_atomic_get_new_crtc_for_encoder(state, - drm_bridge->encoder); + msm_dp_display->bridge->encoder); if (!crtc) return; crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); @@ -1449,11 +1444,8 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *= drm_bridge, drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 -void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); @@ -1470,11 +1462,8 @@ static void msm_dp_display_unprepare(struct msm_dp_d= isplay_private *dp) drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); } =20 -void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_post_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 0b65e16c790d..5116f7bbbd02 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -33,5 +33,12 @@ void msm_dp_display_signal_audio_start(struct msm_dp *ms= m_dp_display); void msm_dp_display_signal_audio_complete(struct msm_dp *msm_dp_display); void msm_dp_display_set_psr(struct msm_dp *dp, bool enter); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct den= try *dentry, bool is_edp); +void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display, + struct drm_atomic_commit *state); +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode); =20 #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index 6ac5bac903d9..6b8923d9dff4 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -49,6 +49,43 @@ static void msm_dp_bridge_debugfs_init(struct drm_bridge= *bridge, struct dentry msm_dp_display_debugfs_init(dp, root, false); } =20 +static void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, + struct drm_atomic_commit *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_enable(dp, state); +} + +static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_commit *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_disable(dp); +} + +static void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridg= e, + struct drm_atomic_commit *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_post_disable(dp); +} + +static enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *dr= m_bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + return msm_dp_display_mode_valid(dp, info, mode); +} + static const struct drm_bridge_funcs msm_dp_bridge_ops =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, @@ -115,7 +152,7 @@ static void msm_edp_bridge_atomic_enable(struct drm_bri= dge *drm_bridge, return; } =20 - msm_dp_bridge_atomic_enable(drm_bridge, state); + msm_dp_display_atomic_enable(dp, state); } =20 static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_dr= m.h index 4bd788ea05d5..da412c788503 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -27,15 +27,6 @@ int msm_dp_bridge_init(struct msm_dp *msm_dp_display, st= ruct drm_device *dev, =20 enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-914f86fffddsm755148485a.12.2026.05.28.03.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:41:43 -0700 (PDT) From: Yongxing Mou Date: Thu, 28 May 2026 18:40:35 +0800 Subject: [PATCH v5 14/15] drm/msm/dp: separate dp_display_prepare() into its own API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-dp_mstclean-v5-14-a9221c1f1f3b@oss.qualcomm.com> References: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> In-Reply-To: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779964831; l=3743; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=PejPis5lPUmTa0t10X2rGcGnHfGkWszn1oUEuwhLLv0=; b=XAghNErOj5Q8+qQKxC2vyn/619TeztHoHxIqNc9crazWw1iU4EdyZh0ib+n4zg356QVgcl4GW KX+FfcvqeHTCfqvEMi1mP5ezwrB/wPUykqMuc8XD7kHLA6Wl5Q2FScK X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: tVWCvtGu-YpK93yC5nyL74RXte9Jh7dz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwOCBTYWx0ZWRfXyysTi7BlrIfn 2l+YPaGp1jeaJozNKdsR8CNUaneZZiW4cCmy4vXxc/nC1IAHBgYQQvTybPViC5r7X85xBuBQO4v If589ZizT0lpFfseYL61GTXoL6/jUYfz8fDiW3ccSckWZErSbPs2hPjJyNOr+GKttG0mf5H4A7C w4Z2qScLfjqctuj/TfbY9TyHqdCqHVEI3WfYE0RwRKk+q0eQFM+Yl+QaybCGihxaJ3CEuon/Cg3 kkCN1ZOJfo1AqhNhqTv69aWIMefXgdm3o7TP+aW9U+mT+h/1c8cKmTuLL8ehEwb7Ih+cNDIIbit 9vwhgaLD6ocXtczNQ08rhS/cnvEZuINAjQMdwDBHjcv8qb0d6iMwozq5kOTthmvQwJWPDC2LSiQ 5E8cb/M/Ix0BuaQHwkK5TgUkQi+yTBIpRVsIUgoKUwdIw5EnuSl9xy2Z2GNnhennWo30akgGngW ELRi5pIG9sVB+GiRSSA== X-Proofpoint-ORIG-GUID: tVWCvtGu-YpK93yC5nyL74RXte9Jh7dz X-Authority-Analysis: v=2.4 cv=Eo7iaycA c=1 sm=1 tr=0 ts=6a181be9 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=rHTcTV9uYuKpyGuOXCsA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280108 From: Abhinav Kumar For MST, the link setup should only be done once when multiple sinks are enabled, while stream setup may run multiple times for each sink. Split the link-related preparation out of msm_dp_display_atomic_enable() so it can be called separately before the per-stream enable path. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 16 +++++++++++----- drivers/gpu/drm/msm/dp/dp_display.h | 5 +++-- drivers/gpu/drm/msm/dp/dp_drm.c | 6 ++++-- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 2d5ef087648c..cd1f2899b733 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1403,8 +1403,8 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display= , struct drm_device *dev, return 0; } =20 -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display, + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -1426,10 +1426,16 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display, } =20 rc =3D msm_dp_display_prepare_link(dp); - if (rc) { + if (rc) DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); - return; - } +} + +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + int rc =3D 0; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 rc =3D msm_dp_display_enable(dp); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 5116f7bbbd02..43ed79093e24 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -35,8 +35,9 @@ void msm_dp_display_set_psr(struct msm_dp *dp, bool enter= ); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct den= try *dentry, bool is_edp); void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); void msm_dp_display_atomic_disable(struct msm_dp *dp_display); -void msm_dp_display_atomic_enable(struct msm_dp *dp_display, - struct drm_atomic_commit *state); +void msm_dp_display_atomic_prepare(struct msm_dp *dp_display, + struct drm_atomic_commit *state); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display); enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index 6b8923d9dff4..4bf1a5b7c3f9 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -55,7 +55,8 @@ static void msm_dp_bridge_atomic_enable(struct drm_bridge= *drm_bridge, struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); struct msm_dp *dp =3D dp_bridge->msm_dp_display; =20 - msm_dp_display_atomic_enable(dp, state); + msm_dp_display_atomic_prepare(dp, state); + msm_dp_display_atomic_enable(dp); } =20 static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -152,7 +153,8 @@ static void msm_edp_bridge_atomic_enable(struct drm_bri= dge *drm_bridge, return; } =20 - msm_dp_display_atomic_enable(dp, state); + msm_dp_display_atomic_prepare(dp, state); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-914f86fffddsm755148485a.12.2026.05.28.03.41.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 03:41:48 -0700 (PDT) From: Yongxing Mou Date: Thu, 28 May 2026 18:40:36 +0800 Subject: [PATCH v5 15/15] drm/msm/dp: pass panel to display enable/disable helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-dp_mstclean-v5-15-a9221c1f1f3b@oss.qualcomm.com> References: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> In-Reply-To: <20260528-dp_mstclean-v5-0-a9221c1f1f3b@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779964831; l=3051; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=9RrNuNwTk/ww6iYx0SuggmHq9TFnipSUNnQOBEesNk0=; b=NUSYehlP04crvps+VPP259ZW5+AW1qkFK0Wi1t/AyhuKVspU510X+GVtKQ1PDP4N7qLZ9NfWQ uzd4MMW4C9gDsqvx+ZO39rdNfAIQjku5I/1EtfrdTdFiOT/K5fvu3H5 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDEwOCBTYWx0ZWRfXzdloEEbWX9K0 iPTwf8vUPrS/VnR/vCWMGUax/gS50KhRAU6NplVRHBgsCqsU+eTvbHnKwYeVuV5baJCI/XBXONM VJEyHVOFVr885GL/VpI9p8pGAGWoNAvRNn2rXovHoktyfbcBoVqgFtEpvT16XersVOBPuUhE2nr ux77dDzjTkgz0S7Zxg2oFMz/VLXbKTfnvslA+3MvxGachBY0ppQUy38NmYFsde87hqwY3TyfdWa ZxyLzw8XfoE7H2Ao3WSa0DG6zZbL/SsWex+LTWSbnzOhpb2pcv4Nb/k1prj4J9YVWUXG32P6TII gt83Mhx9dbFu+8fsWb4FqIlas2iU5lpfPdeoSzvI/Mrp17BIgRPxzcjXAvQ8I5uDl9uwq+YeHa9 3d/PbtQFtFx7ZZRDI/lfdIzXODU4bcr2AKxPBKINe9nm0hGx1v3W9Np0pAqzHjck2aLYF+f89F4 rmkNOxrjzw+LqzdETqg== X-Authority-Analysis: v=2.4 cv=PLo/P/qC c=1 sm=1 tr=0 ts=6a181bed cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=Kfrt2GjMPgVQdVN7MJkA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: gjiTknW9yzkiS01AtDXXMujHcXoVpKc8 X-Proofpoint-ORIG-GUID: gjiTknW9yzkiS01AtDXXMujHcXoVpKc8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_03,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280108 Pass struct msm_dp_panel to the display enable/disable helpers to make them easier to reuse for MST stream handling. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index cd1f2899b733..bea5bfb22967 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -650,7 +650,8 @@ static int msm_dp_display_prepare_link(struct msm_dp_di= splay_private *dp) return msm_dp_ctrl_prepare_stream_on(dp->ctrl, dp->panel, force_link_trai= n); } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp) +static int msm_dp_display_enable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -661,7 +662,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp) return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -707,20 +708,21 @@ static void msm_dp_display_audio_notify_disable(struc= t msm_dp_display_private *d msm_dp_display->audio_enabled =3D false; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static int msm_dp_display_disable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 if (!msm_dp_display->power_on) return 0; =20 - msm_dp_panel_disable_vsc_sdp(dp->panel); + msm_dp_panel_disable_vsc_sdp(msm_dp_panel); =20 msm_dp_ctrl_off_pixel_clk(dp->ctrl); =20 /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) - msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + msm_dp_link_psm_config(dp->link, &msm_dp_panel->link_info, true); =20 msm_dp_ctrl_off_link(dp->ctrl, dp->panel); =20 @@ -1437,14 +1439,14 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - rc =3D msm_dp_display_enable(dp); + rc =3D msm_dp_display_enable(dp, dp->panel); if (rc) DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(dp); + msm_dp_display_disable(dp, dp->panel); } =20 drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); @@ -1479,7 +1481,7 @@ void msm_dp_display_atomic_post_disable(struct msm_dp= *dp) =20 msm_dp_display_audio_notify_disable(msm_dp_display); =20 - msm_dp_display_disable(msm_dp_display); + msm_dp_display_disable(msm_dp_display, msm_dp_display->panel); =20 msm_dp_display_unprepare(msm_dp_display); } --=20 2.43.0