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The core CM6 module is based on the SpacemiT K1 SoC and provides PMIC, DDR, the eth0 PHY and wireless connectivity. The carrier board extends this by adding the eth1 PHY and external interfaces including Ethernet, PCIe M.2, USB, MicroSD, QSPI, and serial console connectivity. Acked-by: Conor Dooley Signed-off-by: Junhui Liu --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Docume= ntation/devicetree/bindings/riscv/spacemit.yaml index af8030242bdc..3e868383eb4a 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -19,6 +19,11 @@ properties: const: '/' compatible: oneOf: + - items: + - enum: + - bananapi,bpi-cm6-io + - const: bananapi,bpi-cm6 + - const: spacemit,k1 - items: - enum: - bananapi,bpi-f3 --=20 2.54.0 From nobody Mon Jun 8 16:49:25 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6213A318EE6; Thu, 28 May 2026 05:24:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-bpi-cm6-v2-2-d0eb3f236cea@pigmoral.tech> References: <20260528-bpi-cm6-v2-0-d0eb3f236cea@pigmoral.tech> In-Reply-To: <20260528-bpi-cm6-v2-0-d0eb3f236cea@pigmoral.tech> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Vivian Wang , Paolo Abeni , Guodong Xu , Yangyu Chen Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779945818; l=5834; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=rPbiI+ilu0sWLrlMfU9HzlanUD+8Jf5nKjJmEKXu0F8=; b=1mQYY2xTcO+DDWebUtj2X3kbiSMbJ9X2a3RloGTPAZTG8qLyeWVCIIl4zm26gSqEDvn2U9jdC sDGtBEWadDJBCXwhIwCesmOJbu6hbg8foG9n2AUzbrn9g4Em9kb/Vgg X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The gmac_clk_ref signal is optional for the GMAC controller and is not strictly required for all hardware designs. The pins for gmac0_clk_ref (GPIO 45) and gmac1_clk_ref (GPIO 46) may also be used as GPIOs for other functions even when the Ethernet controller is active. Split the refclk pins into independent pinctrl groups so boards can request them only when the reference clock path is actually needed. Among the already mainlined boards, BPI-F3, Jupiter and MusePi Pro have optional hardware paths for the GMAC refclk pins. BPI-F3 and Jupiter route both GMAC refclk pins to the PHYs through NC/0R option resistors, while MusePi Pro only does so for GMAC0. Keep referencing the new clk-ref pinctrl groups on these boards so the optional hardware paths remain usable if the option resistors are populated. OrangePi R2S has no publicly available schematic, so also keep the clk-ref groups there to preserve the previous pinmux behavior. Fixes: 60775f28cfb7 ("riscv: dts: spacemit: Add Ethernet support for K1") Signed-off-by: Junhui Liu --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++-- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++-- arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 4 ++-- arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 24 +++++++++++++++++++= ---- 5 files changed, 27 insertions(+), 11 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index 72f77e9edd63..e6ab43be301a 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -101,7 +101,7 @@ ð0 { phy-handle =3D <&rgmii0>; phy-mode =3D "rgmii-id"; pinctrl-names =3D "default"; - pinctrl-0 =3D <&gmac0_cfg>; + pinctrl-0 =3D <&gmac0_cfg>, <&gmac0_clk_ref_cfg>; rx-internal-delay-ps =3D <0>; tx-internal-delay-ps =3D <0>; status =3D "okay"; @@ -124,7 +124,7 @@ ð1 { phy-handle =3D <&rgmii1>; phy-mode =3D "rgmii-id"; pinctrl-names =3D "default"; - pinctrl-0 =3D <&gmac1_cfg>; + pinctrl-0 =3D <&gmac1_cfg>, <&gmac1_clk_ref_cfg>; rx-internal-delay-ps =3D <0>; tx-internal-delay-ps =3D <250>; status =3D "okay"; diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv= /boot/dts/spacemit/k1-milkv-jupiter.dts index 2fc8d6533786..b61f5995ec77 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -121,7 +121,7 @@ ð0 { phy-handle =3D <&rgmii0>; phy-mode =3D "rgmii-id"; pinctrl-names =3D "default"; - pinctrl-0 =3D <&gmac0_cfg>; + pinctrl-0 =3D <&gmac0_cfg>, <&gmac0_clk_ref_cfg>; rx-internal-delay-ps =3D <0>; tx-internal-delay-ps =3D <0>; status =3D "okay"; @@ -144,7 +144,7 @@ ð1 { phy-handle =3D <&rgmii1>; phy-mode =3D "rgmii-id"; pinctrl-names =3D "default"; - pinctrl-0 =3D <&gmac1_cfg>; + pinctrl-0 =3D <&gmac1_cfg>, <&gmac1_clk_ref_cfg>; rx-internal-delay-ps =3D <0>; tx-internal-delay-ps =3D <250>; status =3D "okay"; diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/bo= ot/dts/spacemit/k1-musepi-pro.dts index 0d809e4ad3b1..3078ffb5cb87 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -102,7 +102,7 @@ &combo_phy { ð0 { phy-handle =3D <&rgmii0>; phy-mode =3D "rgmii-id"; - pinctrl-0 =3D <&gmac0_cfg>; + pinctrl-0 =3D <&gmac0_cfg>, <&gmac0_clk_ref_cfg>; pinctrl-names =3D "default"; rx-internal-delay-ps =3D <0>; tx-internal-delay-ps =3D <0>; diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/= boot/dts/spacemit/k1-orangepi-r2s.dts index 1ecc40749e5a..018072722d55 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -50,7 +50,7 @@ ð0 { phy-handle =3D <&rgmii0>; phy-mode =3D "rgmii-id"; pinctrl-names =3D "default"; - pinctrl-0 =3D <&gmac0_cfg>; + pinctrl-0 =3D <&gmac0_cfg>, <&gmac0_clk_ref_cfg>; rx-internal-delay-ps =3D <0>; tx-internal-delay-ps =3D <0>; status =3D "okay"; @@ -74,7 +74,7 @@ ð1 { phy-handle =3D <&rgmii1>; phy-mode =3D "rgmii-id"; pinctrl-names =3D "default"; - pinctrl-0 =3D <&gmac1_cfg>; + pinctrl-0 =3D <&gmac1_cfg>, <&gmac1_clk_ref_cfg>; rx-internal-delay-ps =3D <0>; tx-internal-delay-ps =3D <250>; status =3D "okay"; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot= /dts/spacemit/k1-pinctrl.dtsi index 4e9a62d0e85b..8c57ca05dabd 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -27,8 +27,16 @@ gmac0-pins { , /* gmac0_tx_en */ , /* gmac0_mdc */ , /* gmac0_mdio */ - , /* gmac0_int_n */ - ; /* gmac0_clk_ref */ + ; /* gmac0_int_n */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + + gmac0_clk_ref_cfg: gmac0-clk-ref-cfg { + gmac0-clk-ref-pins { + pinmux =3D ; /* gmac0_clk_ref */ =20 bias-pull-up =3D <0>; drive-strength =3D <21>; @@ -51,8 +59,16 @@ gmac1-pins { , /* gmac1_tx_en */ , /* gmac1_mdc */ , /* gmac1_mdio */ - , /* gmac1_int_n */ - ; /* gmac1_clk_ref */ + ; /* gmac1_int_n */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + + gmac1_clk_ref_cfg: gmac1-clk-ref-cfg { + gmac1-clk-ref-pins { + pinmux =3D ; /* gmac1_clk_ref */ =20 bias-pull-up =3D <0>; drive-strength =3D <21>; --=20 2.54.0 From nobody Mon Jun 8 16:49:25 2026 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E66893191BD; Thu, 28 May 2026 05:25:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779945911; cv=pass; b=hY2UVZj7RJ8uTIXqCMtDXA1zkj4K7OG6LzQhdET+Y1ipy9YBGVZduGEJWrwTDR0yjj5clDZmw58GOjqXNjhn9d21QOc0acMgMrGAvRHCcxcIM5XfSkTdHPau/XdmRHOt8siJMcDhK2zraGji9RtVN4PJZzpwFjhCr2PLAuzd6oE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=wuClTkOk0dKaiP34piQzr0V1cQ3l4u1JoABlU0vrpNk=; b=N9e40GGz3DWhPzV4JZ97o8yDn1ZWgUiOJEPxBloA07rbQ4mAHPLSUGL+NWCb5aGM U8UyhD01Nv2QT7MNFxRPqCGW8k+nRDJYK5I0yLjDFRXCFeGEUJjPhjMS3YZlvTOsGqT McDzKIFTxzvYX2mGit8aYsDwlesCDAjZYq4Tx1lY= Received: by mx.zohomail.com with SMTPS id 1779945875685152.24407731614338; Wed, 27 May 2026 22:24:35 -0700 (PDT) From: Junhui Liu Date: Thu, 28 May 2026 13:22:49 +0800 Subject: [PATCH v2 3/3] riscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-bpi-cm6-v2-3-d0eb3f236cea@pigmoral.tech> References: <20260528-bpi-cm6-v2-0-d0eb3f236cea@pigmoral.tech> In-Reply-To: <20260528-bpi-cm6-v2-0-d0eb3f236cea@pigmoral.tech> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Vivian Wang , Paolo Abeni , Guodong Xu , Yangyu Chen Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu , Michael Opdenacker X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779945818; l=11684; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=5WrgPccF1WmmeqzSVaPFWAtNkJ8zQ5N2YbTJ4s7W0OA=; b=FoLtqkDOMnT2V72xkdKubvILwxaLJfEY1GZYMqpc01/+Y92L/fvBorT3HjzwT1uTsWfFdomx5 mFh6nT4B4CwBQvUGm3G4pmZwHARigt7ymO4+wXbyDdkTr8nIwf7IIeu X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The Banana Pi BPI-CM6 IO board combines the BPI-CM6 compute module with an IO carrier board. The core module integrates the SpacemiT K1 SoC, PMIC, DDR, eMMC, the eth0 PHY, and wireless connectivity. The companion IO carrier board extends it by providing the eth1 PHY and exposing standard interfaces, including dual Gigabit Ethernet, MicroSD, two USB-A ports, a USB Type-C port, two PCIe M.2 slots, and a serial console. The board also has two I2C EEPROMs. One is on the core module, which stores factory manufacturing data and is marked read-only. The other is on the carrier board, which is shipped unprogrammed and left writable for evaluation purposes. Add initial support for UART console, eMMC, SD card, I2C, EEPROMs, PCIe, USB, and dual Ethernet interfaces. Link: https://docs.banana-pi.org/en/BPI-CM6/BananaPi_BPI-CM6 Reviewed-by: Michael Opdenacker Tested-by: Michael Opdenacker Signed-off-by: Junhui Liu --- arch/riscv/boot/dts/spacemit/Makefile | 1 + .../riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts | 213 +++++++++++++++++= ++ arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi | 227 +++++++++++++++++= ++++ 3 files changed, 441 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/sp= acemit/Makefile index acb993c452ba..dd6125dc2012 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-bananapi-cm6-io.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-bananapi-f3.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-musepi-pro.dtb diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts b/arch/ris= cv/boot/dts/spacemit/k1-bananapi-cm6-io.dts new file mode 100644 index 000000000000..137b7ef3fc7b --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2026 Junhui Liu + */ + +#include "k1-bananapi-cm6.dtsi" + +#include + +/ { + model =3D "Banana Pi BPI-CM6 IO Board"; + compatible =3D "bananapi,bpi-cm6-io", "bananapi,bpi-cm6", "spacemit,k1"; + + aliases { + ethernet0 =3D ð0; + ethernet1 =3D ð1; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led0 { + color =3D ; + gpios =3D <&gpio K1_GPIO(96) GPIO_ACTIVE_LOW>; + }; + + led1 { + color =3D ; + gpios =3D <&gpio K1_GPIO(97) GPIO_ACTIVE_LOW>; + }; + }; + + vdd_sys_12v: regulator-vdd-sys-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_SYS"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_5v0: regulator-vdd-5v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_5V0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <&vdd_sys_12v>; + }; + + pcie_vcc_3v3: regulator-pcie-vcc-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "NGFF_KEYM_VDD"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <&vdd_sys_12v>; + }; + + usb_vbus_5v: regulator-usb-vbus-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VBUS_A_B"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio K1_GPIO(124) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <®_vdd_5v0>; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <&vdd_sys_12v>; + }; + + sd_vcc_3v3: regulator-sd-vcc-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3.3VS_CARD"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <®_vdd_3v3>; + }; +}; + +&combo_phy { + status =3D "okay"; +}; + +ð0 { + status =3D "okay"; +}; + +ð1 { + nvmem-cells =3D <&mac_address 1>; + nvmem-cell-names =3D "mac-address"; + phy-handle =3D <&rgmii1>; + phy-mode =3D "rgmii-id"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1_cfg>; + rx-internal-delay-ps =3D <0>; + tx-internal-delay-ps =3D <250>; + status =3D "okay"; + + mdio-bus { + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + + reset-gpios =3D <&gpio K1_GPIO(46) GPIO_ACTIVE_LOW>; + reset-delay-us =3D <10000>; + reset-post-delay-us =3D <100000>; + + rgmii1: phy@1 { + reg =3D <0x1>; + }; + }; +}; + +&i2c2 { + eeprom@54 { + compatible =3D "atmel,24c08"; + reg =3D <0x54>; + vcc-supply =3D <&buck3_1v8>; + pagesize =3D <16>; + size =3D <1024>; + }; +}; + +&pcie1_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_3_cfg>; + status =3D "okay"; +}; + +&pcie1_port { + phys =3D <&pcie1_phy>; + vpcie3v3-supply =3D <&pcie_vcc_3v3>; +}; + +&pcie1 { + status =3D "okay"; +}; + +&pcie2_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_4_cfg>; + status =3D "okay"; +}; + +&pcie2_port { + phys =3D <&pcie2_phy>; + vpcie3v3-supply =3D <&pcie_vcc_3v3>; +}; + +&pcie2 { + status =3D "okay"; +}; + +&qspi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qspi_cfg>; + status =3D "okay"; +}; + +&sdhci0 { + pinctrl-names =3D "default", "uhs"; + pinctrl-0 =3D <&mmc1_cfg>; + pinctrl-1 =3D <&mmc1_uhs_cfg>; + bus-width =3D <4>; + cd-gpios =3D <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply =3D <&sd_vcc_3v3>; + vqmmc-supply =3D <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_2_cfg>; + status =3D "okay"; +}; + +&usbphy2 { + status =3D "okay"; +}; + +&usb_dwc3 { + dr_mode =3D "host"; + vbus-supply =3D <&usb_vbus_5v>; + status =3D "okay"; +}; + +&vddin_sys_5v { + vin-supply =3D <®_vdd_5v0>; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi b/arch/riscv= /boot/dts/spacemit/k1-bananapi-cm6.dtsi new file mode 100644 index 000000000000..9b91128edb34 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2026 Junhui Liu + */ + +#include "k1.dtsi" +#include "k1-pinctrl.dtsi" + +/ { + model =3D "Banana Pi BPI-CM6 Module"; + compatible =3D "bananapi,bpi-cm6", "spacemit,k1"; + + aliases { + i2c2 =3D &i2c2; + i2c8 =3D &i2c8; + }; + + vddin_sys_5v: regulator-vddin-sys-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDDIN_SYS"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vcc_4v: regulator-vcc-4v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCC4V0_SYS"; + regulator-min-microvolt =3D <4000000>; + regulator-max-microvolt =3D <4000000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <&vddin_sys_5v>; + }; +}; + +&emmc { + bus-width =3D <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status =3D "okay"; +}; + +ð0 { + nvmem-cells =3D <&mac_address 0>; + nvmem-cell-names =3D "mac-address"; + phy-handle =3D <&rgmii0>; + phy-mode =3D "rgmii-id"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_cfg>; + rx-internal-delay-ps =3D <0>; + tx-internal-delay-ps =3D <0>; + + mdio-bus { + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + + reset-gpios =3D <&gpio K1_GPIO(45) GPIO_ACTIVE_LOW>; + reset-delay-us =3D <10000>; + reset-post-delay-us =3D <100000>; + + rgmii0: phy@1 { + reg =3D <0x1>; + }; + }; +}; + +&pdma { + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_0_cfg>; + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + vcc-supply =3D <&buck3_1v8>; + pagesize =3D <16>; + read-only; + size =3D <256>; + + nvmem-layout { + compatible =3D "onie,tlv-layout"; + + mac_address: mac-address { + #nvmem-cell-cells =3D <1>; + }; + + num-macs { + }; + + serial-number { + }; + }; + }; +}; + +&i2c8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c8_cfg>; + status =3D "okay"; + + pmic@41 { + compatible =3D "spacemit,p1"; + reg =3D <0x41>; + interrupts =3D <64>; + vin1-supply =3D <®_vcc_4v>; + vin2-supply =3D <®_vcc_4v>; + vin3-supply =3D <®_vcc_4v>; + vin4-supply =3D <®_vcc_4v>; + vin5-supply =3D <®_vcc_4v>; + vin6-supply =3D <®_vcc_4v>; + aldoin-supply =3D <®_vcc_4v>; + dldoin1-supply =3D <&buck5>; + dldoin2-supply =3D <&buck5>; + + regulators { + buck1 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3450000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3450000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck4 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3450000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3450000>; + regulator-ramp-delay =3D <5000>; + regulator-always-on; + }; + + aldo1: aldo1 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + }; + + aldo3 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + }; + + aldo4 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + }; + + dldo1 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + }; + + dldo3 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + }; + + dldo4 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + }; + + dldo6 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3400000>; + }; + }; + }; +}; --=20 2.54.0