From nobody Mon Jun 8 15:38:17 2026 Received: from mail-07.mail-europe.com (mail-07.mail-europe.com [188.165.51.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09DD43B2FC9; Thu, 28 May 2026 09:48:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=188.165.51.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961737; cv=none; b=C7whw200grXX7tAuL3YBKjMNJ/WnhqFjVqHlBJtetoMIzjjrCg/H1/1Izzwq6MxoBi9yPfgOxSTwIx+KAqlS4Xg3sg/wi7Wm1CIjCxsqh1DXgoLPetRWjmPUhiVxI+cgLZSHQI5qp5TqI48XdKPZzbR/x+JAD+jH2Upu2gry1pM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961737; c=relaxed/simple; bh=/fsT2N/xim+1oKj0wH9AEoxpM7fB+zWQEt4p4+KUxew=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q7s5fnEEjl8lK5Aesb4cXB1cLiXnNpIhHdmVcTLbRyK7A+/T+7YC1pXOQJfVGc6g/EzOyPE5AETW65pLnEzc0eQN8GQnClzMmuE1CZCLiNB9GF5W8fZttq7ewoUQLrZsMHLros3V0otG0yGkOegjUj1KCKIz7F279Bt4jMuZvJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=lYg7Y4RW; arc=none smtp.client-ip=188.165.51.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="lYg7Y4RW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1779961718; x=1780220918; bh=l0aCynGdTED5J28htu9O4TbhTVf6MOK84YreJh5isrs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=lYg7Y4RWQnecf1Hb1mjWTfOrLJJrxqX7GYeIiwwq4VdQScyDuN/mA+g/cmPFsAz3M tejIUALdL2rnLrD9DGKTgkKZKxPeEvn8WwgZYIOdHiMgUlGTRLhUStASDijYkfcdTf FfImasO8gq8ssLQ5cXp4ecsvkmZ8GS63Thh05RwOgkYLxRIg8Ni869DyxL8Euhrn2k NapTEXM/0SzybfI5D5RKce2Q41vbNGhBB7q4Vzx4DoPJ4qlfQ2wqBR55eASaMPVF8F 8o4Rug75W9P5dQ8Se8dIMSjdlolJhwRcK4vlzDx8bNgZVbmZa39DFgD/1sJWBcwppw +aGFyL9Q4me9Q== Date: Thu, 28 May 2026 09:48:30 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Krzysztof Kozlowski Subject: [PATCH v7 1/6] dt-bindings: display/msm/gmu: Document Adreno 810 GMU Message-ID: <20260528-adreno-810-v7-1-7fe7fdd97fc2@pm.me> In-Reply-To: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> References: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 4f032d334d990370280c087567951f68f6710d00 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Adreno 810 GMU in the dt-binding specification. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- .../devicetree/bindings/display/msm/gmu.yaml | 30 ++++++++++++++++++= ++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index 93e5e6e19754..8578c2f8122e 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -300,6 +300,36 @@ allOf: required: - qcom,qmp =20 + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-810.0 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: hub + - if: properties: compatible: --=20 2.53.0 From nobody Mon Jun 8 15:38:17 2026 Received: from mail-43102.protonmail.ch (mail-43102.protonmail.ch [185.70.43.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12E7D3B19CD; Thu, 28 May 2026 09:48:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.102 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961727; cv=none; b=lLeCX0SBPEmaqfaDZgGd/T7cdu3hL5lrizEgT71cYnDatzoW8IGUyNG39Wx/ip1dIAcsK/0SUtQSHy5gWGRE0XNy4u/Yvy11ltsZwXbm+aONVkPWqKfIfrQfRKyMrfRL3fACIDmFXkvAnETyOMpLyouxVunjEBmso75v28GKXxA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961727; c=relaxed/simple; bh=EOfkEqoI59XmVVmUQgLQY7QKKEQ7Ln2MOTubLdT2nN8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fxRv2jmwprw7ZUr4+QmzmwXMOd8BCZfE0moXGHVSweJ7W2TLQJwbUjtCkFACysJ9ICPpdnu3clVlliaFJMUZlijbFdb2B0igLQD4wzFtU96CdlcfhQbtz5rLfKsacWM0H9FRxar7V7ollLEu+7YzU3PA0YUUrYBd9PilPjvhd7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=Hz8PiSFs; arc=none smtp.client-ip=185.70.43.102 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="Hz8PiSFs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1779961722; x=1780220922; bh=6quOadJw0T40j2a2pj1RIqbFfyX3sZvPfSLjCbf9oyo=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Hz8PiSFshssZhY+P9tiFU17cGqAmBJOZ3nx3xv9n4sShdSKzYGfwhmU+Gpfeo4yCz M2x7Sy+apvxVC2Ok+6YKind9vQc45ZRrbIrvWWIAbZxVsib7xZK0DIxHGlsPRPSKiJ jDUWHeuriJjfRrQ6WiUF//Ru6/PE5hL15CJvUd8thD3v+xU73/lBZKy4SmhlAAbadu 2mLIOUP5FVwWMKQUzxr+jrUo27VX2jjCfqWOfevSpP5AcDt8y4+SGzbCbpABgCSsaF sdiG3x7lW7rH8OVB06odeU0ApkkW4PtvI8yDo1DFpM8jrazi2DmiNkRCGTse2Vdydn gjd0D0kjL1/NA== Date: Thu, 28 May 2026 09:48:39 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH v7 2/6] dt-bindings: display/msm/gpu: Document Adreno 810 GPU Message-ID: <20260528-adreno-810-v7-2-7fe7fdd97fc2@pm.me> In-Reply-To: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> References: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: b0700308c569d04cc9deec9ef3d4d5b4f1f32221 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the GPU compatible string used for the Adreno 810. Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index 77caacd0fb3f..a40899e5ea58 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -415,7 +415,9 @@ allOf: properties: compatible: contains: - const: qcom,adreno-44070001 + enum: + - qcom,adreno-44010000 + - qcom,adreno-44070001 then: properties: reg: @@ -449,6 +451,7 @@ allOf: - qcom,adreno-43050a01 - qcom,adreno-43050c01 - qcom,adreno-43051401 + - qcom,adreno-44010000 - qcom,adreno-44070001 =20 then: # Starting with A6xx, the clocks are usually defined in the GMU = node --=20 2.53.0 From nobody Mon Jun 8 15:38:17 2026 Received: from mail-43103.protonmail.ch (mail-43103.protonmail.ch [185.70.43.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC806377EA7; Thu, 28 May 2026 09:48:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.103 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961735; cv=none; b=r7MEvnw1aQgdJlFT6DRLLLNZUEl9vMPEIoqMzCbQ3Yci/dygRn9zCH8I10XHThsMvc+64FxOfDoYqPVmiDdm/3nChJld665lOPgEoZCsLGMnHL7vtilDU8SJjUHuTkUCvq9l6K/7hyZjmgcon0Uv8HfCL59vh/Cka2CpPhP/mO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961735; c=relaxed/simple; bh=Jl/G/gTDl8uKXDIINM6JMF3s1+09PskGsSGzYYZoi8o=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dSb1ig6rw09svwpZ0XWXivmEcHrMK8+yD7CHKP7sGDFm5AR8jC5rCl6F1BXCh2YIcch1SuZ+PAfObk3ehGTTCnLX2NP8/V/JVvqvcgSXwyKXsNt5SPrwwaP+EoNHGpfkhup8pt2LkJVn4WUFs5JkLQz/Thf6vinP8pqgaQPnrtA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=R5GMD4Yn; arc=none smtp.client-ip=185.70.43.103 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="R5GMD4Yn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1779961731; x=1780220931; bh=Pwcu63ikJrBUWs1LIH0P56ShN/z0EHbd37jIzWPzl+k=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=R5GMD4YnxJLE1otYkHJctejHxg5YO9E4v7pSgxICpvdJ/tn5NY41hGjSBuneCxIGa /rPn0qunGvZdNdsh4tT7sYSSpdzuFk17mnWd7GyPiu2a5PKKbrWZZi2w9eCf7iF6nL 0ixtiD5Rl+FaqNwNZtS1vmaUZJF/gPZtyqRCXQjjXfg5wqvO7HTKR0GcgQfcWfDoSj tr78vlMPFJEpXR5kNayE6OrXsW9qREhyPJFbkAnz5qjUdoA54nPmZkAPXMS3ee+DkJ F8IJ+DRA+fMVbbgqmTdwwKBSPsOhrks/QMdIICL8ouqeIl8zj9g08VZtjeYC5wxHzD rKqouUpy7U+Lg== Date: Thu, 28 May 2026 09:48:47 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH v7 3/6] drm/msm/adreno: rename llc_mmio to cx_misc_mmio Message-ID: <20260528-adreno-810-v7-3-7fe7fdd97fc2@pm.me> In-Reply-To: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> References: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: c5e8ecdd86c55dddfd1f425e8bf6ea86ceb3c4c6 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This region is used for more than just LLCC, it also provides access to software fuse values (raytracing, etc). Rename relevant symbols from _llc to _cx_misc for use in a follow up change that decouples this from LLCC. Reviewed-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++-------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 14 +++++++------- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 47b5702e1b40..2e5d7b53a0c3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -947,7 +947,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsi= gned int state) =20 /* Turn on TCM (Tightly Coupled Memory) retention */ if (adreno_is_a7xx(adreno_gpu)) - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); + a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); else if (!adreno_is_a8xx(adreno_gpu)) gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); =20 @@ -1215,7 +1215,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx= _gpu) if (!qcom_scm_is_available()) { dev_warn_once(gpu->dev->dev, "SCM is not available, poking fuse register\n"); - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, + a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); @@ -1236,7 +1236,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx= _gpu) * firmware, find out whether that's the case. The scm call * above sets the fuse register. */ - fuse_val =3D a6xx_llc_read(a6xx_gpu, + fuse_val =3D a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE); adreno_gpu->has_ray_tracing =3D !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); @@ -1343,7 +1343,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) =20 /* Check to see if we are doing a cold or warm boot */ if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { - status =3D a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) =3D=3D= 1 ? + status =3D a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) = =3D=3D 1 ? GMU_WARM_BOOT : GMU_COLD_BOOT; } else if (gmu->legacy) { status =3D gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) =3D=3D 1 ? diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index ea91e8bb9a21..d7f446e92098 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2038,7 +2038,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->llc_mmio)) + if (IS_ERR(a6xx_gpu->cx_misc_mmio)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2077,14 +2077,14 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx= _gpu) * pagetables */ if (!a6xx_gpu->have_mmu500) { - a6xx_llc_write(a6xx_gpu, + a6xx_cx_misc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); =20 /* * Program cacheability overrides to not allocate cache * lines on a write miss */ - a6xx_llc_rmw(a6xx_gpu, + a6xx_cx_misc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); return; } @@ -2097,7 +2097,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->llc_mmio)) + if (IS_ERR(a6xx_gpu->cx_misc_mmio)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2150,15 +2150,15 @@ static void a6xx_llc_slices_init(struct platform_de= vice *pdev, of_node_put(phandle); =20 if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->llc_mmio =3D msm_ioremap(pdev, "cx_mem"); + a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); else - a6xx_gpu->llc_mmio =3D NULL; + a6xx_gpu->cx_misc_mmio =3D NULL; =20 a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); =20 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); + a6xx_gpu->cx_misc_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2695,7 +2695,7 @@ static int a6xx_read_speedbin(struct device *dev, str= uct a6xx_gpu *a6xx_gpu, return ret; =20 if (info->quirks & ADRENO_QUIRK_SOFTFUSE) { - *speedbin =3D a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMI= T_STATUS); + *speedbin =3D a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_= LIMIT_STATUS); *speedbin =3D A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*spe= edbin); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index f60a0801a62d..b50c57f427b4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -112,7 +112,7 @@ struct a6xx_gpu { =20 bool has_whereami; =20 - void __iomem *llc_mmio; + void __iomem *cx_misc_mmio; void *llc_slice; void *htw_llc_slice; bool have_mmu500; @@ -250,19 +250,19 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *g= pu) return true; } =20 -static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 ma= sk, u32 or) +static inline void a6xx_cx_misc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u3= 2 mask, u32 or) { - return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); + return msm_rmw(a6xx_gpu->cx_misc_mmio + (reg << 2), mask, or); } =20 -static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) +static inline u32 a6xx_cx_misc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) { - return readl(a6xx_gpu->llc_mmio + (reg << 2)); + return readl(a6xx_gpu->cx_misc_mmio + (reg << 2)); } =20 -static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 = value) +static inline void a6xx_cx_misc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, = u32 value) { - writel(value, a6xx_gpu->llc_mmio + (reg << 2)); + writel(value, a6xx_gpu->cx_misc_mmio + (reg << 2)); } =20 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index bff57fdc1ae0..66a6c9c714fa 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -104,7 +104,7 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) return; } =20 - slice_mask &=3D a6xx_llc_read(a6xx_gpu, + slice_mask &=3D a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL); =20 a6xx_gpu->slice_mask =3D slice_mask; --=20 2.53.0 From nobody Mon Jun 8 15:38:17 2026 Received: from mail-106119.protonmail.ch (mail-106119.protonmail.ch [79.135.106.119]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C6C83B52E9 for ; Thu, 28 May 2026 09:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.119 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961760; cv=none; b=HAdY/gZD+7BxKCg57eDCHEhSOhrMrH7S5nttI5zY9HZNaitR8VRvfL5W1F2Kzz5/CgE7fMb5iRCTNT1FCIeeivmJ1u7IgNm1i5hjdypxy++fVy3z/JkD5gwXT620mV0e5UwfiI9owmDjupJ+5zK4NRFoFLdh9AYPRYTQ+CnoY8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961760; c=relaxed/simple; bh=4GIvf6g25dTeIEkU4yrk2b1GS2dt1d/k+38Dt9gY7H8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DCnIG7F9aqWtD0Rooh3GUQLAs5uINEuGM+HJyvpdP1uy7tAHCr8VjSX9Y8bLNu1uFDJbUaIutFub7QzQSMIGPyH9qkHqtiiu3rlsE5jnvqLRCmPNmX+OzlZQoVfIdz9bFeiJsQx1xYZtU7fQd2Rl71IuEIxaUxerVg3IkJNr1E4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=o4z7Ys61; arc=none smtp.client-ip=79.135.106.119 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="o4z7Ys61" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1779961750; x=1780220950; bh=4GIvf6g25dTeIEkU4yrk2b1GS2dt1d/k+38Dt9gY7H8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=o4z7Ys61t3P+B+ziURs+oZdCqJ4NtuId2lEVKgGvPlqkX0T4aeBbhSBVA3RbJ4m/h jPU4Zv50P0UYRGRrSW8BX2etngPWd462ZtBjw/DDtb46ZcIVf3lCgu40JNm8lsCZs+ T1hbhkZ2g6osNDyCioaFXzXGOwqVJNh+4fmguurUBzSt3xvL6LVtwnO7dJIchzYyOP Rubjm3O+bR3ZCwI6cpogE5m0RctzBEayoBSaub79Ca8THVo/R0EJP/I6bDH1SJ011P Gftettr+0/xfwd3lDk0cOCFXIZu2O8TYgoUMZxfi5Z+k8J5XBTe00LiAYnvt8U8p0n i8ju91tm4GXqA== Date: Thu, 28 May 2026 09:48:57 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH v7 4/6] drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC Message-ID: <20260528-adreno-810-v7-4-7fe7fdd97fc2@pm.me> In-Reply-To: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> References: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: fc7329e3a68a6e39061236e0de59472a1ac92049 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Platforms without a LLCC (e.g. milos) still need to be able to read and write to the cx_mem region. Previously if LLCC slices were unavailable the cx_misc_mmio mapping was overwritten with ERR_PTR, causing a crash when the GMU later accessed cx_mem. Move the cx_misc_mmio mapping out of a6xx_llc_slices_init() into a6xx_gpu_init() so that cx_mem mapping is independent of LLCC. Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++++++++++++++++---------------= ---- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index d7f446e92098..ac9597baeb44 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2038,7 +2038,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2097,7 +2097,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2134,31 +2134,12 @@ static void a6xx_llc_slices_destroy(struct a6xx_gpu= *a6xx_gpu) static void a6xx_llc_slices_init(struct platform_device *pdev, struct a6xx_gpu *a6xx_gpu, bool is_a7xx) { - struct device_node *phandle; - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) return; =20 - /* - * There is a different programming path for A6xx targets with an - * mmu500 attached, so detect if that is the case - */ - phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); - a6xx_gpu->have_mmu500 =3D (phandle && - of_device_is_compatible(phandle, "arm,mmu-500")); - of_node_put(phandle); - - if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); - else - a6xx_gpu->cx_misc_mmio =3D NULL; - a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); - - if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->cx_misc_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2756,6 +2737,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devic= e *dev) struct platform_device *pdev =3D priv->gpu_pdev; struct adreno_platform_config *config =3D pdev->dev.platform_data; const struct adreno_info *info =3D config->info; + struct device_node *phandle; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; @@ -2806,6 +2788,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 + /* + * There is a different programming path for A6xx targets with an + * mmu500 attached, so detect if that is the case + */ + phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); + a6xx_gpu->have_mmu500 =3D (phandle && + of_device_is_compatible(phandle, "arm,mmu-500")); + of_node_put(phandle); + + if (is_a7xx || !a6xx_gpu->have_mmu500) + a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); + else + a6xx_gpu->cx_misc_mmio =3D NULL; + ret =3D a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); --=20 2.53.0 From nobody Mon Jun 8 15:38:17 2026 Received: from mail-43100.protonmail.ch (mail-43100.protonmail.ch [185.70.43.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54EA63B2FF5; Thu, 28 May 2026 09:49:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961755; cv=none; b=G0eWp9+jfJePMHnL1zcuttiTqaVtTqnYUg/kyd/4MiqJCMdELsrBulMhE1/KTcNm4uXaFi59VcMn+CW1VFEaVgYBBIjOhiK7tFDu022RawzqidL6hg9zb4WFBpj7CYTaZa5/RaxC/7N3VefwiAT8heyLvH7s2z4wEtdGn0Cwgh0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961755; c=relaxed/simple; bh=4cNpgUFkxkNEbpjpaCfVK8wi7WkJctG6LthT6aKiF/s=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fqafyzLTHfouHMLBYxPa5Y9HrNqCFXGwCcHPmGnTYlHyWZZydGZ1dUdzyPoXPofpph41T6J1dl8Y4eyNB36Nog1ci5Nfdw4kPD3wTMJHZ/497ZXrl2m8eAdKq/F87DXEp2Fs2gWyFzmju0MjirwIkGOGX8+7gybSef9Oh2NnTtY= ARC-Authentication-Results: i=1; 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charset="utf-8" A8XX GPUs have two sets of protect registers: 64 global slots and 16 pipe specific slots. The last-span-unbound feature is only available on pipe protect registers, and should always target pipe slot 15. This matches the downstream driver which hardcodes pipe slot 15 for all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on A810. Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 66a6c9c714fa..5e2d15e42452 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -265,8 +265,8 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) * Last span feature is only supported on PIPE specific register. * So update those here */ - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); - a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); =20 a8xx_aperture_clear(gpu); } --=20 2.53.0 From nobody Mon Jun 8 15:38:17 2026 Received: from mail-244121.protonmail.ch (mail-244121.protonmail.ch [109.224.244.121]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49B0A3B27E5 for ; Thu, 28 May 2026 09:49:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.121 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961774; cv=none; b=OWEVKHC9HiYA+4qRyJqEST/1mnmiwsX6J6YKFF2uDJw+183NoE/OE1NxC0NqySbWLP4Yqh/B2OKIwswr+D+WjkyP9V1BnAR0UhnO0QsAUNyzyommgBKdpajcIFiRlIbOJHLCm5k35ceOEX8FeZrdSZLEwgyuu3PfoxqOfhEInUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779961774; c=relaxed/simple; bh=MzuhaxepM5/KRPM7wBao0X2LSDQ3ffQ/74C94fXIQ8w=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LO2C+LbFsVjkkn0q2WWqAO+WqNitYxL3VuGE5Xt+IxPYCKJ/T1QhonoDG3/XocKKQzUpydClWlKt5zf9kJDw+Nt27yDMmk7Gy0ng/ZOkJHED79Bsak/UhYLRVIoQC40zKfnoCKChO0h72pU73R28OxTpr3BsKTVhdsv8C9k4gEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=DLr3gyKx; arc=none smtp.client-ip=109.224.244.121 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="DLr3gyKx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1779961764; x=1780220964; bh=pzmm1qBq9/agtzNc7qO0Y6QV4Q4byLeGlVb8xvZTcgk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=DLr3gyKxSd4YGac9JG4ZDugDhb4e03MYTsDr1l0F08AhHumTaBW+S/d3CEogv5Oop ykj9mCGlkmqzOTeFXnaiASjDnPzK16iYQzf7QiuOqk1IS8+glsijw82m5PtOy/BEfQ S1a0rBvK+fpZEljvobOjud9ijDj2nbPujYWf8KbTRt+HbL9TbzfReJDusOGrYjg0BO +YjFPeOPV1lJLrlFcf0gG3Z/LyLXjBoc6BCV3849lbHYODFCq9jNbymsh6RA8GlDVM ryTYhPVHY1sNQQH/bwlocS5pSY01q/04DdSS/KsSKBYwPne+EwzxUUvitskqTADTjF cW4BpTnVKX9bA== Date: Thu, 28 May 2026 09:49:16 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH v7 6/6] drm/msm/adreno: add Adreno 810 GPU support Message-ID: <20260528-adreno-810-v7-6-7fe7fdd97fc2@pm.me> In-Reply-To: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> References: <20260528-adreno-810-v7-0-7fe7fdd97fc2@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 968e0fa4248611ac9bff57573ec8890570a447e8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add catalog entry and register configuration for the Adreno 810 found in Qualcomm SM7635 (Milos) based devices. Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 298 ++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 + 2 files changed, 303 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 550ff3a9b82e..3e6f409d13a2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1799,6 +1799,261 @@ static const struct adreno_reglist_pipe x285_dyn_pw= rup_reglist_regs[] =3D { }; DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist); =20 +static const struct adreno_reglist_pipe a810_nonctxt_regs[] =3D { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR)= }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) |= BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000023, BIT(PIPE_BV) }, /* Avoid partia= l waves at VFD */ + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + /* + * BIT(22): Disable PS out of order retire + * BIT(23): Enable half wave mode and MM instruction src&dst is half prec= ision + */ + { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + /* Disable write slow pointer in data phase queue */ + { REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) }, + { }, +}; + +static const u32 a810_protect_regs[] =3D { + A6XX_PROTECT_RDONLY(0x00000, 0x03a3), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x0026), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0787), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x20000, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0381), + A6XX_PROTECT_NORDWR(0x27882, 0x0001), + A6XX_PROTECT_NORDWR(0x27c02, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a810_protect, 64); + +static const uint32_t a810_pwrup_reglist_regs[] =3D { + REG_A6XX_UCHE_MODE_CNTL, + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, + REG_A8XX_UCHE_GBIF_GX_CONFIG, + REG_A8XX_UCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_MODE_CNTL, + REG_A8XX_UCHE_CCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_TRAP_BASE, + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_HW_DBG_CNTL, + REG_A8XX_UCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_TRAP_BASE, + REG_A8XX_UCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CLIENT_PF, + REG_A8XX_RB_CMP_NC_MODE_CNTL, + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, + REG_A7XX_SP_READ_SEL, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL1, + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), +}; +DECLARE_ADRENO_REGLIST_LIST(a810_pwrup_reglist); + +static const u32 a810_ifpc_reglist_regs[] =3D { + REG_A8XX_RBBM_NC_MODE_CNTL, + REG_A8XX_RBBM_PERFCTR_CNTL, + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A7XX_SP_CHICKEN_BITS_2, + REG_A7XX_SP_CHICKEN_BITS_3, + REG_A6XX_SP_PERFCTR_SHADER_MASK, + REG_A8XX_CP_PROTECT_GLOBAL(0), + REG_A8XX_CP_PROTECT_GLOBAL(1), + REG_A8XX_CP_PROTECT_GLOBAL(2), + REG_A8XX_CP_PROTECT_GLOBAL(3), + REG_A8XX_CP_PROTECT_GLOBAL(4), + REG_A8XX_CP_PROTECT_GLOBAL(5), + REG_A8XX_CP_PROTECT_GLOBAL(6), + REG_A8XX_CP_PROTECT_GLOBAL(7), + REG_A8XX_CP_PROTECT_GLOBAL(8), + REG_A8XX_CP_PROTECT_GLOBAL(9), + REG_A8XX_CP_PROTECT_GLOBAL(10), + REG_A8XX_CP_PROTECT_GLOBAL(11), + REG_A8XX_CP_PROTECT_GLOBAL(12), + REG_A8XX_CP_PROTECT_GLOBAL(13), + REG_A8XX_CP_PROTECT_GLOBAL(14), + REG_A8XX_CP_PROTECT_GLOBAL(15), + REG_A8XX_CP_PROTECT_GLOBAL(16), + REG_A8XX_CP_PROTECT_GLOBAL(17), + REG_A8XX_CP_PROTECT_GLOBAL(18), + REG_A8XX_CP_PROTECT_GLOBAL(19), + REG_A8XX_CP_PROTECT_GLOBAL(20), + REG_A8XX_CP_PROTECT_GLOBAL(21), + REG_A8XX_CP_PROTECT_GLOBAL(22), + REG_A8XX_CP_PROTECT_GLOBAL(23), + REG_A8XX_CP_PROTECT_GLOBAL(24), + REG_A8XX_CP_PROTECT_GLOBAL(25), + REG_A8XX_CP_PROTECT_GLOBAL(26), + REG_A8XX_CP_PROTECT_GLOBAL(27), + REG_A8XX_CP_PROTECT_GLOBAL(28), + REG_A8XX_CP_PROTECT_GLOBAL(29), + REG_A8XX_CP_PROTECT_GLOBAL(30), + REG_A8XX_CP_PROTECT_GLOBAL(31), + REG_A8XX_CP_PROTECT_GLOBAL(32), + REG_A8XX_CP_PROTECT_GLOBAL(33), + REG_A8XX_CP_PROTECT_GLOBAL(34), + REG_A8XX_CP_PROTECT_GLOBAL(35), + REG_A8XX_CP_PROTECT_GLOBAL(36), + REG_A8XX_CP_PROTECT_GLOBAL(37), + REG_A8XX_CP_PROTECT_GLOBAL(38), + REG_A8XX_CP_PROTECT_GLOBAL(39), + REG_A8XX_CP_PROTECT_GLOBAL(40), + REG_A8XX_CP_PROTECT_GLOBAL(41), + REG_A8XX_CP_PROTECT_GLOBAL(42), + REG_A8XX_CP_PROTECT_GLOBAL(43), + REG_A8XX_CP_PROTECT_GLOBAL(44), + REG_A8XX_CP_PROTECT_GLOBAL(45), + REG_A8XX_CP_PROTECT_GLOBAL(46), + REG_A8XX_CP_PROTECT_GLOBAL(47), + REG_A8XX_CP_PROTECT_GLOBAL(48), + REG_A8XX_CP_PROTECT_GLOBAL(49), + REG_A8XX_CP_PROTECT_GLOBAL(50), + REG_A8XX_CP_PROTECT_GLOBAL(51), + REG_A8XX_CP_PROTECT_GLOBAL(52), + REG_A8XX_CP_PROTECT_GLOBAL(53), + REG_A8XX_CP_PROTECT_GLOBAL(54), + REG_A8XX_CP_PROTECT_GLOBAL(55), + REG_A8XX_CP_PROTECT_GLOBAL(56), + REG_A8XX_CP_PROTECT_GLOBAL(57), + REG_A8XX_CP_PROTECT_GLOBAL(58), + REG_A8XX_CP_PROTECT_GLOBAL(59), + REG_A8XX_CP_PROTECT_GLOBAL(60), + REG_A8XX_CP_PROTECT_GLOBAL(61), + REG_A8XX_CP_PROTECT_GLOBAL(62), + REG_A8XX_CP_PROTECT_GLOBAL(63), +}; +DECLARE_ADRENO_REGLIST_LIST(a810_ifpc_reglist); + +static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] =3D { + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE= _BV) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(a810_dyn_pwrup_reglist); + static const struct adreno_reglist_pipe a840_nonctxt_regs[] =3D { { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, @@ -2193,6 +2448,48 @@ static const struct adreno_info a8xx_gpus[] =3D { { 252, 2 }, { 221, 3 }, ), + }, { + .chip_ids =3D ADRENO_CHIP_IDS(0x44010000), + .family =3D ADRENO_8XX_GEN1, + .fw =3D { + [ADRENO_FW_SQE] =3D "gen80300_sqe.fw", + [ADRENO_FW_GMU] =3D "gen80300_gmu.bin", + }, + .gmem =3D SZ_512K + SZ_64K, + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs =3D &a8xx_gpu_funcs, + .zapfw =3D "gen80300_zap.mbn", + .a6xx =3D &(const struct a6xx_info) { + .protect =3D &a810_protect, + .nonctxt_reglist =3D a810_nonctxt_regs, + .pwrup_reglist =3D &a810_pwrup_reglist, + .dyn_pwrup_reglist =3D &a810_dyn_pwrup_reglist, + .ifpc_reglist =3D &a810_ifpc_reglist, + .gbif_cx =3D a840_gbif, + .max_slices =3D 1, + .gmu_chipid =3D 0x8030000, + .bcms =3D (const struct a6xx_bcm[]) { + { .name =3D "SH0", .buswidth =3D 16 }, + { .name =3D "MC0", .buswidth =3D 4 }, + { + .name =3D "ACV", + .fixed =3D true, + .perfmode =3D BIT(2), + .perfmode_bw =3D 10687500, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size =3D 4558 * SZ_1K, + .speedbins =3D ADRENO_SPEEDBINS( + { 0, 0 }, + { 242, 1 }, + { 221, 2 }, + ), } }; =20 @@ -2205,4 +2502,5 @@ static inline __always_unused void __build_asserts(vo= id) BUILD_BUG_ON(a660_protect.count > a660_protect.count_max); BUILD_BUG_ON(a690_protect.count > a690_protect.count_max); BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); + BUILD_BUG_ON(a810_protect.count > a810_protect.count_max); } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index ec643b84646b..d88eb8ecf417 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -592,6 +592,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gp= u) return gpu->info->family >=3D ADRENO_8XX_GEN1; } =20 +static inline int adreno_is_a810(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x44010000; +} + static inline int adreno_is_x285(struct adreno_gpu *gpu) { return gpu->info->chip_ids[0] =3D=3D 0x44070001; --=20 2.53.0