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Wed, 27 May 2026 13:24:36 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:1c3e:1134:26fb:2a51]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454a0cd5sm514992175e9.10.2026.05.27.13.24.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 13:24:36 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2] arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes Date: Wed, 27 May 2026 21:24:30 +0100 Message-ID: <20260527202430.606341-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Enable the xSPI0 and xSPI1 controllers on the RZ/T2H N2H EVK board. Configure the xSPI0 controller interface to 1-bit (x1) mode, even though the connected MX25LW51245 octal flash device supports octal mode. Add a corresponding inline hardware comment detailing this restriction; operating in octal mode causes the BootROM to fail loading the first-stage bootloader following a Watchdog Timer (WDT) reset. Configure the xSPI1 controller interface connected to the AT25SF128A flash device for 4-bit (x4) mode to utilize all available data lines. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - Dropped CKN pin - Added ECS pin configuration for T2H EVK - Added Switch settings for both T2H and N2H EVKs - Fixed partition address for xSPI0 flash device - Added spi-max-frequency property for both xSPI controllers - Dropped grouping the pinctrl into subnodes for XSPI1 and for XSPI0 merged the ctrl and data pins into a single group v1: https://lore.kernel.org/all/20260526204045.3481604-1-prabhakar.mahadev-= lad.rj@bp.renesas.com/ Note, - Ive reabased the patch on top of patch [0]. - Sending just this single patch as SoC DTSI patches have been reviwed and are queued for merging. [0] https://lore.kernel.org/all/20260514210220.7616-1-fabrizio.castro.jz@re= nesas.com/ --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 15 +++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 127 ++++++++++++++++++ 2 files changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 4c0e52850ca9..e9ed2de128f6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -345,3 +345,18 @@ usb_pins: usb-pins { }; }; =20 +/* + * XSPI0 Pin Configuration: + * ------------------------ + * Signal | Pin | SW5 + * -----------|---------|--------------- + * XSPI0_ECS | P07_5 | 5: OFF, 6: ON + */ +&xspi0_pins { + ecs-pins { + pinmux =3D ; /* XSPI0_ECS0 */ + drive-strength-microamp =3D <2500>; + input-schmitt-disable; + slew-rate =3D <0>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/a= rm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 46f4aaac0478..cdb5096a71b3 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ =20 +#include #include #include #include @@ -20,6 +21,8 @@ aliases { mmc0 =3D &sdhi0; mmc1 =3D &sdhi1; serial0 =3D &sci0; + spi0 =3D &xspi0; + spi1 =3D &xspi1; }; =20 chosen { @@ -456,6 +459,45 @@ ctrl-pins { input-schmitt-disable; }; }; + + xspi0_pins: xspi0-group { + ctrl-data-pins { + pinmux =3D , /* XSPI0_CKP */ + , /* XSPI0_CS0 */ + , /* XSPI0_DS */ + , /* XSPI0_IO0 */ + , /* XSPI0_IO1 */ + , /* XSPI0_IO2 */ + , /* XSPI0_IO3 */ + , /* XSPI0_IO4 */ + , /* XSPI0_IO5 */ + , /* XSPI0_IO6 */ + , /* XSPI0_IO7 */ + ; /* XSPI0_RESET0 */ + drive-strength-microamp =3D <9000>; + input-schmitt-disable; + slew-rate =3D <1>; + }; + }; + + /* + * XSPI1 Pin Configuration: + * ------------------------ + * Signal | Pin | RZ/T2H (SW1) | RZ/N2H (DSW2) + * -----------|----------|---------------|--------------- + * ALL | Multiple | 6: ON | 6: ON + */ + xspi1_pins: xspi1-pins { + pinmux =3D , /* XSPI1_CKP */ + , /* XSPI1_CS0 */ + , /* XSPI1_IO0 */ + , /* XSPI1_IO1 */ + , /* XSPI1_IO2 */ + ; /* XSPI1_IO3 */ + drive-strength-microamp =3D <9000>; + input-schmitt-enable; + slew-rate =3D <1>; + }; }; =20 &sci0 { @@ -520,3 +562,88 @@ &wdt2 { timeout-sec =3D <60>; }; =20 +&xspi0 { + pinctrl-0 =3D <&xspi0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + assigned-clocks =3D <&cpg CPG_CORE R9A09G077_XSPI_CLK0>; + assigned-clock-rates =3D <50000000>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + vcc-supply =3D <®_3p3v>; + m25p,fast-read; + /* + * Configure for 1-bit mode to prevent the BootROM from failing + * to load the first-stage bootloader following a watchdog reset. + */ + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <1>; + spi-max-frequency =3D <50000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "bl2-0"; + reg =3D <0x00000000 0x00060000>; + read-only; + }; + + partition@60000 { + label =3D "fip-0"; + reg =3D <0x00060000 0x007a0000>; + read-only; + }; + + partition@800000 { + label =3D "user-0"; + reg =3D <0x800000 0x003800000>; + }; + }; + }; +}; + +&xspi1 { + pinctrl-0 =3D <&xspi1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + assigned-clocks =3D <&cpg CPG_CORE R9A09G077_XSPI_CLK1>; + assigned-clock-rates =3D <50000000>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + vcc-supply =3D <®_3p3v>; + m25p,fast-read; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <50000000>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "bl2-1"; + reg =3D <0x00000000 0x00060000>; + }; + + partition@60000 { + label =3D "fip-1"; + reg =3D <0x00060000 0x007a0000>; + }; + + partition@800000 { + label =3D "user-1"; + reg =3D <0x800000 0x800000>; + }; + }; + }; +}; --=20 2.54.0