From nobody Mon Jun 8 17:47:14 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17EBB15687D for ; Wed, 27 May 2026 17:44:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779903847; cv=none; b=twOzFD8oeZx9HV7kWPMH9CwMcxK/KmIp3mWcCkSIjREoRhGRyf0P94cwj6PCVpNlYSssqFEksC6CUhByyFpmnHpXrAL0vFp36jNRSZGOvYQ/cplj+YG67uzFp0DiukwKhK+l5ORhxx2cgro+A5Mv6AsZppcVMADWQMZtIQUrFQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779903847; c=relaxed/simple; bh=4dM+MyiSqvp+Jq7wcMz9CiXdA6assxQeJuKyAT0TKZc=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=XeBNFXhDh4r8VmhTpO0V+HS+p+Lhq9CVSygxjlonLzlQlLx6FEZ8MXZodFB435iVSFYTQHZVN4HGwmIHcN0MYFXnh54lTxMs0lYKJG4XZRvAAR3OEzIRpnElKhdm1n32kJ9Gql0SjNd2vt4gvUIHQoQ3TpEy+U8V8cAjeKdruqQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=TjnqpcY1; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="TjnqpcY1" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-2b4530a90fdso67149475ad.1 for ; Wed, 27 May 2026 10:44:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1779903843; x=1780508643; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=3sU0RPFbAlDPXpf7+JC6NZ9VwzjnBo5QhV+gWzHYteo=; b=TjnqpcY150n2ARgba1RKS2JOFYkT7xCbmvruo4cbCGtzZBqLgqLVuApvKoTK8RX7bL pWH/QLRcokrEPoRd4g4g9veWLp/y6t4H83QjrpCCP1Cm8GbDxsKepSC0Had0PJSdyA6C z/BuUxxu9TFvy0qkJorJpyMwTSakP7r1Y+07wSbfe2jytRfUUNB6JpOvOHzq2osbG+gr ED9NsRFS4bagd15h3m72MB7y0gAeA8NJu9oLE6vNhiA4ElmrbY3ltHw1NMeNYofF6rfj Zjg+jcsqm11AUV0McAOO8hB0p9eyzYjcZ2RsP+sbaPghGHtpxCLUJLKENh4v7PnPb4Sy SHxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779903843; x=1780508643; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=3sU0RPFbAlDPXpf7+JC6NZ9VwzjnBo5QhV+gWzHYteo=; b=Z1H6LXWxRSxH+Q+A6yBgEg0ynPNS5eSy2No+XxVRscAZ6dXTHEiITbDuCXKKb0sSwN /onEwxBfGmnPt5mL2unxx0ljPV1rMy6j/CsC+v7jqQdP0SQf8WKCZiO/mPXtlRKq/eSz Dxi0txm2GhJOebrneAXXLVjViAo8Mzc/jh4+xGzYzKLhc7tKqSB/lI+49TghcCBaCRfb 6mh8ZT/CJTLTLB2txxlFrnu/Omsxa9hHY1b08YbIHgmy4mZSWvAqw9JC35fvFG+g9Mft FupOkek4GfqoM67P8jrpON00Dk+YFiAjDy0GOktkoo4XfiTZSp/L92wchP4M/zcgfthN LgTg== X-Forwarded-Encrypted: i=1; AFNElJ+Mc1cu5gc+VamcoHsA7d7/PgdHystzltVCObdlf35uKWfSAy1Uj5r+nZRCf/40QqXTBNWxAvNXJdw4JOY=@vger.kernel.org X-Gm-Message-State: AOJu0YxZqId+7rq/+scRqeggI3eCRVkzni95Kj3VmZog8TnS6tVcqqWj GwHcq8ag6DxqgGkPS3EjLM2I9Hwj8woYrpUw6jeuwzYTVR11gu6e5bmdzu8lkNYthinWGHAVzv4 gwR/mouKmO3txEA== X-Received: from plbbf3.prod.google.com ([2002:a17:902:b903:b0:2be:b234:7438]) (user=jmattson job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:32ce:b0:2bd:eeb6:ff1b with SMTP id d9443c01a7336-2beb0390f7dmr272457635ad.4.1779903842482; Wed, 27 May 2026 10:44:02 -0700 (PDT) Date: Wed, 27 May 2026 10:43:43 -0700 In-Reply-To: <20260527174347.2356165-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260527174347.2356165-1-jmattson@google.com> X-Mailer: git-send-email 2.54.0.794.g4f17f83d09-goog Message-ID: <20260527174347.2356165-2-jmattson@google.com> Subject: [PATCH v4 1/5] KVM: x86: Consolidate CPUID fault handling for emulator and interception logic From: Jim Mattson To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, ctpence@google.com, David.Kaplan@amd.com, binbin.wu@linux.intel.com Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sean Christopherson Extract the logic for emulating CPUID faulting (where CPUID #GPs at CPL>0 outside of SMM) into a dedicated helper and use the helper for both the full emulator and the intercepted-CPUID paths. Opportunistically drop kvm_require_cpl(), as kvm_emulate_cpuid() was the one and only user. No functional change intended. Signed-off-by: Sean Christopherson [jim: Add EXPORT_STATIC_CALL_GPL(kvm_x86_get_cpl) so that KVM vendor modules can call kvm_is_cpuid_allowed(). Fix typo in commit message.] Signed-off-by: Jim Mattson Reviewed-by: Binbin Wu --- arch/x86/include/asm/kvm_host.h | 1 - arch/x86/kvm/cpuid.c | 5 +++-- arch/x86/kvm/cpuid.h | 8 ++++++++ arch/x86/kvm/emulate.c | 6 +----- arch/x86/kvm/kvm_emulate.h | 1 + arch/x86/kvm/x86.c | 19 +++++++------------ 6 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index d72051150bac..4c22b338ac7b 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -2321,7 +2321,6 @@ static inline void kvm_inject_emulated_page_fault(str= uct kvm_vcpu *vcpu, __kvm_inject_emulated_page_fault(vcpu, fault, false); } =20 -bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); =20 static inline int __kvm_irq_line_state(unsigned long *irq_state, diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index e69156b54cff..1c95d1fa3ead 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -2161,9 +2161,10 @@ int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) { u32 eax, ebx, ecx, edx; =20 - if (!is_smm(vcpu) && cpuid_fault_enabled(vcpu) && - !kvm_require_cpl(vcpu, 0)) + if (!kvm_is_cpuid_allowed(vcpu)) { + kvm_queue_exception_e(vcpu, GP_VECTOR, 0); return 1; + } =20 eax =3D kvm_rax_read(vcpu); ecx =3D kvm_rcx_read(vcpu); diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index 039b8e6f40ba..bc4a8428b836 100644 --- a/arch/x86/kvm/cpuid.h +++ b/arch/x86/kvm/cpuid.h @@ -7,6 +7,8 @@ #include #include =20 +#include "smm.h" + extern u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; extern bool kvm_is_configuring_cpu_caps __read_mostly; =20 @@ -192,6 +194,12 @@ static inline bool cpuid_fault_enabled(struct kvm_vcpu= *vcpu) MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; } =20 +static inline bool kvm_is_cpuid_allowed(struct kvm_vcpu *vcpu) +{ + return !cpuid_fault_enabled(vcpu) || is_smm(vcpu) || + !kvm_x86_call(get_cpl)(vcpu); +} + static __always_inline void kvm_cpu_cap_clear(unsigned int x86_feature) { unsigned int x86_leaf =3D __feature_leaf(x86_feature); diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 0a17a9ee6f32..585a8ceab220 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -3594,12 +3594,8 @@ static int em_sti(struct x86_emulate_ctxt *ctxt) static int em_cpuid(struct x86_emulate_ctxt *ctxt) { u32 eax, ebx, ecx, edx; - u64 msr =3D 0; =20 - ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); - if (!ctxt->ops->is_smm(ctxt) && - (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT) && - ctxt->ops->cpl(ctxt)) + if (!ctxt->ops->is_cpuid_allowed(ctxt)) return emulate_gp(ctxt, 0); =20 eax =3D reg_read(ctxt, VCPU_REGS_RAX); diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index f5df31a52996..3e375af15c03 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -230,6 +230,7 @@ struct x86_emulate_ops { struct x86_instruction_info *info, enum x86_intercept_stage stage); =20 + bool (*is_cpuid_allowed)(struct x86_emulate_ctxt *ctxt); bool (*get_cpuid)(struct x86_emulate_ctxt *ctxt, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool exact_only); bool (*guest_has_movbe)(struct x86_emulate_ctxt *ctxt); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 1578c0ecbbd1..72bd3cddb026 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -151,6 +151,7 @@ struct kvm_x86_ops kvm_x86_ops __read_mostly; #include EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); +EXPORT_STATIC_CALL_GPL(kvm_x86_get_cpl); =20 static bool __read_mostly ignore_msrs =3D 0; module_param(ignore_msrs, bool, 0644); @@ -1022,18 +1023,6 @@ void kvm_queue_exception_e(struct kvm_vcpu *vcpu, un= signed nr, u32 error_code) } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_queue_exception_e); =20 -/* - * Checks if cpl <=3D required_cpl; if true, return true. Otherwise queue - * a #GP and return false. - */ -bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) -{ - if (kvm_x86_call(get_cpl)(vcpu) <=3D required_cpl) - return true; - kvm_queue_exception_e(vcpu, GP_VECTOR, 0); - return false; -} - bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) { if ((dr !=3D 4 && dr !=3D 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE)) @@ -8829,6 +8818,11 @@ static int emulator_intercept(struct x86_emulate_ctx= t *ctxt, &ctxt->exception); } =20 +static bool emulator_is_cpuid_allowed(struct x86_emulate_ctxt *ctxt) +{ + return kvm_is_cpuid_allowed(emul_to_vcpu(ctxt)); +} + static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool exact_only) @@ -8966,6 +8960,7 @@ static const struct x86_emulate_ops emulate_ops =3D { .wbinvd =3D emulator_wbinvd, .fix_hypercall =3D emulator_fix_hypercall, .intercept =3D emulator_intercept, + .is_cpuid_allowed =3D emulator_is_cpuid_allowed, .get_cpuid =3D emulator_get_cpuid, .guest_has_movbe =3D emulator_guest_has_movbe, .guest_has_fxsr =3D emulator_guest_has_fxsr, --=20 2.54.0.794.g4f17f83d09-goog From nobody Mon Jun 8 17:47:14 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5BC342316B for ; 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Wed, 27 May 2026 10:44:03 -0700 (PDT) Date: Wed, 27 May 2026 10:43:44 -0700 In-Reply-To: <20260527174347.2356165-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260527174347.2356165-1-jmattson@google.com> X-Mailer: git-send-email 2.54.0.794.g4f17f83d09-goog Message-ID: <20260527174347.2356165-3-jmattson@google.com> Subject: [PATCH v4 2/5] KVM: x86: Prioritize CPUID faulting over CPUID VM-exits in nested VMX From: Jim Mattson To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, ctpence@google.com, David.Kaplan@amd.com, binbin.wu@linux.intel.com Cc: Jim Mattson , Sashiko Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Per the Intel SDM, "Certain exceptions have priority over VM exits. These include invalid-opcode exceptions, faults based on privilege level, and general-protection exceptions that are based on checking I/O permission bits in the task-state segment (TSS)." Ensure that when L2 executes CPUID at CPL > 0 while L1 has enabled CPUID faulting, KVM intercepts the exit in L0 and queues #GP rather than forwarding the CPUID VM-exit to L1. Empirical testing confirms that this #GP has higher precedence than a CPUID VM-exit on Granite Rapids (F/M/S 6/0xad/1). Fixes: db2336a80489 ("KVM: x86: virtualize cpuid faulting") Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260513224608.1859737-1-jmattson%40= google.com?part=3D3 Signed-off-by: Jim Mattson --- arch/x86/kvm/vmx/nested.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index a78ce0080963..30dcabc899a2 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -6552,6 +6552,8 @@ static bool nested_vmx_l0_wants_exit(struct kvm_vcpu = *vcpu, nested_evmcs_l2_tlb_flush_enabled(vcpu) && kvm_hv_is_tlb_flush_hcall(vcpu); #endif + case EXIT_REASON_CPUID: + return !kvm_is_cpuid_allowed(vcpu); default: break; } --=20 2.54.0.794.g4f17f83d09-goog From nobody Mon Jun 8 17:47:14 2026 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3AED450909 for ; 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Wed, 27 May 2026 10:44:04 -0700 (PDT) Date: Wed, 27 May 2026 10:43:45 -0700 In-Reply-To: <20260527174347.2356165-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260527174347.2356165-1-jmattson@google.com> X-Mailer: git-send-email 2.54.0.794.g4f17f83d09-goog Message-ID: <20260527174347.2356165-4-jmattson@google.com> Subject: [PATCH v4 3/5] KVM: x86: Remove supports_cpuid_fault() helper From: Jim Mattson To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, ctpence@google.com, David.Kaplan@amd.com, binbin.wu@linux.intel.com Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The function, supports_cpuid_fault(), tests specifically for guest support of Intel's CPUID faulting feature. It does not test for guest support of AMD's CPUID faulting feature. To avoid confusion, remove the helper. Suggested-by: Sean Christopherson Signed-off-by: Jim Mattson Reviewed-by: Binbin Wu --- arch/x86/kvm/cpuid.h | 5 ----- arch/x86/kvm/x86.c | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index bc4a8428b836..95d09ccbf951 100644 --- a/arch/x86/kvm/cpuid.h +++ b/arch/x86/kvm/cpuid.h @@ -183,11 +183,6 @@ static inline int guest_cpuid_stepping(struct kvm_vcpu= *vcpu) return x86_stepping(best->eax); } =20 -static inline bool supports_cpuid_fault(struct kvm_vcpu *vcpu) -{ - return vcpu->arch.msr_platform_info & MSR_PLATFORM_INFO_CPUID_FAULT; -} - static inline bool cpuid_fault_enabled(struct kvm_vcpu *vcpu) { return vcpu->arch.msr_misc_features_enables & diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 72bd3cddb026..d5a2d794c3c9 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4264,7 +4264,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) case MSR_MISC_FEATURES_ENABLES: if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && - !supports_cpuid_fault(vcpu))) + !(vcpu->arch.msr_platform_info & MSR_PLATFORM_INFO_CPUID_FAULT))) return 1; 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charset="utf-8" On AMD CPUs, CPUID faulting support is advertised via CPUID.80000021H:EAX.CpuidUserDis[bit 17] and enabled by setting HWCR.CpuidUserDis[bit 35]. Advertise the feature to userspace regardless of host CPU support. Allow writes to HWCR to set bit 35 when the guest CPUID advertises CpuidUserDis. Update cpuid_fault_enabled() to check HWCR.CpuidUserDis as well as MSR_FEATURE_ENABLES.CPUID_GP_ON_CPL_GT_0. Unlike VMX, SVM prioritizes the CPUID intercept over the #GP induced by CPUID faulting.[1] This behavior has been confirmed on a Turin CPU (F/M/S 1AH/2/1). Link: https://lore.kernel.org/r/DS7PR12MB82011943131DF5415365E19E940B2@DS7P= R12MB8201.namprd12.prod.outlook.com [1] Signed-off-by: Jim Mattson --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/cpuid.h | 5 +++-- arch/x86/kvm/x86.c | 18 ++++++++++++------ 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index a14a0f43e04a..f534f150d1c5 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -898,6 +898,7 @@ #define MSR_K7_HWCR_IRPERF_EN_BIT 30 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_HWCR_CPUID_USER_DIS_BIT 35 +#define MSR_K7_HWCR_CPUID_USER_DIS BIT_ULL(MSR_K7_HWCR_CPUID_USER_DIS_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 #define MSR_K7_HWCR_CPB_DIS_BIT 25 diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 1c95d1fa3ead..8e5340dd2621 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1248,7 +1248,7 @@ void kvm_initialize_cpu_caps(void) F(AUTOIBRS), EMULATED_F(NO_SMM_CTL_MSR), /* PrefetchCtlMsr */ - /* GpOnUserCpuid */ + EMULATED_F(GP_ON_USER_CPUID), /* EPSF */ F(PREFETCHI), F(AVX512_BMM), diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index 95d09ccbf951..fc96ba86c644 100644 --- a/arch/x86/kvm/cpuid.h +++ b/arch/x86/kvm/cpuid.h @@ -185,8 +185,9 @@ static inline int guest_cpuid_stepping(struct kvm_vcpu = *vcpu) =20 static inline bool cpuid_fault_enabled(struct kvm_vcpu *vcpu) { - return vcpu->arch.msr_misc_features_enables & - MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; + return (vcpu->arch.msr_misc_features_enables & + MSR_MISC_FEATURES_ENABLES_CPUID_FAULT) || + (vcpu->arch.msr_hwcr & MSR_K7_HWCR_CPUID_USER_DIS); } =20 static inline bool kvm_is_cpuid_allowed(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index d5a2d794c3c9..54c552efb59e 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4002,22 +4002,28 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) break; case MSR_EFER: return set_efer(vcpu, msr_info); - case MSR_K7_HWCR: - data &=3D ~(u64)0x40; /* ignore flush filter disable */ - data &=3D ~(u64)0x100; /* ignore ignne emulation enable */ - data &=3D ~(u64)0x8; /* ignore TLB cache disable */ - + case MSR_K7_HWCR: { /* * Allow McStatusWrEn and TscFreqSel. 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Wed, 27 May 2026 10:44:06 -0700 (PDT) Date: Wed, 27 May 2026 10:43:47 -0700 In-Reply-To: <20260527174347.2356165-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260527174347.2356165-1-jmattson@google.com> X-Mailer: git-send-email 2.54.0.794.g4f17f83d09-goog Message-ID: <20260527174347.2356165-6-jmattson@google.com> Subject: [PATCH v4 5/5] KVM: selftests: Update hwcr_msr_test for CPUID faulting bit From: Jim Mattson To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, ctpence@google.com, David.Kaplan@amd.com, binbin.wu@linux.intel.com Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add BIT_ULL(35) (CpuidUserDis) to the valid mask in hwcr_msr_test, now that KVM accepts writes to this bit when the guest CPUID advertises CpuidUserDis. Signed-off-by: Jim Mattson --- tools/testing/selftests/kvm/include/x86/processor.h | 1 + tools/testing/selftests/kvm/x86/hwcr_msr_test.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 06878e7c7347..513e4a1075fa 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -226,6 +226,7 @@ struct kvm_x86_cpu_feature { #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) #define X86_FEATURE_SEV_SNP KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 4) +#define X86_FEATURE_GP_ON_USER_CPUID KVM_X86_CPU_FEATURE(0x80000021, 0, EA= X, 17) #define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) #define X86_FEATURE_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX,= 2) =20 diff --git a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c b/tools/testin= g/selftests/kvm/x86/hwcr_msr_test.c index 8e20a03b3329..53b7971aa072 100644 --- a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c +++ b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c @@ -11,12 +11,17 @@ void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit) { const u64 ignored =3D BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8); - const u64 valid =3D BIT_ULL(18) | BIT_ULL(24); - const u64 legal =3D ignored | valid; + u64 valid =3D BIT_ULL(18) | BIT_ULL(24); u64 val =3D BIT_ULL(bit); u64 actual; + u64 legal; int r; =20 + if (kvm_cpu_has(X86_FEATURE_GP_ON_USER_CPUID)) + valid |=3D BIT_ULL(35); + + legal =3D ignored | valid; + r =3D _vcpu_set_msr(vcpu, MSR_K7_HWCR, val); TEST_ASSERT(val & ~legal ? !r : r =3D=3D 1, "Expected KVM_SET_MSRS(MSR_K7_HWCR) =3D 0x%lx to %s", --=20 2.54.0.794.g4f17f83d09-goog