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Wed, 27 May 2026 08:41:26 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Wed, 27 May 2026 08:41:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Wed, 27 May 2026 08:41:25 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id AF6933F7068; Wed, 27 May 2026 08:41:22 -0700 (PDT) From: Geetha sowjanya To: , , , CC: , , Subject: [PATCH v7 1/2] dt-bindings: perf: marvell: Add CN20K DDR PMU binding Date: Wed, 27 May 2026 21:11:17 +0530 Message-ID: <20260527154118.12884-2-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260527154118.12884-1-gakula@marvell.com> References: <20260527154118.12884-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: FhN5udkyJK38i6kh7tk-dKGWiK1kg3kZ X-Authority-Analysis: v=2.4 cv=ScjHsPRu c=1 sm=1 tr=0 ts=6a1710a6 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=gEfo2CItAAAA:8 a=M5GUcnROAAAA:8 a=cPq5-T7l7yds4WLDPVIA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: FhN5udkyJK38i6kh7tk-dKGWiK1kg3kZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI3MDE1NyBTYWx0ZWRfXwec3TSnidsLJ RknTZ+LNq2b8sxC0NT8i2Y2dGIefKfoM4OqQ1gUeLvkUjyZrscMt5TMYFUIl48hPFZjUhWAECuG r/3XofHhsPg/bFUnkZdscEi02pDl4iLa1xLZFDetYiYVImnu7zhiqMoztcW4KD/7Zxu8LH6r8it aIOL4Wr+rdL4DFWrFIXKNXpMYeR2kY/U16TDXtDFpQIo2whdgroK/Ype8lmspeoRMJHpjjtVfXG ArSlXz/dVWd5SckGOlbuVe1vS5wzVc/afVBnFOm2H2RkzUppU3sXR6J/+0aVSkgTlLK55lYLi6/ 4qTmeJKZeFKUDT/8/P81iWPR0JVsl0jPufadSjbWdEYgj+uV5bJ1NamoOcZgJy85HJEJdiqyyd2 rzsnW850dHFya/CULaSH0/UKac51Bz1J6NWj9/SMovKsiT+mN8Qx9DqcvaVp6cEoo1ta/oiHJES tjf8m644B3SowUJdE9g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-27_02,2026-05-26_03,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU) associated with the DDR controller. The block provides hardware counters to monitor DDR traffic and performance events and is accessed via a dedicated MMIO region. The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU, with minor register offset differences. Signed-off-by: Geetha sowjanya Reviewed-by: Krzysztof Kozlowski --- Changes in v7: - Dropped the CN20K DeviceTree example. Changes in v6: - dt-bindings: Document CN20K in the existing marvell-cn10k-ddr.yaml; add maintainer, description, compatible enum entry, and a CN20K example with unit-address aligned to reg. .../devicetree/bindings/perf/marvell-cn10k-ddr.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml = b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml index a18dd0a8c43a..f2f0d6b61eac 100644 --- a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml @@ -4,16 +4,22 @@ $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Marvell CN10K DDR performance monitor +title: Marvell CN10K / CN20K DDR performance monitor + +description: + Performance Monitoring Unit (PMU) for the DDR controller on Marvell + CN10K and CN20K SoCs. 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charset="utf-8" The CN20K DRAM Subsystem exposes eight programmable performance counters and two fixed counters for DDR read and write traffic. Software selects events for the programmable counters from traffic at the DDR PHY interface, the CHI interconnect, or inside the DDR controller. Add CN20K register offsets, event maps, and sysfs attributes; match the device via OF (marvell,cn20k-ddr-pmu) and ACPI (MRVL000B). Represent the SoC variant in platform data with bit flags so CN20K can reuse the CN10K PMU code path where appropriate. Signed-off-by: Geetha sowjanya --- Changes in v7: - perf: Add ZQ case (62/63) before the DFI switch range; handle shared IDs 58-61 only inside the DFI branch (fixes overlapping cases and Odyssey EINVAL for perf-width events). - perf: Widen programmable-event case to EVENT_OP_IS_CAS_WS through EVENT_OP_IS_ZQLATCH so CAS sysfs events (36-38) map in ddr_perf_get_event_bitmap. - perf: On event_add failure from ddr_perf_get_event_bitmap, cancel timer if needed and free the counter slot instead of returning with partial setup. - perf: For CN20K, zero CFG0 before writing ZQ to CFG1 and zero CFG1 before non-ZQ CFG0 so stale masks do not combine across banks. drivers/perf/marvell_cn10k_ddr_pmu.c | 230 +++++++++++++++++++++++++-- 1 file changed, 214 insertions(+), 16 deletions(-) diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn= 10k_ddr_pmu.c index 72ac17efd846..6f638dfe829b 100644 --- a/drivers/perf/marvell_cn10k_ddr_pmu.c +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c @@ -13,31 +13,43 @@ #include #include #include +#include + +/* SoC variant flags for struct ddr_pmu_platform_data (mutually exclusive = in pdata) */ +#define IS_CN10K BIT(0) +#define IS_ODY BIT(1) +#define IS_CN20K BIT(2) =20 /* Performance Counters Operating Mode Control Registers */ #define CN10K_DDRC_PERF_CNT_OP_MODE_CTRL 0x8020 #define ODY_DDRC_PERF_CNT_OP_MODE_CTRL 0x20020 +#define CN20K_DDRC_PERF_CNT_OP_MODE_CTRL 0x20000 #define OP_MODE_CTRL_VAL_MANUAL 0x1 =20 /* Performance Counters Start Operation Control Registers */ #define CN10K_DDRC_PERF_CNT_START_OP_CTRL 0x8028 #define ODY_DDRC_PERF_CNT_START_OP_CTRL 0x200A0 +#define CN20K_DDRC_PERF_CNT_START_OP_CTRL 0x20080 #define START_OP_CTRL_VAL_START 0x1ULL #define START_OP_CTRL_VAL_ACTIVE 0x2 =20 /* Performance Counters End Operation Control Registers */ #define CN10K_DDRC_PERF_CNT_END_OP_CTRL 0x8030 #define ODY_DDRC_PERF_CNT_END_OP_CTRL 0x200E0 +#define CN20K_DDRC_PERF_CNT_END_OP_CTRL 0x200C0 #define END_OP_CTRL_VAL_END 0x1ULL =20 /* Performance Counters End Status Registers */ #define CN10K_DDRC_PERF_CNT_END_STATUS 0x8038 #define ODY_DDRC_PERF_CNT_END_STATUS 0x20120 +#define CN20K_DDRC_PERF_CNT_END_STATUS 0x20100 #define END_STATUS_VAL_END_TIMER_MODE_END 0x1 =20 /* Performance Counters Configuration Registers */ #define CN10K_DDRC_PERF_CFG_BASE 0x8040 #define ODY_DDRC_PERF_CFG_BASE 0x20160 +#define CN20K_DDRC_PERF_CFG_BASE 0x20140 +#define CN20K_DDRC_PERF_CFG1_BASE 0x20180 =20 /* 8 Generic event counter + 2 fixed event counters */ #define DDRC_PERF_NUM_GEN_COUNTERS 8 @@ -61,6 +73,24 @@ * DO NOT change these event-id numbers, they are used to * program event bitmap in h/w. */ + +/* CN20K specific events */ +#define EVENT_PERF_OP_IS_RD16 61 +#define EVENT_PERF_OP_IS_RD32 60 +#define EVENT_PERF_OP_IS_WR16 59 +#define EVENT_PERF_OP_IS_WR32 58 +#define EVENT_OP_IS_ENTER_DSM 44 +#define EVENT_OP_IS_RFM 43 + + +#define EVENT_CN20K_OP_IS_ZQLATCH 62 +#define EVENT_CN20K_OP_IS_ZQSTART 63 +#define EVENT_CN20K_OP_IS_TCR_MRR 50 +#define EVENT_CN20K_OP_IS_DQSOSC_MRR 49 +#define EVENT_CN20K_OP_IS_DQSOSC_MPC 48 +#define EVENT_CN20K_VISIBLE_WIN_LIMIT_REACHED_WR 47 +#define EVENT_CN20K_VISIBLE_WIN_LIMIT_REACHED_RD 46 + #define EVENT_DFI_CMD_IS_RETRY 61 #define EVENT_RD_UC_ECC_ERROR 60 #define EVENT_RD_CRC_ERROR 59 @@ -87,6 +117,9 @@ #define EVENT_OP_IS_SPEC_REF 41 #define EVENT_OP_IS_CRIT_REF 40 #define EVENT_OP_IS_REFRESH 39 +#define EVENT_OP_IS_CAS_WCK_SUS 38 +#define EVENT_OP_IS_CAS_WS_OFF 37 +#define EVENT_OP_IS_CAS_WS 36 #define EVENT_OP_IS_ENTER_MPSM 35 #define EVENT_OP_IS_ENTER_POWERDOWN 31 #define EVENT_OP_IS_ENTER_SELFREF 27 @@ -183,8 +216,8 @@ struct ddr_pmu_platform_data { u64 cnt_freerun_clr; u64 cnt_value_wr_op; u64 cnt_value_rd_op; - bool is_cn10k; - bool is_ody; + u64 cfg1_base; + unsigned int silicon_flags; /* IS_CN10K, IS_ODY, or IS_CN20K */ }; =20 static ssize_t cn10k_ddr_pmu_event_show(struct device *dev, @@ -336,6 +369,80 @@ static struct attribute *odyssey_ddr_perf_events_attrs= [] =3D { NULL }; =20 +static struct attribute *cn20k_ddr_perf_events_attrs[] =3D { + /* Programmable */ + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_or_wr_access, EVENT_HIF_RD_OR_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_wr_access, EVENT_HIF_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_access, EVENT_HIF_RD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rmw_access, EVENT_HIF_RMW), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_pri_rdaccess, EVENT_HIF_HI_PRI_RD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_bypass_access, EVENT_READ_BYPASS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_act_bypass_access, EVENT_ACT_BYPASS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_wr_data_access, + EVENT_DFI_WR_DATA_CYCLES), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_rd_data_access, + EVENT_DFI_RD_DATA_CYCLES), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hpri_sched_rd_crit_access, + EVENT_HPR_XACT_WHEN_CRITICAL), + CN10K_DDR_PMU_EVENT_ATTR(ddr_lpri_sched_rd_crit_access, + EVENT_LPR_XACT_WHEN_CRITICAL), + CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_trxn_crit_access, + EVENT_WR_XACT_WHEN_CRITICAL), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_active_access, EVENT_OP_IS_ACTIVATE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_or_wr_access, + EVENT_OP_IS_RD_OR_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_active_access, + EVENT_OP_IS_RD_ACTIVATE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_read, EVENT_OP_IS_RD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_write, EVENT_OP_IS_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_mwr, EVENT_OP_IS_MWR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge, EVENT_OP_IS_PRECHARGE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_rdwr, + EVENT_PRECHARGE_FOR_RDWR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_other, + EVENT_PRECHARGE_FOR_OTHER), + CN10K_DDR_PMU_EVENT_ATTR(ddr_rdwr_transitions, EVENT_RDWR_TRANSITIONS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_write_combine, EVENT_WRITE_COMBINE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_war_hazard, EVENT_WAR_HAZARD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_raw_hazard, EVENT_RAW_HAZARD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_waw_hazard, EVENT_WAW_HAZARD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_selfref, EVENT_OP_IS_ENTER_SELFREF), + CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_powerdown, + EVENT_OP_IS_ENTER_POWERDOWN), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cas_ws, EVENT_OP_IS_CAS_WS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cas_ws_off, EVENT_OP_IS_CAS_WS_OFF), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cas_wck_sus, EVENT_OP_IS_CAS_WCK_SUS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_refresh, EVENT_OP_IS_REFRESH), + CN10K_DDR_PMU_EVENT_ATTR(ddr_crit_ref, EVENT_OP_IS_CRIT_REF), + CN10K_DDR_PMU_EVENT_ATTR(ddr_spec_ref, EVENT_OP_IS_SPEC_REF), + CN10K_DDR_PMU_EVENT_ATTR(ddr_load_mode, EVENT_OP_IS_LOAD_MODE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_rfm, EVENT_OP_IS_RFM), + CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_dsm, EVENT_OP_IS_ENTER_DSM), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_cycles, EVENT_DFI_CYCLES), + CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_rd, + EVENT_CN20K_VISIBLE_WIN_LIMIT_REACHED_RD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_wr, + EVENT_CN20K_VISIBLE_WIN_LIMIT_REACHED_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mpc, EVENT_CN20K_OP_IS_DQSOSC_MPC), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mrr, EVENT_CN20K_OP_IS_DQSOSC_MRR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_tcr_mrr, EVENT_CN20K_OP_IS_TCR_MRR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_zqstart, EVENT_CN20K_OP_IS_ZQSTART), + CN10K_DDR_PMU_EVENT_ATTR(ddr_zqlatch, EVENT_CN20K_OP_IS_ZQLATCH), + CN10K_DDR_PMU_EVENT_ATTR(ddr_read16, EVENT_PERF_OP_IS_RD16), + CN10K_DDR_PMU_EVENT_ATTR(ddr_read32, EVENT_PERF_OP_IS_RD32), + CN10K_DDR_PMU_EVENT_ATTR(ddr_write16, EVENT_PERF_OP_IS_WR16), + CN10K_DDR_PMU_EVENT_ATTR(ddr_write32, EVENT_PERF_OP_IS_WR32), + /* Free run event counters */ + CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_reads, EVENT_DDR_READS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_writes, EVENT_DDR_WRITES), + NULL +}; + +static struct attribute_group cn20k_ddr_perf_events_attr_group =3D { + .name =3D "events", + .attrs =3D cn20k_ddr_perf_events_attrs, +}; + static struct attribute_group odyssey_ddr_perf_events_attr_group =3D { .name =3D "events", .attrs =3D odyssey_ddr_perf_events_attrs, @@ -393,6 +500,13 @@ static const struct attribute_group *odyssey_attr_grou= ps[] =3D { NULL }; =20 +static const struct attribute_group *cn20k_attr_groups[] =3D { + &cn20k_ddr_perf_events_attr_group, + &cn10k_ddr_perf_format_attr_group, + &cn10k_ddr_perf_cpumask_attr_group, + NULL +}; + /* Default poll timeout is 100 sec, which is very sufficient for * 48 bit counter incremented max at 5.6 GT/s, which may take many * hours to overflow. @@ -411,14 +525,38 @@ static int ddr_perf_get_event_bitmap(int eventid, u64= *event_bitmap, int err =3D 0; =20 switch (eventid) { + case EVENT_CN20K_OP_IS_ZQLATCH ... EVENT_CN20K_OP_IS_ZQSTART: + if (ddr_pmu->p_data->silicon_flags & IS_CN20K) { + *event_bitmap =3D (1ULL << (eventid - 42)); + break; + } + err =3D -EINVAL; + break; case EVENT_DFI_PARITY_POISON ...EVENT_DFI_CMD_IS_RETRY: - if (!ddr_pmu->p_data->is_ody) { + /* + * 58..61: CN20K perf width events share numeric IDs with Odyssey + * DFI events; same 1ULL << (eventid - 1) bitmap on both paths. + */ + if (eventid >=3D EVENT_PERF_OP_IS_WR32 && + eventid <=3D EVENT_PERF_OP_IS_RD16) { + if (ddr_pmu->p_data->silicon_flags & IS_CN20K) { + *event_bitmap =3D (1ULL << (eventid - 1)); + break; + } + if (!(ddr_pmu->p_data->silicon_flags & IS_ODY)) { + err =3D -EINVAL; + break; + } + *event_bitmap =3D (1ULL << (eventid - 1)); + break; + } + if (!(ddr_pmu->p_data->silicon_flags & IS_ODY)) { err =3D -EINVAL; break; } fallthrough; case EVENT_HIF_RD_OR_WR ... EVENT_WAW_HAZARD: - case EVENT_OP_IS_REFRESH ... EVENT_OP_IS_ZQLATCH: + case EVENT_OP_IS_CAS_WS ... EVENT_OP_IS_ZQLATCH: *event_bitmap =3D (1ULL << (eventid - 1)); break; case EVENT_OP_IS_ENTER_SELFREF: @@ -524,9 +662,9 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_= ddr_pmu *pmu, int counter, bool enable) { const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + unsigned int silicon_flags =3D pmu->p_data->silicon_flags; u64 ctrl_reg =3D pmu->p_data->cnt_op_mode_ctrl; const struct ddr_pmu_ops *ops =3D pmu->ops; - bool is_ody =3D pmu->p_data->is_ody; u32 reg; u64 val; =20 @@ -546,7 +684,7 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_= ddr_pmu *pmu, =20 writeq_relaxed(val, pmu->base + reg); =20 - if (is_ody) { + if ((silicon_flags & IS_ODY) || (silicon_flags & IS_CN20K)) { if (enable) { /* * Setup the PMU counter to work in @@ -621,6 +759,7 @@ static int cn10k_ddr_perf_event_add(struct perf_event *= event, int flags) { struct cn10k_ddr_pmu *pmu =3D to_cn10k_ddr_pmu(event->pmu); const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + unsigned int silicon_flags =3D pmu->p_data->silicon_flags; const struct ddr_pmu_ops *ops =3D pmu->ops; struct hw_perf_event *hwc =3D &event->hw; u8 config =3D event->attr.config; @@ -642,10 +781,27 @@ static int cn10k_ddr_perf_event_add(struct perf_event= *event, int flags) if (counter < DDRC_PERF_NUM_GEN_COUNTERS) { /* Generic counters, configure event id */ reg_offset =3D DDRC_PERF_CFG(p_data->cfg_base, counter); + ret =3D ddr_perf_get_event_bitmap(config, &val, pmu); if (ret) - return ret; - + goto err_free_counter; + + if (silicon_flags & IS_CN20K) { + if (config =3D=3D EVENT_CN20K_OP_IS_ZQSTART || + config =3D=3D EVENT_CN20K_OP_IS_ZQLATCH) { + /* ZQ lives in CFG1; clear stale event mask in CFG0 */ + writeq_relaxed(0, pmu->base + + DDRC_PERF_CFG(p_data->cfg_base, + counter)); + reg_offset =3D DDRC_PERF_CFG(p_data->cfg1_base, + counter); + } else { + /* Clear CFG1 so a prior ZQ select cannot linger */ + writeq_relaxed(0, pmu->base + + DDRC_PERF_CFG(p_data->cfg1_base, + counter)); + } + } writeq_relaxed(val, pmu->base + reg_offset); } else { /* fixed event counter, clear counter value */ @@ -661,6 +817,14 @@ static int cn10k_ddr_perf_event_add(struct perf_event = *event, int flags) cn10k_ddr_perf_event_start(event, flags); =20 return 0; + +err_free_counter: + if (pmu->active_events =3D=3D 1) + hrtimer_cancel(&pmu->hrtimer); + pmu->active_events--; + cn10k_ddr_perf_free_counter(pmu, counter); + hwc->idx =3D -1; + return ret; } =20 static void cn10k_ddr_perf_event_stop(struct perf_event *event, int flags) @@ -952,7 +1116,25 @@ static const struct ddr_pmu_platform_data cn10k_ddr_p= mu_pdata =3D { .cnt_freerun_clr =3D 0, .cnt_value_wr_op =3D CN10K_DDRC_PERF_CNT_VALUE_WR_OP, .cnt_value_rd_op =3D CN10K_DDRC_PERF_CNT_VALUE_RD_OP, - .is_cn10k =3D TRUE, + .silicon_flags =3D IS_CN10K, +}; + +static const struct ddr_pmu_platform_data cn20k_ddr_pmu_pdata =3D { + .counter_overflow_val =3D 0, + .counter_max_val =3D GENMASK_ULL(63, 0), + .cnt_base =3D ODY_DDRC_PERF_CNT_VALUE_BASE, + .cfg_base =3D CN20K_DDRC_PERF_CFG_BASE, + .cfg1_base =3D CN20K_DDRC_PERF_CFG1_BASE, + .cnt_op_mode_ctrl =3D CN20K_DDRC_PERF_CNT_OP_MODE_CTRL, + .cnt_start_op_ctrl =3D CN20K_DDRC_PERF_CNT_START_OP_CTRL, + .cnt_end_op_ctrl =3D CN20K_DDRC_PERF_CNT_END_OP_CTRL, + .cnt_end_status =3D CN20K_DDRC_PERF_CNT_END_STATUS, + .cnt_freerun_en =3D 0, + .cnt_freerun_ctrl =3D ODY_DDRC_PERF_CNT_FREERUN_CTRL, + .cnt_freerun_clr =3D ODY_DDRC_PERF_CNT_FREERUN_CLR, + .cnt_value_wr_op =3D ODY_DDRC_PERF_CNT_VALUE_WR_OP, + .cnt_value_rd_op =3D ODY_DDRC_PERF_CNT_VALUE_RD_OP, + .silicon_flags =3D IS_CN20K, }; #endif =20 @@ -979,7 +1161,7 @@ static const struct ddr_pmu_platform_data odyssey_ddr_= pmu_pdata =3D { .cnt_freerun_clr =3D ODY_DDRC_PERF_CNT_FREERUN_CLR, .cnt_value_wr_op =3D ODY_DDRC_PERF_CNT_VALUE_WR_OP, .cnt_value_rd_op =3D ODY_DDRC_PERF_CNT_VALUE_RD_OP, - .is_ody =3D TRUE, + .silicon_flags =3D IS_ODY, }; #endif =20 @@ -989,8 +1171,7 @@ static int cn10k_ddr_perf_probe(struct platform_device= *pdev) struct cn10k_ddr_pmu *ddr_pmu; struct resource *res; void __iomem *base; - bool is_cn10k; - bool is_ody; + unsigned int silicon_flags; char *name; int ret; =20 @@ -1014,10 +1195,9 @@ static int cn10k_ddr_perf_probe(struct platform_devi= ce *pdev) ddr_pmu->base =3D base; =20 ddr_pmu->p_data =3D dev_data; - is_cn10k =3D ddr_pmu->p_data->is_cn10k; - is_ody =3D ddr_pmu->p_data->is_ody; + silicon_flags =3D ddr_pmu->p_data->silicon_flags; =20 - if (is_cn10k) { + if (silicon_flags & IS_CN10K) { ddr_pmu->ops =3D &ddr_pmu_ops; /* Setup the PMU counter to work in manual mode */ writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base + @@ -1039,7 +1219,7 @@ static int cn10k_ddr_perf_probe(struct platform_devic= e *pdev) }; } =20 - if (is_ody) { + if (silicon_flags & IS_ODY) { ddr_pmu->ops =3D &ddr_pmu_ody_ops; =20 ddr_pmu->pmu =3D (struct pmu) { @@ -1056,6 +1236,22 @@ static int cn10k_ddr_perf_probe(struct platform_devi= ce *pdev) }; } =20 + if (silicon_flags & IS_CN20K) { + ddr_pmu->ops =3D &ddr_pmu_ody_ops; + + ddr_pmu->pmu =3D (struct pmu) { + .module =3D THIS_MODULE, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + .task_ctx_nr =3D perf_invalid_context, + .attr_groups =3D cn20k_attr_groups, + .event_init =3D cn10k_ddr_perf_event_init, + .add =3D cn10k_ddr_perf_event_add, + .del =3D cn10k_ddr_perf_event_del, + .start =3D cn10k_ddr_perf_event_start, + .stop =3D cn10k_ddr_perf_event_stop, + .read =3D cn10k_ddr_perf_event_update, + }; + } /* Choose this cpu to collect perf data */ ddr_pmu->cpu =3D raw_smp_processor_id(); =20 @@ -1098,6 +1294,7 @@ static void cn10k_ddr_perf_remove(struct platform_dev= ice *pdev) #ifdef CONFIG_OF static const struct of_device_id cn10k_ddr_pmu_of_match[] =3D { { .compatible =3D "marvell,cn10k-ddr-pmu", .data =3D &cn10k_ddr_pmu_pdata= }, + { .compatible =3D "marvell,cn20k-ddr-pmu", .data =3D &cn20k_ddr_pmu_pdata= }, { }, }; MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match); @@ -1107,6 +1304,7 @@ MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match); static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] =3D { {"MRVL000A", (kernel_ulong_t)&cn10k_ddr_pmu_pdata }, {"MRVL000C", (kernel_ulong_t)&odyssey_ddr_pmu_pdata}, + {"MRVL000B", (kernel_ulong_t)&cn20k_ddr_pmu_pdata}, {}, }; MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match); --=20 2.25.1