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Wed, 27 May 2026 05:55:05 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 01/13] net/mlx5: LAG, factor out shared FDB code into dedicated file Date: Wed, 27 May 2026 15:54:15 +0300 Message-ID: <20260527125427.385976-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E66:EE_|SA3PR12MB7860:EE_ X-MS-Office365-Filtering-Correlation-Id: dbf998f6-6bf7-4df8-9a37-08debbef3c0b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700016|82310400026|18002099003|22082099003|11063799006|6133799003|56012099006; X-Microsoft-Antispam-Message-Info: 2Bu/uXy16yvGmBITw1I6Rz9yVv05bo8whtu5RSOW+6DKBm5TYkSo0uwcThQ/jJdemxxvYqzZi/rOpCGeEvvwLQ8r+CbjzztB/0SDDoFgmWoouL0k5nHcffT60V0eE0DRLT63qs/zlC0wKKo+BR23czm0V510tfSxa6elmErHXYtuQaY0X8YyKcV2tpvnPpB44bNHPrDf5h/scY0pI/A+knLpTg9GNX4krxCKlwdZEZMY/7cTueJzzBe21MV/qG1EmqSIOWfnmnwPgQ7ThCW1KEwuhxiFyxpoNBR599WG5syOhaeK+mBW05PdAT77kG5p+xj4kp6P1E7mhBa6bIU6+/Bsheoe1rIEehoQXydA6kb/C96teNoBO8KuSzt5QPNWbWignVXZaeDcPmaGPATyhVPOXTK7y0pxQFX/9ExjS4S8C3h2/68a1xezmhDN8UAn9j2mo+XhAS0eS1ntG29CQ55tkgYVrMAdYyRNefXvTcnYNkwyDPu0BHyW+bHj+VbN6k6btOI8QBm3lcbKmyCvGFeC8ZyjJnqxatmGmxKN+6Hsj9LuuX00xyJe4PtA2bsFtTfnl/p61bZPZe8o4SjqRXnEZO1DpaNww7gs/6gPFgCsmhRK4IL1wN5yyP24lqPYfwCJVodKUMStu807nQS3TGpqJ7yqiW2uFmSWXIxPRd2SLkSEOsPZdUl+TBnk4sFcZuXUKrzQNXapgrlq3s+61CXWoOwzDJl8qho+2U6BL7s= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700016)(82310400026)(18002099003)(22082099003)(11063799006)(6133799003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: n06U1SL58Lm3M2cMejOr8va2Gi1vQAhTNtDi7BpmaMwo4Sh9pXcXJakiI/kzenxrizMugq9NIeyAWS6RMbDJ1LJk50V8Usnrhq1ihUH8S6pA818styqeJVwv97D4g+BO9/EA9k7fDh7kzB5bmfooj85nDl7gI4xd/RH/2l9HuTjnmelKy3ujcxU4o/sAB86o+BA4MG6611IHgpfU/PER5IHFWv03bd0dDCgY7lU1n3jgp57iw0f0WYl7KJdjHEbK28toEJ85siai6lMnRMgaMvJtolOje716Ad8AOuENC0N22BtSjNTAaxo7kmrX2PM3TT9pcPtJg+jCgCU3PldJSaZbIgCuoc4xucVRIy2bJjagQoTRygkb6RlkqQRtN8JcI6hJQZF5ByrT6ZuO/71xOBZ1zf2kzZkt+DTjuWUXGJcO/JPXedMgkxuDhyW8ziwC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:55:31.1240 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbf998f6-6bf7-4df8-9a37-08debbef3c0b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E66.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7860 Content-Type: text/plain; charset="utf-8" From: Shay Drory Refactor shared FDB LAG logic into a new lag/shared_fdb.c file to improve code organization and enable reuse. Move shared FDB specific functions from lag.c and introduce consolidated APIs: - mlx5_lag_shared_fdb_create() handles LAG activation with shared FDB - mlx5_lag_shared_fdb_destroy() handles LAG deactivation with shared FDB Update mlx5_do_bond(), mlx5_disable_lag() and mpesw.c to use the new APIs, which simplifies the shared FDB code paths. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/Makefile | 2 +- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 156 ++++-------------- .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 26 +++ .../ethernet/mellanox/mlx5/core/lag/mpesw.c | 25 +-- .../mellanox/mlx5/core/lag/shared_fdb.c | 143 ++++++++++++++++ 5 files changed, 210 insertions(+), 142 deletions(-) create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c diff --git a/drivers/net/ethernet/mellanox/mlx5/core/Makefile b/drivers/net= /ethernet/mellanox/mlx5/core/Makefile index d39fe9c4a87c..19e50f0d55af 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/Makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/Makefile @@ -41,7 +41,7 @@ mlx5_core-$(CONFIG_MLX5_CORE_EN_DCB) +=3D en_dcbnl.o en/p= ort_buffer.o mlx5_core-$(CONFIG_PCI_HYPERV_INTERFACE) +=3D en/hv_vhca_stats.o mlx5_core-$(CONFIG_MLX5_ESWITCH) +=3D lag/mp.o lag/port_sel.o lib/gene= ve.o lib/port_tun.o \ en_rep.o en/rep/bond.o en/mod_hdr.o \ - en/mapping.o lag/mpesw.o + en/mapping.o lag/mpesw.o lag/shared_fdb.o mlx5_core-$(CONFIG_MLX5_CLS_ACT) +=3D en_tc.o en/rep/tc.o en/rep/neigh= .o \ lib/fs_chains.o en/tc_tun.o \ esw/indir_table.o en/tc_tun_encap.o \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 22b7efea34b8..5dfdd799828f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -817,43 +817,6 @@ char *mlx5_get_str_port_sel_mode(enum mlx5_lag_mode mo= de, unsigned long flags) } } =20 -static int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) -{ - int master_idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); - struct mlx5_eswitch *master_esw; - struct mlx5_core_dev *dev0; - int i, j; - int err; - - if (master_idx < 0) - return -EINVAL; - - dev0 =3D mlx5_lag_pf(ldev, master_idx)->dev; - master_esw =3D dev0->priv.eswitch; - mlx5_ldev_for_each(i, 0, ldev) { - struct mlx5_eswitch *slave_esw; - - if (i =3D=3D master_idx) - continue; - - slave_esw =3D mlx5_lag_pf(ldev, i)->dev->priv.eswitch; - - err =3D mlx5_eswitch_offloads_single_fdb_add_one(master_esw, - slave_esw, ldev->ports); - if (err) - goto err; - } - return 0; -err: - mlx5_ldev_for_each_reverse(j, i, 0, ldev) { - if (j =3D=3D master_idx) - continue; - mlx5_eswitch_offloads_single_fdb_del_one(master_esw, - mlx5_lag_pf(ldev, j)->dev->priv.eswitch); - } - return err; -} - static int mlx5_create_lag(struct mlx5_lag *ldev, struct lag_tracker *tracker, enum mlx5_lag_mode mode, @@ -1218,12 +1181,15 @@ void mlx5_disable_lag(struct mlx5_lag *ldev) if (idx < 0) return; =20 + if (shared_fdb) { + mlx5_lag_shared_fdb_destroy(ldev); + return; + } + dev0 =3D mlx5_lag_pf(ldev, idx)->dev; roce_lag =3D __mlx5_lag_is_roce(ldev); =20 - if (shared_fdb) { - mlx5_lag_remove_devices(ldev); - } else if (roce_lag) { + if (roce_lag) { mlx5_lag_rescan_dev_locked(ldev, dev0, false); mlx5_ldev_for_each(i, 0, ldev) { if (i =3D=3D idx) @@ -1236,49 +1202,8 @@ void mlx5_disable_lag(struct mlx5_lag *ldev) if (err) return; =20 - if (shared_fdb || roce_lag) + if (roce_lag) mlx5_lag_add_devices(ldev); - - if (shared_fdb) - mlx5_lag_reload_ib_reps_from_locked(ldev, - MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV, - true); -} - -bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) -{ - struct mlx5_core_dev *dev; - bool ret =3D false; - int idx; - int i; - - idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); - if (idx < 0) - return false; - - mlx5_ldev_for_each(i, 0, ldev) { - if (i =3D=3D idx) - continue; - dev =3D mlx5_lag_pf(ldev, i)->dev; - if (is_mdev_switchdev_mode(dev) && - mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch) && - MLX5_CAP_GEN(dev, lag_native_fdb_selection) && - MLX5_CAP_ESW(dev, root_ft_on_other_esw) && - mlx5_eswitch_get_npeers(dev->priv.eswitch) =3D=3D - MLX5_CAP_GEN(dev, num_lag_ports) - 1) - continue; - return false; - } - - dev =3D mlx5_lag_pf(ldev, idx)->dev; - if (is_mdev_switchdev_mode(dev) && - mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch) && - mlx5_esw_offloads_devcom_is_ready(dev->priv.eswitch) && - MLX5_CAP_ESW(dev, esw_shared_ingress_acl) && - mlx5_eswitch_get_npeers(dev->priv.eswitch) =3D=3D MLX5_CAP_GEN(dev, n= um_lag_ports) - 1) - ret =3D true; - - return ret; } =20 static bool mlx5_lag_is_roce_lag(struct mlx5_lag *ldev) @@ -1493,47 +1418,37 @@ static void mlx5_do_bond(struct mlx5_lag *ldev) =20 roce_lag =3D mlx5_lag_is_roce_lag(ldev); =20 - if (shared_fdb || roce_lag) - mlx5_lag_remove_devices(ldev); - - err =3D mlx5_activate_lag(ldev, &tracker, - roce_lag ? MLX5_LAG_MODE_ROCE : - MLX5_LAG_MODE_SRIOV, - shared_fdb); - if (err) { - if (shared_fdb || roce_lag) - mlx5_lag_add_devices(ldev); - if (shared_fdb) - mlx5_lag_reload_ib_reps_from_locked(ldev, 0, - true); - - return; - } + if (shared_fdb) { + err =3D mlx5_lag_shared_fdb_create(ldev, &tracker, + MLX5_LAG_MODE_SRIOV); + if (err) + return; + } else { + if (roce_lag) + mlx5_lag_remove_devices(ldev); =20 - if (roce_lag) { - struct mlx5_core_dev *dev; - - mlx5_lag_rescan_dev_locked(ldev, dev0, true); - mlx5_ldev_for_each(i, 0, ldev) { - if (i =3D=3D idx) - continue; - dev =3D mlx5_lag_pf(ldev, i)->dev; - if (mlx5_get_roce_state(dev)) - mlx5_nic_vport_enable_roce(dev); - } - } else if (shared_fdb) { - mlx5_lag_rescan_dev_locked(ldev, dev0, true); - err =3D mlx5_lag_reload_ib_reps_from_locked(ldev, 0, - false); + err =3D mlx5_activate_lag(ldev, &tracker, + roce_lag ? MLX5_LAG_MODE_ROCE : + MLX5_LAG_MODE_SRIOV, + false); if (err) { - mlx5_lag_rescan_dev_locked(ldev, dev0, false); - mlx5_deactivate_lag(ldev); - mlx5_lag_add_devices(ldev); - mlx5_lag_reload_ib_reps_from_locked(ldev, 0, - true); - mlx5_core_err(dev0, "Failed to enable lag\n"); + if (roce_lag) + mlx5_lag_add_devices(ldev); return; } + + if (roce_lag) { + struct mlx5_core_dev *dev; + + mlx5_lag_rescan_dev_locked(ldev, dev0, true); + mlx5_ldev_for_each(i, 0, ldev) { + if (i =3D=3D idx) + continue; + dev =3D mlx5_lag_pf(ldev, i)->dev; + if (mlx5_get_roce_state(dev)) + mlx5_nic_vport_enable_roce(dev); + } + } } if (tracker.tx_type =3D=3D NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) { ndev =3D mlx5_lag_active_backup_get_netdev(dev0); @@ -1545,7 +1460,8 @@ static void mlx5_do_bond(struct mlx5_lag *ldev) ndev); dev_put(ndev); } - mlx5_lag_set_vports_agg_speed(ldev); + if (!shared_fdb) + mlx5_lag_set_vports_agg_speed(ldev); } else if (mlx5_lag_should_modify_lag(ldev, do_bond)) { mlx5_modify_lag(ldev, &tracker); mlx5_lag_set_vports_agg_speed(ldev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index 6afe7707d076..23c0457ce799 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -137,7 +137,33 @@ mlx5_lag_is_ready(struct mlx5_lag *ldev) return test_bit(MLX5_LAG_FLAG_NDEVS_READY, &ldev->state_flags); } =20 +#ifdef CONFIG_MLX5_ESWITCH +int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, + struct lag_tracker *tracker, + enum mlx5_lag_mode mode); +void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev); +int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev); bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev); +#else +static inline int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, + struct lag_tracker *tracker, + enum mlx5_lag_mode mode) +{ + return -EOPNOTSUPP; +} + +static inline void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev) {} + +static inline int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) +{ + return -EOPNOTSUPP; +} + +static inline bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) +{ + return false; +} +#endif bool mlx5_lag_check_prereq(struct mlx5_lag *ldev); int mlx5_lag_demux_init(struct mlx5_core_dev *dev, struct mlx5_flow_table_attr *ft_attr); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/= net/ethernet/mellanox/mlx5/core/lag/mpesw.c index 8a349f8fd823..64e2d1dd5308 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -92,38 +92,21 @@ static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) if (err) return err; =20 - mlx5_lag_remove_devices(ldev); - - err =3D mlx5_activate_lag(ldev, NULL, MLX5_LAG_MODE_MPESW, true); + err =3D mlx5_lag_shared_fdb_create(ldev, NULL, MLX5_LAG_MODE_MPESW); if (err) { mlx5_core_warn(dev0, "Failed to create LAG in MPESW mode (%d)\n", err); - goto err_add_devices; + mlx5_mpesw_metadata_cleanup(ldev); + return err; } =20 - mlx5_lag_rescan_dev_locked(ldev, dev0, true); - err =3D mlx5_lag_reload_ib_reps_from_locked(ldev, 0, false); - if (err) - goto err_rescan_drivers; - - mlx5_lag_set_vports_agg_speed(ldev); - return 0; - -err_rescan_drivers: - mlx5_lag_rescan_dev_locked(ldev, dev0, false); - mlx5_deactivate_lag(ldev); -err_add_devices: - mlx5_lag_add_devices(ldev); - mlx5_lag_reload_ib_reps_from_locked(ldev, 0, true); - mlx5_mpesw_metadata_cleanup(ldev); - return err; } =20 void mlx5_lag_disable_mpesw(struct mlx5_lag *ldev) { if (ldev->mode =3D=3D MLX5_LAG_MODE_MPESW) { mlx5_mpesw_metadata_cleanup(ldev); - mlx5_disable_lag(ldev); + mlx5_lag_shared_fdb_destroy(ldev); } } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/dri= vers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c new file mode 100644 index 000000000000..e5b8e9f1e6fd --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB +/* Copyright (c) 2026, NVIDIA CORPORATION & AFFILIATES. All rights reserve= d. */ + +#include +#include +#include +#include "mlx5_core.h" +#include "lag.h" +#include "eswitch.h" + +bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) +{ + struct mlx5_core_dev *dev; + bool ret =3D false; + int idx; + int i; + + idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); + if (idx < 0) + return false; + + mlx5_ldev_for_each(i, 0, ldev) { + if (i =3D=3D idx) + continue; + dev =3D mlx5_lag_pf(ldev, i)->dev; + if (is_mdev_switchdev_mode(dev) && + mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch) && + MLX5_CAP_GEN(dev, lag_native_fdb_selection) && + MLX5_CAP_ESW(dev, root_ft_on_other_esw) && + mlx5_eswitch_get_npeers(dev->priv.eswitch) =3D=3D + MLX5_CAP_GEN(dev, num_lag_ports) - 1) + continue; + return false; + } + + dev =3D mlx5_lag_pf(ldev, idx)->dev; + if (is_mdev_switchdev_mode(dev) && + mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch) && + mlx5_esw_offloads_devcom_is_ready(dev->priv.eswitch) && + MLX5_CAP_ESW(dev, esw_shared_ingress_acl) && + mlx5_eswitch_get_npeers(dev->priv.eswitch) =3D=3D + MLX5_CAP_GEN(dev, num_lag_ports) - 1) + ret =3D true; + + return ret; +} + +int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) +{ + int master_idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); + struct mlx5_eswitch *master_esw; + struct mlx5_core_dev *dev0; + int i, j; + int err; + + if (master_idx < 0) + return -EINVAL; + + dev0 =3D mlx5_lag_pf(ldev, master_idx)->dev; + master_esw =3D dev0->priv.eswitch; + mlx5_ldev_for_each(i, 0, ldev) { + struct mlx5_eswitch *slave_esw; + + if (i =3D=3D master_idx) + continue; + + slave_esw =3D mlx5_lag_pf(ldev, i)->dev->priv.eswitch; + + err =3D mlx5_eswitch_offloads_single_fdb_add_one(master_esw, + slave_esw, + ldev->ports); + if (err) + goto err; + } + return 0; +err: + mlx5_ldev_for_each_reverse(j, i, 0, ldev) { + struct mlx5_eswitch *slave_esw; + + if (j =3D=3D master_idx) + continue; + slave_esw =3D mlx5_lag_pf(ldev, j)->dev->priv.eswitch; + mlx5_eswitch_offloads_single_fdb_del_one(master_esw, slave_esw); + } + return err; +} + +int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, + struct lag_tracker *tracker, + enum mlx5_lag_mode mode) +{ + int idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); + struct mlx5_core_dev *dev0; + int err; + + if (idx < 0) + return -EINVAL; + + dev0 =3D mlx5_lag_pf(ldev, idx)->dev; + + mlx5_lag_remove_devices(ldev); + + err =3D mlx5_activate_lag(ldev, tracker, mode, true); + if (err) { + mlx5_core_warn(dev0, "Failed to create LAG in shared FDB mode (%d)\n", + err); + goto err_add_devices; + } + + mlx5_lag_rescan_dev_locked(ldev, dev0, true); + err =3D mlx5_lag_reload_ib_reps_from_locked(ldev, 0, false); + if (err) { + mlx5_core_err(dev0, "Failed to enable lag\n"); + goto err_rescan_drivers; + } + + mlx5_lag_set_vports_agg_speed(ldev); + return 0; + +err_rescan_drivers: + mlx5_lag_rescan_dev_locked(ldev, dev0, false); + mlx5_deactivate_lag(ldev); +err_add_devices: + mlx5_lag_add_devices(ldev); + mlx5_lag_reload_ib_reps_from_locked(ldev, 0, true); + return err; +} + +void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev) +{ + int err; + + mlx5_lag_remove_devices(ldev); + + err =3D mlx5_deactivate_lag(ldev); + if (err) + return; + + mlx5_lag_add_devices(ldev); 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Wed, 27 May 2026 05:55:11 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 02/13] net/mlx5: E-Switch, align disable sequence with switchdev-to-legacy transition Date: Wed, 27 May 2026 15:54:16 +0300 Message-ID: <20260527125427.385976-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E65:EE_|DM3PR12MB9434:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d41d194-f867-4c95-a050-08debbef3f43 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014|18002099003|22082099003|6133799003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: Lcf5YAjAxCLZTulMHMc72WLRtSaGXokFN02QtXQ+bdjhlkMRU8t6jnmNEueJW7gT1QCL5jVhoKYOGj+B20sDv0eUF/aSY67gxpls2LBr7gbf87BBVL/tgvyrHLuUJje3ImGNQP8sJMh1eXvii2q6neKAdEJZ2g7TZzcb0S4EvELCuuFo7+4rpa57G+YividYyn0DTEOzUQH/ot2fzoDdVxZjJ9zjKF7x1a717dOxwM0PXdbxBsj29b+J/K2nqW5vRGSQve5jNr7OTPzxfl1s4oUTRsCgLe7vOjsCj/vIn7hwDaheviCNl3miLpXBNhYek2YpfLzcJQMRWlubL0CinUrL9UckR6Xjw8iYp2kWL1u3zA7IE9afdLnb9ii+HOs6TqiC81tztLLcVv/kX9qLhki2Uqi4VH3UpnCCc1acGZasm3l4vONUgc82TCd2uByLsT7qLmyqRgy6QMwByqNb30KfBcu/orv1+VC34A8bg0UCwS/2ymce6AqDpXmSvBKyX1+BdUAji0Cv/TgUQ/qZBbPAjGaCK6DQP4m+WTRX/aAdaZ6AkB6ADn+bzJ66R7sZVlpa/V3wwsbMMe+fPpTwMec73nVPAFs1ezSUhXjtT45cKlrNfMNGojDm8XUvIa/fPEqZ048cwAI1NLLCDBb1e+04mzf5d8ZiJ65waLbyqZ2LRlJW+fXuxYG4c395XCfmrPXgNp5tvVYHkbiFXPokrTGnvZke02mRIEK0FpYBhA4= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(7416014)(376014)(18002099003)(22082099003)(6133799003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nWoL9J/BpQTCjMqNrG3ujo3IRO1WKyTRzboPWQY4f2M3G46YMAa2gh/KenUgP7AF0ccxoeW6KnuxPf8b48oZNauS7MRVQlFchzJYFgZeeW91sJK/XoAUQcCmrt9xk9a3Cdhbq+ViGogD5V5nM7j+h5KHIqzQcvTyRax5Pj4pe3TpvVMfqOpI8FhRxr4ko56sPcwrkkwXxgnmQAMeMKR7I2VDjt/FE6OhffUi4NoOnuMTXZHOZCLmCKKF6YyxqRnuFZ3Xt5lZnNGE9SIr2RDPlEo4fpKxMnYzQjp5QYksWair7CjxqnhZ0Xda4TColgJkN54E9R2ARorcnwyp3IiM8Bix+D1WFstfuXTtfzY8Bb77cuTYkl5IKCubiQMWbL20Tw8/W7mfGyZfb/GTDsOPjXhS96xr84pTvOFiXHsYt6GwA67kfK4Kq4fe3nTtawtp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:55:36.5178 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d41d194-f867-4c95-a050-08debbef3f43 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E65.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9434 Content-Type: text/plain; charset="utf-8" From: Shay Drory This patch align the eswitch disable sequence with the switchdev-to-legacy mode transition, where eswitch must be disabled before device detachment. The consistent ordering is required for proper SD LAG cleanup which depends on eswitch state during teardown. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index 0c6e4efe38c8..fd285aeb9630 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1369,7 +1369,6 @@ static int mlx5_load(struct mlx5_core_dev *dev) =20 static void mlx5_unload(struct mlx5_core_dev *dev) { - mlx5_eswitch_disable(dev->priv.eswitch); mlx5_devlink_traps_unregister(priv_to_devlink(dev)); mlx5_vhca_event_stop(dev); mlx5_sf_dev_table_destroy(dev); @@ -1484,6 +1483,7 @@ void mlx5_uninit_one(struct mlx5_core_dev *dev) =20 mlx5_hwmon_dev_unregister(dev); mlx5_crdump_disable(dev); + mlx5_eswitch_disable(dev->priv.eswitch); mlx5_unregister_device(dev); =20 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { @@ -1568,6 +1568,7 @@ void mlx5_unload_one_devl_locked(struct mlx5_core_dev= *dev, bool suspend) devl_assert_locked(priv_to_devlink(dev)); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 03/13] net/mlx5: E-Switch, move devcom init from TC to eswitch layer Date: Wed, 27 May 2026 15:54:17 +0300 Message-ID: <20260527125427.385976-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E65:EE_|LV2PR12MB5847:EE_ X-MS-Office365-Filtering-Correlation-Id: 374f2b11-0a55-423e-1d2f-08debbef422f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|1800799024|6133799003|22082099003|56012099006|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: B4hpJdONit4/YC4SdUyBZVd8xWMH7ufof7mm0zC2Is7G09dw5hWfFYBCeK1JtE2D2UQnNq7Xo1cq+SNKhengMiPMJxEAgCySSgJYXceoOjXs4+305c5eT9bSFV4HSoqWODhRx8jfVIWWCSTCbM7AxyKIyWRm+VtwIlxqGTuG6VUVl0N7JRcZ/4x4S6AehAO72LCrBBagrxBM6C1nFA6g1JVxXICtMYx2W1laQ7JDIpm3oJ37TWbeEjcRk/09oD03Gha+wx1CxYiyouvsq9y4Af2Azg8SMYicDsd+XNi9E2n4tbB/AELJYRq59AiWdti53h9g3NoGG4USlMskUTA/Sftqv/vUtihgAiZV6ro5mB8o/nSMnaPhPysGleJEJHi3z8DdcJ6XKL2//+akWFkSzl0W0hGWMErp73Q/kHTj+K/CKVle9wu1qLoNIuZn+EeXmWW4sD/MiUZs9PBtTh6UKMXoeCta6b2FK53RCSCUowutGQPkPFuG5pxXiPHFJiQ0EyYXi1/zWLSe14RMCDZQY03UwNjlwtAHESQZ6pWiWxSiQJUob/ctQBAF1nvTVbOsdih7ehBcIQCHHJz3bhCVI5FNwHsX9QG+pLPGpbQ2KCNvPWyjHpxmPlQPbJDH/DyXEkSxSbANR2mwok0YffhQuuoz670sGomMs8cE896n66TBAZVIwLYGgUos2tNTmFzvUEU/Emc0IKeGFZOJGCF/34ku+7KxfyQSQPRmnrmSq1o= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(7416014)(376014)(1800799024)(6133799003)(22082099003)(56012099006)(18002099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: yDaRpsOJsDRzHpLJ32iq2amjJPNtAFhKUdgOD/ZspWnKoOcUrjHAlcd8IQT4CTWIOjtx4xOAG5C4/nnOTlua7r5ZKG1CAbp2u6L9LkF5TUDT2+zjywGqaHrlOvht+iEPUXt3SokDvne5SKkDWoHDi8ZEYu0PcL6VYLQhGK+ah81/fuMy8jIkmLlBtdZ7yMYYizsJm2K22eUga5aCN5Su34t2KKzXwu8oa/jitbSt9YyoMw0ApUrJ3MxaiItH8e/iW9K0t3g3dTsenrzRUzR/Ul/rurqsN7Q8NG+1k4sfhxl6QhdrGeRCyFxwnB5pROAMxd8bDKmXvjmgrjhY7LAb/b+HCKQ2G8Uu1Z5d2tyaPsLfsfB/YKqgdP6FKkIzIasjoRbXSZAL427scS9DQqF20GE2Zf6A7UIlO8rSEyHkXeXImUkSyU9YzjYjiJaQbtqD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:55:41.4234 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 374f2b11-0a55-423e-1d2f-08debbef422f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E65.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5847 Content-Type: text/plain; charset="utf-8" From: Shay Drory Move the E-swtich devcom component management from TC layer to ESW layer. This refactoring places devcom lifecycle management at the appropriate layer and prepares for SD LAG which needs devcom registration independent of the TC/representor initialization. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_tc.c | 20 ------------------- .../mellanox/mlx5/core/eswitch_offloads.c | 6 ++++++ 2 files changed, 6 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tc.c index a9001d1c902f..3846c16c3138 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -5394,8 +5394,6 @@ int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *up= link_priv) { const size_t sz_enc_opts =3D sizeof(struct tunnel_match_enc_opts); u8 mapping_id[MLX5_SW_IMAGE_GUID_MAX_BYTES]; - struct mlx5_devcom_match_attr attr =3D {}; - struct netdev_phys_item_id ppid; struct mlx5e_rep_priv *rpriv; struct mapping_ctx *mapping; struct mlx5_eswitch *esw; @@ -5456,14 +5454,6 @@ int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *u= plink_priv) goto err_action_counter; } =20 - err =3D netif_get_port_parent_id(priv->netdev, &ppid, false); - if (!err) { - memcpy(&attr.key.buf, &ppid.id, ppid.id_len); - attr.flags =3D MLX5_DEVCOM_MATCH_FLAGS_NS; - attr.net =3D mlx5_core_net(esw->dev); - mlx5_esw_offloads_devcom_init(esw, &attr); - } - return 0; =20 err_action_counter: @@ -5484,16 +5474,6 @@ int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *u= plink_priv) =20 void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv) { - struct mlx5e_rep_priv *rpriv; - struct mlx5_eswitch *esw; - struct mlx5e_priv *priv; - - rpriv =3D container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv); - priv =3D netdev_priv(rpriv->netdev); - esw =3D priv->mdev->priv.eswitch; - - mlx5_esw_offloads_devcom_cleanup(esw); - mlx5e_tc_tun_cleanup(uplink_priv->encap); =20 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 189be11c4c39..d9683d3ea0e7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3866,6 +3866,7 @@ bool mlx5_esw_offloads_controller_valid(const struct = mlx5_eswitch *esw, u32 cont int esw_offloads_enable(struct mlx5_eswitch *esw) { u8 mapping_id[MLX5_SW_IMAGE_GUID_MAX_BYTES]; + struct mlx5_devcom_match_attr attr =3D {}; struct mapping_ctx *reg_c0_obj_pool; struct mlx5_vport *vport; unsigned long i; @@ -3926,6 +3927,10 @@ int esw_offloads_enable(struct mlx5_eswitch *esw) if (err) goto err_vports; =20 + memcpy(attr.key.buf, mapping_id, id_len); + attr.flags =3D MLX5_DEVCOM_MATCH_FLAGS_NS; + attr.net =3D mlx5_core_net(esw->dev); + mlx5_esw_offloads_devcom_init(esw, &attr); return 0; =20 err_vports: @@ -3970,6 +3975,7 @@ static int esw_offloads_stop(struct mlx5_eswitch *esw, =20 void esw_offloads_disable(struct mlx5_eswitch *esw) { + mlx5_esw_offloads_devcom_cleanup(esw); mlx5_eswitch_disable_pf_vf_vports(esw); mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK); esw_set_passing_vport_metadata(esw, false); --=20 2.44.0 From nobody Mon Jun 8 18:55:59 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010067.outbound.protection.outlook.com [40.93.198.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5127C3F58FE; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 04/13] net/mlx5: LAG, replace peer count check with direct peer lookup Date: Wed, 27 May 2026 15:54:18 +0300 Message-ID: <20260527125427.385976-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB74:EE_|MN2PR12MB4440:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b266b51-02ca-4e64-40c5-08debbef4406 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|7416014|1800799024|22082099003|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: dOG42C6G70/8hdn68c+V25lfn8ujselU6h3n7psMrXDw7qpliyySg+PSCLYF6ZG80J9sZF9sn3ct5tdKKu/iHvv+Czr7v6DMvoDFGKv54BCeInDR6QrT023fS4107vRawZNtObyRg4nWOQOoiWLs0QflO1L9TE1cvRUnq0VhYLmx224rA5rTfI4nrUdnlq/UvDiaRIgYbg4xUUH59yjeXEImAg4AxSvBbyto8qpwFf4cZEFPA0XtlUYPYzAJeW1pY0zHE6N9cuPW5Ht06XNhPrMTTPWLr+VER/BKX093nJ+wfplJ80ipqt9Aq8fSJN4SFhOJwBngoAXcQwjQxmi4q4iMtivdeqqiNpvpjkTnNNkqXkEeJCRHM1HwLQgEshDLLf2lsGH/zzXmgkOIj4oEx7EzxjFLqWzauVeHkPlpJjQa1WqNnbVumeB0JH9aPPFOhl+mjr4gyQXroimM9L8ufTS3vCi157EdpRS/QzHPFAeQ7PwMcm5P+jt6jyg/F6lp2b2KZBtRnRFE8TE4AOm4EoQsN8TY1D98VMJvBZjz1aAA5+1nEkb4d+3d/zmv+/7gcDDJ3BVaVbtLWO058eewNIejsl3knhQaRppuMoRATKr44CRGF5n928RXl5ik01iHx8VszbD7EkEk96iOsL0utGU5SvofJ6SvVs6GHfbRbfcFASsKWTMa1883Om3q6BjRfzDROO5BuegH8/YptLiMBryK/KkMOy3PEVQc+PxeOrw= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(7416014)(1800799024)(22082099003)(18002099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: iQGyqBnDWIMyG1lmO9YGC4kIDsyj7x4aEu/2+UtsXUVwMyWFs7eJLQQvKlWfzT1ekzfr4bFXfhjyOpQzwb/L/oCBtTaJu3asnc46qHdBRh9B0HY/xXCYHXFP+xTf+XbMy0KASBikM079OzywrdCf4483kNnvlEWUQGQN/6ew+/lETnpjWag1Fc6pR+4RmoF9kGyUPYt0aaxVGcGvU/eNMAJes6KVRyQvhCLUYKpAbv/x1MP4nCqrSVAvInyQOuutiUaGMeAfyznhIUDUWyTEe6Ymm/X0MiSWw8n/4jsW43pYg/vQmyIe9A3Xzs3IfYVDcF5basxlK59Qn6sUAqadkV2JGraZ56ZY7DvAm+jJswJMT16j3eaI3EsTkC+kYKU7ntrHPEx6/862BLzfg7gf0BSUOXreDvLEwq+hMR66BS1sEWl1nWg+IbPAdSs774J6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:55:44.4069 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b266b51-02ca-4e64-40c5-08debbef4406 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4440 Content-Type: text/plain; charset="utf-8" From: Shay Drory Replace mlx5_eswitch_get_npeers() count-based check with a new mlx5_eswitch_is_peer() function that directly verifies the peer relationship between two eswitches. This change prepares for SD LAG support, which is a virtual LAG that does not have num_lag_ports capability and cannot use the count-based peer validation. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 11 ++--------- .../mellanox/mlx5/core/eswitch_offloads.c | 12 ++++++++++++ .../mellanox/mlx5/core/lag/shared_fdb.c | 17 +++++++---------- 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 8a94c38f8566..94a530d19828 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -955,6 +955,8 @@ int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx= 5_eswitch *master_esw, void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_= esw, struct mlx5_eswitch *slave_esw); int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw); +bool mlx5_eswitch_is_peer(struct mlx5_eswitch *esw, + struct mlx5_eswitch *peer_esw); =20 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb); void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev); @@ -970,13 +972,6 @@ static inline int mlx5_eswitch_num_vfs(struct mlx5_esw= itch *esw) return 0; } =20 -static inline int mlx5_eswitch_get_npeers(struct mlx5_eswitch *esw) -{ - if (mlx5_esw_allowed(esw)) - return esw->num_peers; - return 0; -} - static inline struct mlx5_flow_table * mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch *esw) { @@ -1058,8 +1053,6 @@ static inline void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, struct mlx5_eswitch *slave_esw) {} =20 -static inline int mlx5_eswitch_get_npeers(struct mlx5_eswitch *esw) { retu= rn 0; } - static inline int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index d9683d3ea0e7..d65f30bb2f80 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3296,6 +3296,18 @@ static int mlx5_esw_offloads_set_ns_peer(struct mlx5= _eswitch *esw, return 0; } =20 +bool mlx5_eswitch_is_peer(struct mlx5_eswitch *esw, + struct mlx5_eswitch *peer_esw) +{ + u16 peer_esw_i; + + if (!mlx5_esw_allowed(esw) || !mlx5_esw_allowed(peer_esw)) + return false; + + peer_esw_i =3D MLX5_CAP_GEN(peer_esw->dev, vhca_id); + return !!xa_load(&esw->paired, peer_esw_i); +} + static int mlx5_esw_offloads_devcom_event(int event, void *my_data, void *event_data) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/dri= vers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c index e5b8e9f1e6fd..b5cbe3409720 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c @@ -10,7 +10,7 @@ =20 bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) { - struct mlx5_core_dev *dev; + struct mlx5_core_dev *dev0, *dev; bool ret =3D false; int idx; int i; @@ -19,6 +19,7 @@ bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) if (idx < 0) return false; =20 + dev0 =3D mlx5_lag_pf(ldev, idx)->dev; mlx5_ldev_for_each(i, 0, ldev) { if (i =3D=3D idx) continue; @@ -27,19 +28,15 @@ bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *lde= v) mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch) && MLX5_CAP_GEN(dev, lag_native_fdb_selection) && MLX5_CAP_ESW(dev, root_ft_on_other_esw) && - mlx5_eswitch_get_npeers(dev->priv.eswitch) =3D=3D - MLX5_CAP_GEN(dev, num_lag_ports) - 1) + mlx5_eswitch_is_peer(dev0->priv.eswitch, dev->priv.eswitch)) continue; return false; } =20 - dev =3D mlx5_lag_pf(ldev, idx)->dev; - if (is_mdev_switchdev_mode(dev) && - mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch) && - mlx5_esw_offloads_devcom_is_ready(dev->priv.eswitch) && - MLX5_CAP_ESW(dev, esw_shared_ingress_acl) && - mlx5_eswitch_get_npeers(dev->priv.eswitch) =3D=3D - MLX5_CAP_GEN(dev, num_lag_ports) - 1) + if (is_mdev_switchdev_mode(dev0) && + mlx5_eswitch_vport_match_metadata_enabled(dev0->priv.eswitch) && + mlx5_esw_offloads_devcom_is_ready(dev0->priv.eswitch) && + MLX5_CAP_ESW(dev0, esw_shared_ingress_acl)) ret =3D true; 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Wed, 27 May 2026 05:55:29 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 05/13] net/mlx5: LAG, prepare for SD device integration Date: Wed, 27 May 2026 15:54:19 +0300 Message-ID: <20260527125427.385976-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E66:EE_|DS0PR12MB6413:EE_ X-MS-Office365-Filtering-Correlation-Id: 48c2c278-82c3-4ad5-f09a-08debbef494d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|376014|7416014|6133799003|22082099003|56012099006|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: d6kmjgG7zLD3WBDVArfOuWPta3s3MA1c6SYjc+W6QamQ/1OJErwQPBKEuIiwirqvnNC0H16QdtPqonx1X5QhK7bnPuwS3h5ZwP8qCyHcYIHPTq5cgoPMxgTlt5cf1PWW/tgw+W37miTJ4b3mTUlivCs2Ukju2GVXMPksbQ8Hg6XxPbvE29JMRazmPdMg5jyRdOwNo41lXi6aPmjaKQOg4euWcNBw0W2FCh82mT0DIhkKrI7Rl3ajTQqnHEYsF3ePRr7iJWc7HO+RsCxJzVchtX6LALF1/f4W3PA1F/78Qv6Ox60tUSIBmfmZ2z0+/P2mVVisjG4jvVylAgNbDWpqDavQFlrMXC/v9uJDyd7lSiphLaiQcAla71gGsvfabqxo1YhLmtlx2j4tYOfvbEby5Dcvl22xEP7GcnWrQIj7oWFB6g+MkX3GhilD2bOR0eMILaU3+2EBbmHEswPln2UpWR2tvRHVToTRtBbwn2CDNJipfwqv16S0z0vBY0/ufSthgQieCG4/i/MRk2l4zsP7hnkKOVC4K1rg5ihJIl9KRhQmnNqqKMEhoWjwCkUcVn7q/iNvD9QFYxSTfRywJ4FBN8edVqgGkEJ+7ibTX5EiALJ01FX58tJNUPkINUApeePO3M3mpNxUdPbJMkSSOHSxN0tpHBvwJ2uiRpJxzw0ecFRu3Il9AnbLYgbV9a/GAHwjrdC0wWxXlF658nj+FS1f/DXS3CcvulgleWwkbPmJWYY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(376014)(7416014)(6133799003)(22082099003)(56012099006)(18002099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VdlRQvXCTdH9tTJAdjSRZM7ZrjyAxLmIYAl1plcsGlHcohX7XH21wCSEupzSR+ysL6Zv/PIFoXxx0KP/RbfY66irNKBCRAhPPErhb3C96KhZcXrSyNYECZTrXqmD27/6xQC7OWFUZb7WuzCJaO4Xrxhjxxu1+cb6D+00uHcg1rkgsIFG087wcdQh5Rr1L+5LOFo863BCMPo4HkJ9PZFCIaDFV8O1+xKuKJsfn0artm5Tuq0Pm7IMibnIhL1BkrI76FlSh773Ct48u+sF3qaJadd+mjkEwdqwXfP7is5LjzRDVclMciP9b25UAFXwVQYS+w6oF3jffFivy8UEDoA6a0Sr4bRbYrumlq/BwplVfuumKSIiPJ1LJvZ+8BmneJV8Lmhwrbae/vUrcBtCJHZXEA2SF2H/6sTOSBL8+16VXkyrcEqKVciBht4VIleq+5g0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:55:53.3730 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48c2c278-82c3-4ad5-f09a-08debbef494d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E66.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6413 Content-Type: text/plain; charset="utf-8" From: Shay Drory Socket Direct (SD) secondaries devices will participate in LAG, even though they are silent. SD secondary devices share the same physical port as their primary but are separate PCI functions that need to be tracked alongside regular LAG ports. Extend lag_func with a group_id field to identify SD group membership and introduce a unified iterator that can filter by group. Add APIs for registering SD secondary devices in an existing LAG. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 59 ++++++++++++++----- .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 53 +++++++++++++++-- 2 files changed, 90 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 5dfdd799828f..03cb02c7000d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -242,7 +242,7 @@ static void mlx5_ldev_free(struct kref *ref) unregister_netdevice_notifier_net(net, &ldev->nb); } =20 - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { pf =3D mlx5_lag_pf(ldev, i); if (pf->port_change_nb.nb.notifier_call) { struct mlx5_nb *nb =3D &pf->port_change_nb; @@ -391,7 +391,7 @@ int mlx5_lag_get_dev_seq(struct mlx5_core_dev *dev) if (pf && pf->dev =3D=3D dev) return 0; =20 - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { if (i =3D=3D master_idx) continue; pf =3D mlx5_lag_pf(ldev, i); @@ -1034,7 +1034,7 @@ static void mlx5_lag_assert_locked_transition(struct = mlx5_lag *ldev) =20 lockdep_assert_held(&ldev->lock); =20 - i =3D mlx5_get_next_ldev_func(ldev, 0); + i =3D mlx5_get_next_lag_func(ldev, 0, MLX5_LAG_FILTER_PORTS); if (i < MLX5_MAX_PORTS) { pf =3D mlx5_lag_pf(ldev, i); devcom =3D pf->dev->priv.hca_devcom_comp; @@ -1482,7 +1482,7 @@ struct mlx5_devcom_comp_dev *mlx5_lag_get_devcom_comp= (struct mlx5_lag *ldev) int i; =20 mutex_lock(&ldev->lock); - i =3D mlx5_get_next_ldev_func(ldev, 0); + i =3D mlx5_get_next_lag_func(ldev, 0, MLX5_LAG_FILTER_PORTS); if (i < MLX5_MAX_PORTS) { pf =3D mlx5_lag_pf(ldev, i); devcom =3D pf->dev->priv.hca_devcom_comp; @@ -1965,8 +1965,9 @@ static void mlx5_ldev_remove_netdev(struct mlx5_lag *= ldev, spin_unlock_irqrestore(&lag_lock, flags); } =20 -static int mlx5_ldev_add_mdev(struct mlx5_lag *ldev, - struct mlx5_core_dev *dev) +int mlx5_ldev_add_mdev(struct mlx5_lag *ldev, + struct mlx5_core_dev *dev, + u32 group_id) { struct lag_func *pf; u32 idx; @@ -1985,8 +1986,14 @@ static int mlx5_ldev_add_mdev(struct mlx5_lag *ldev, =20 pf->idx =3D idx; pf->dev =3D dev; + pf->group_id =3D group_id; dev->priv.lag =3D ldev; =20 + if (group_id) + return 0; + + xa_set_mark(&ldev->pfs, idx, MLX5_LAG_XA_MARK_PORT); + MLX5_NB_INIT(&pf->port_change_nb, mlx5_lag_mpesw_port_change_event, PORT_CHANGE); mlx5_eq_notifier_register(dev, &pf->port_change_nb); @@ -1994,13 +2001,13 @@ static int mlx5_ldev_add_mdev(struct mlx5_lag *ldev, return 0; } =20 -static void mlx5_ldev_remove_mdev(struct mlx5_lag *ldev, - struct mlx5_core_dev *dev) +void mlx5_ldev_remove_mdev(struct mlx5_lag *ldev, + struct mlx5_core_dev *dev) { struct lag_func *pf; int i; =20 - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { pf =3D mlx5_lag_pf(ldev, i); if (pf->dev =3D=3D dev) break; @@ -2035,7 +2042,7 @@ static int __mlx5_lag_dev_add_mdev(struct mlx5_core_d= ev *dev) mlx5_core_err(dev, "Failed to alloc lag dev\n"); return 0; } - err =3D mlx5_ldev_add_mdev(ldev, dev); + err =3D mlx5_ldev_add_mdev(ldev, dev, 0); if (err) { mlx5_core_err(dev, "Failed to add mdev to lag dev\n"); mlx5_ldev_put(ldev); @@ -2050,7 +2057,7 @@ static int __mlx5_lag_dev_add_mdev(struct mlx5_core_d= ev *dev) return -EAGAIN; } mlx5_ldev_get(ldev); - err =3D mlx5_ldev_add_mdev(ldev, dev); + err =3D mlx5_ldev_add_mdev(ldev, dev, 0); if (err) { mlx5_ldev_put(ldev); mutex_unlock(&ldev->lock); @@ -2187,27 +2194,47 @@ void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, mlx5_queue_bond_work(ldev, 0); } =20 -int mlx5_get_pre_ldev_func(struct mlx5_lag *ldev, int start_idx, int end_i= dx) +int mlx5_get_pre_lag_func(struct mlx5_lag *ldev, int start_idx, int end_id= x, + u32 filter) { struct lag_func *pf; int i; =20 for (i =3D start_idx; i >=3D end_idx; i--) { pf =3D xa_load(&ldev->pfs, i); - if (pf && pf->dev) + if (!pf || !pf->dev) + continue; + if (filter =3D=3D MLX5_LAG_FILTER_PORTS) { + if (xa_get_mark(&ldev->pfs, i, MLX5_LAG_XA_MARK_PORT)) + return i; + } else if (filter =3D=3D MLX5_LAG_FILTER_ALL || + filter =3D=3D pf->group_id) { return i; + } } return -1; } =20 -int mlx5_get_next_ldev_func(struct mlx5_lag *ldev, int start_idx) +int mlx5_get_next_lag_func(struct mlx5_lag *ldev, int start_idx, u32 filte= r) { struct lag_func *pf; unsigned long idx; =20 - xa_for_each_start(&ldev->pfs, idx, pf, start_idx) - if (pf->dev) + if (filter =3D=3D MLX5_LAG_FILTER_PORTS) { + xa_for_each_marked_start(&ldev->pfs, idx, pf, + MLX5_LAG_XA_MARK_PORT, start_idx) + if (pf->dev) + return idx; + return MLX5_MAX_PORTS; + } + + xa_for_each_start(&ldev->pfs, idx, pf, start_idx) { + if (!pf->dev) + continue; + if (filter =3D=3D MLX5_LAG_FILTER_ALL || + filter =3D=3D pf->group_id) return idx; + } return MLX5_MAX_PORTS; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index 23c0457ce799..70baa7997364 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -15,6 +15,13 @@ * Note: XA_MARK_0 is reserved by XA_FLAGS_ALLOC for free-slot tracking. */ #define MLX5_LAG_XA_MARK_MASTER XA_MARK_1 +/* XArray mark for port-level entries (excludes SD secondaries) */ +#define MLX5_LAG_XA_MARK_PORT XA_MARK_2 + +/* Like xa_for_each_marked but starting from a given index */ +#define xa_for_each_marked_start(xa, index, entry, filter, start) \ + for (index =3D start, entry =3D xa_find(xa, &index, ULONG_MAX, filter); \ + entry; entry =3D xa_find_after(xa, &index, ULONG_MAX, filter)) =20 #include "mlx5_core.h" #include "mp.h" @@ -50,6 +57,8 @@ struct lag_func { bool has_drop; unsigned int idx; /* xarray index assigned by LAG */ struct mlx5_nb port_change_nb; + u32 group_id; /* SD group ID, 0 =3D not SD */ + bool sd_fdb_active; /* set on all SD group members */ }; =20 /* Used for collection of netdev event info. */ @@ -125,6 +134,20 @@ mlx5_lag_pf_by_dev_idx(struct mlx5_lag *ldev, int dev_= idx) return NULL; } =20 +/* Find lag_func by mlx5_core_dev pointer */ +static inline struct lag_func * +mlx5_lag_pf_by_dev(struct mlx5_lag *ldev, struct mlx5_core_dev *dev) +{ + struct lag_func *pf; + unsigned long idx; + + xa_for_each(&ldev->pfs, idx, pf) { + if (pf->dev =3D=3D dev) + return pf; + } + return NULL; +} + static inline bool __mlx5_lag_is_active(struct mlx5_lag *ldev) { @@ -214,20 +237,38 @@ static inline bool mlx5_lag_is_supported(struct mlx5_= core_dev *dev) return true; } =20 -#define mlx5_ldev_for_each(i, start_index, ldev) \ - for (int tmp =3D start_index; tmp =3D mlx5_get_next_ldev_func(ldev, tmp),= \ +/* Iterator filter constants for mlx5_lag_for_each() */ +#define MLX5_LAG_FILTER_ALL 0 /* iterate ALL devices */ +#define MLX5_LAG_FILTER_PORTS U32_MAX /* iterate ports only (XA_MARK_PORT= ) */ +/* any other value =3D iterate devices with that specific group_id */ + +#define mlx5_lag_for_each(i, start_index, ldev, filter) \ + for (int tmp =3D start_index; \ + tmp =3D mlx5_get_next_lag_func(ldev, tmp, filter), \ i =3D tmp, tmp < MLX5_MAX_PORTS; tmp++) =20 -#define mlx5_ldev_for_each_reverse(i, start_index, end_index, ldev) \ +#define mlx5_lag_for_each_reverse(i, start_index, end_index, ldev, filter)= \ for (int tmp =3D start_index, tmp1 =3D end_index; \ - tmp =3D mlx5_get_pre_ldev_func(ldev, tmp, tmp1), \ + tmp =3D mlx5_get_pre_lag_func(ldev, tmp, tmp1, filter), \ i =3D tmp, tmp >=3D tmp1; tmp--) =20 -int mlx5_get_pre_ldev_func(struct mlx5_lag *ldev, int start_idx, int end_i= dx); -int mlx5_get_next_ldev_func(struct mlx5_lag *ldev, int start_idx); +/* Convenience wrappers - keeps existing behavior */ +#define mlx5_ldev_for_each(i, start_index, ldev) \ + mlx5_lag_for_each(i, start_index, ldev, MLX5_LAG_FILTER_PORTS) + +#define mlx5_ldev_for_each_reverse(i, start_index, end_index, ldev) \ + mlx5_lag_for_each_reverse(i, start_index, end_index, ldev, \ + MLX5_LAG_FILTER_PORTS) + +int mlx5_get_pre_lag_func(struct mlx5_lag *ldev, int start_idx, int end_id= x, + u32 filter); +int mlx5_get_next_lag_func(struct mlx5_lag *ldev, int start_idx, u32 filte= r); int mlx5_lag_get_dev_index_by_seq(struct mlx5_lag *ldev, int seq); int mlx5_lag_num_devs(struct mlx5_lag *ldev); int mlx5_lag_num_netdevs(struct mlx5_lag *ldev); int mlx5_lag_reload_ib_reps_from_locked(struct mlx5_lag *ldev, u32 flags, bool cont_on_fail); +int mlx5_ldev_add_mdev(struct mlx5_lag *ldev, struct mlx5_core_dev *dev, + u32 group_id); +void mlx5_ldev_remove_mdev(struct mlx5_lag *ldev, struct mlx5_core_dev *de= v); #endif /* __MLX5_LAG_H__ */ --=20 2.44.0 From nobody Mon Jun 8 18:55:59 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012024.outbound.protection.outlook.com [40.107.200.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 399073F39E3; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 06/13] net/mlx5: LAG, extend shared FDB API with group_id filter Date: Wed, 27 May 2026 15:54:20 +0300 Message-ID: <20260527125427.385976-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|CY8PR12MB7491:EE_ X-MS-Office365-Filtering-Correlation-Id: e8c72a3e-92fa-454b-eb79-08debbef4a19 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|7416014|376014|1800799024|11063799006|56012099006|6133799003|18002099003|22082099003|3023799007; X-Microsoft-Antispam-Message-Info: 2HpjEIzDEfqIrnC5jfW+BIcYQcwdv9XoongoPXAP1FUwdeFyCeWiIfjOQIq0wk5zG5wOfHauTSFbsW+LVAsolsKEltFt52awqi8jAVvviAHexdskD8D4QdcIxRnb0was5nHz+ikWdCPrtjo3DK8RnCwREwsHEHy0e4IFiTNDh6Dr9fHsEzpnX+a8o9icD5Jshky0W112jHGcZ1DCnbgtQdkZ+RotwrZoFdjRjhoWr21BfEbY7aHDMmPluKat/4Mx1lLtdkTYbjLD+eoBh4g/YYURFsLXKrk1GYhFrOHTrzA0t4ZFtAqYgl8h6ZciJNW0L+LCtRclEOVn3EJoIsODFawVW2TdCwBk65hT36bzjqFBsZT8SpMQ7CorFMqU9qdLw/Z1kdUfVFzI+maE5miySHiGw7jGVIgj0FTSVhQ15mxVT3kAhemeK9KPAEQrwW1prRr/40uw1oslxzHQtg7PstPIER7hLBGySOWRjzJ9wXXcpSezo0/W9nCmEWUn7NKnovQMNRYSHJu8cMXiC1hQEK2DTFhZx9Z9D0G/tOQ6fxlv1eBvib97dODYNHqjPVOeu4P5HMGTki3Ain1WStwy9U+C2zlWjw1vI7/lWBGCGqPv4fnqiGHkJogQZqmsXmgH9FplerBqdlmlXE3HcGqGN/zKjjmgBLCrTs2IOU3YfjeuFHP5qld6zoqvYXdKonUuuzdpXJM2GAlro+DO5DIkwas+Jkt6YzDQCw4si6/Y680= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(7416014)(376014)(1800799024)(11063799006)(56012099006)(6133799003)(18002099003)(22082099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dKZP5IWS+koCHu8i2kHA8y+sYgYNv+LEqyBkjX902D0Mwf4WtoTvJkNuDoOAA/HyUn9EYykDhFi4u/6myxJnP5a9kRs25n3wN7yTOSRHgsYnbcPKPqBnPKLViNNL3LChIWbWcWeEuBWD2wiKXm3n+vhqMtn6IIn/qsPFVeGHbXF/zHgzFLtmXR7PYl1TT2RKZzpPd+KiAZU734uWnKY14fb6Hszvib1BNh1NtpHTMErTQImmffMF5U/IMQ/MN6B+R82Ac2tt5xc6kFYa9rNC90F4qW1PcsfJ1bauWk/Ob42wCP9iaYItQCbF0UVueFKcNi8aV8Vussy0LFHrQmzEuNs0FPhrj7ZvhwkD9KEBjr3P0uuLinXIJttfhYBv1lT/Y0iRby05BI69gzlcFWhl2SfYj25WLMT7DZOAOM2LcpyKVEnQ+E5MSmuhZGhIdw7q X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:55:54.5999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e8c72a3e-92fa-454b-eb79-08debbef4a19 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7491 Content-Type: text/plain; charset="utf-8" From: Shay Drory Add a group_id parameter to mlx5_lag_shared_fdb_create() and mlx5_lag_shared_fdb_destroy() to scope shared FDB operations to a specific SD group. When group_id is U32_MAX, the functions operate on all LAG devices. When group_id is non-zero, they operate only on devices in that SD group without issuing FW LAG commands, since SD LAG is a pure software construct. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 195 ++++++++++++++---- .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 32 ++- .../ethernet/mellanox/mlx5/core/lag/mpesw.c | 7 +- .../mellanox/mlx5/core/lag/shared_fdb.c | 151 +++++++++++--- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 10 + .../net/ethernet/mellanox/mlx5/core/lib/sd.h | 10 + 6 files changed, 322 insertions(+), 83 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 03cb02c7000d..3decb49e9f19 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -370,6 +370,22 @@ int mlx5_lag_get_dev_index_by_seq(struct mlx5_lag *lde= v, int seq) return -ENOENT; } =20 +/* Return the appropriate iterator filter for a device in LAG: + * - SD shared FDB active: iterate only the device's SD group + * - SD group exists but shared FDB not active: iterate all devices + * - No SD: iterate ports only + */ +static u32 mlx5_lag_get_filter(struct mlx5_lag *ldev, struct mlx5_core_dev= *dev) +{ + struct lag_func *pf =3D mlx5_lag_pf_by_dev(ldev, dev); + + if (pf && pf->sd_fdb_active) + return pf->group_id; + if (pf && pf->group_id) + return MLX5_LAG_FILTER_ALL; + return MLX5_LAG_FILTER_PORTS; +} + /* Reverse of mlx5_lag_get_dev_index_by_seq: given a device, return its * sequence number in the LAG. Master is always 0, others numbered * sequentially starting from 1. @@ -379,11 +395,13 @@ int mlx5_lag_get_dev_seq(struct mlx5_core_dev *dev) struct mlx5_lag *ldev =3D mlx5_lag_dev(dev); int master_idx, i, num =3D 1; struct lag_func *pf; + u32 filter; =20 if (!ldev) return -ENOENT; =20 - master_idx =3D mlx5_lag_get_master_idx(ldev); + filter =3D mlx5_lag_get_filter(ldev, dev); + master_idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, 0, filter); if (master_idx < 0) return -ENOENT; =20 @@ -391,7 +409,7 @@ int mlx5_lag_get_dev_seq(struct mlx5_core_dev *dev) if (pf && pf->dev =3D=3D dev) return 0; =20 - mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { + mlx5_lag_for_each(i, 0, ldev, filter) { if (i =3D=3D master_idx) continue; pf =3D mlx5_lag_pf(ldev, i); @@ -403,6 +421,69 @@ int mlx5_lag_get_dev_seq(struct mlx5_core_dev *dev) } EXPORT_SYMBOL(mlx5_lag_get_dev_seq); =20 +/* seq 0 =3D master, then all remaining devices */ +static int mlx5_lag_get_dev_index_by_seq_all(struct mlx5_lag *ldev, int se= q) +{ + int master_idx, i, num =3D 0; + + master_idx =3D mlx5_lag_get_master_idx(ldev); + + if (master_idx >=3D 0) { + if (seq =3D=3D 0) + return master_idx; + num++; + } + + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { + if (i =3D=3D master_idx) + continue; + if (num =3D=3D seq) + return i; + num++; + } + return -ENOENT; +} + +/* From group POV, port-marked entry is the lag master */ +static int mlx5_lag_get_dev_index_by_seq_group(struct mlx5_lag *ldev, int = seq, + u32 group_id) +{ + int i, num =3D 0; + + mlx5_lag_for_each(i, 0, ldev, group_id) { + if (xa_get_mark(&ldev->pfs, i, MLX5_LAG_XA_MARK_PORT)) { + if (seq =3D=3D 0) + return i; + num++; + break; + } + } + + mlx5_lag_for_each(i, 0, ldev, group_id) { + if (xa_get_mark(&ldev->pfs, i, MLX5_LAG_XA_MARK_PORT)) + continue; + if (num =3D=3D seq) + return i; + num++; + } + return -ENOENT; +} + +int mlx5_lag_get_dev_index_by_seq_filter(struct mlx5_lag *ldev, int seq, + u32 filter) +{ + if (!ldev) + return -ENOENT; + + if (!filter || filter =3D=3D MLX5_LAG_FILTER_PORTS) + return mlx5_lag_get_dev_index_by_seq(ldev, seq); + + if (filter =3D=3D MLX5_LAG_FILTER_ALL) + return mlx5_lag_get_dev_index_by_seq_all(ldev, seq); + + return mlx5_lag_get_dev_index_by_seq_group(ldev, seq, filter); +} + /* Devcom events for LAG master marking */ #define LAG_DEVCOM_PAIR (0) #define LAG_DEVCOM_UNPAIR (1) @@ -512,6 +593,14 @@ static bool __mlx5_lag_is_sriov(struct mlx5_lag *ldev) return ldev->mode =3D=3D MLX5_LAG_MODE_SRIOV; } =20 +static bool __mlx5_lag_is_sd_active(struct mlx5_lag *ldev, + struct mlx5_core_dev *dev) +{ + struct lag_func *pf =3D mlx5_lag_pf_by_dev(ldev, dev); + + return pf && pf->sd_fdb_active; +} + /* Create a mapping between steering slots and active ports. * As we have ldev->buckets slots per port first assume the native * mapping should be used. @@ -927,27 +1016,19 @@ int mlx5_deactivate_lag(struct mlx5_lag *ldev) u32 in[MLX5_ST_SZ_DW(destroy_lag_in)] =3D {}; bool roce_lag =3D __mlx5_lag_is_roce(ldev); unsigned long flags =3D ldev->mode_flags; - struct mlx5_eswitch *master_esw; struct mlx5_core_dev *dev0; int err; - int i; =20 if (master_idx < 0) return -EINVAL; =20 dev0 =3D mlx5_lag_pf(ldev, master_idx)->dev; - master_esw =3D dev0->priv.eswitch; ldev->mode =3D MLX5_LAG_MODE_NONE; ldev->mode_flags =3D 0; mlx5_lag_mp_reset(ldev); =20 if (test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &flags)) { - mlx5_ldev_for_each(i, 0, ldev) { - if (i =3D=3D master_idx) - continue; - mlx5_eswitch_offloads_single_fdb_del_one(master_esw, - mlx5_lag_pf(ldev, i)->dev->priv.eswitch); - } + mlx5_lag_destroy_single_fdb(ldev); clear_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &flags); } =20 @@ -1026,7 +1107,7 @@ bool mlx5_lag_check_prereq(struct mlx5_lag *ldev) return true; } =20 -static void mlx5_lag_assert_locked_transition(struct mlx5_lag *ldev) +static void mlx5_lag_assert_locked_transition(struct mlx5_lag *ldev, u32 f= ilter) { struct mlx5_devcom_comp_dev *devcom =3D NULL; struct lag_func *pf; @@ -1034,17 +1115,21 @@ static void mlx5_lag_assert_locked_transition(struc= t mlx5_lag *ldev) =20 lockdep_assert_held(&ldev->lock); =20 - i =3D mlx5_get_next_lag_func(ldev, 0, MLX5_LAG_FILTER_PORTS); + i =3D mlx5_get_next_lag_func(ldev, 0, filter); if (i < MLX5_MAX_PORTS) { pf =3D mlx5_lag_pf(ldev, i); - devcom =3D pf->dev->priv.hca_devcom_comp; + if (filter =3D=3D MLX5_LAG_FILTER_PORTS || + filter =3D=3D MLX5_LAG_FILTER_ALL) + devcom =3D pf->dev->priv.hca_devcom_comp; + else + devcom =3D mlx5_sd_get_devcom(pf->dev); } mlx5_devcom_comp_assert_locked(devcom); } =20 -static void mlx5_lag_drop_lock_for_reps(struct mlx5_lag *ldev) +static void mlx5_lag_drop_lock_for_reps(struct mlx5_lag *ldev, u32 filter) { - mlx5_lag_assert_locked_transition(ldev); + mlx5_lag_assert_locked_transition(ldev, filter); =20 /* Keep PF membership stable while ldev->lock is dropped. Device add * and remove paths observe mode_changes_in_progress and retry. @@ -1075,21 +1160,22 @@ void mlx5_lag_rescan_dev_locked(struct mlx5_lag *ld= ev, * callbacks and take reps_lock. Drop ldev->lock so the only ordering * remains reps_lock -> ldev->lock from representor callbacks. */ - mlx5_lag_drop_lock_for_reps(ldev); + mlx5_lag_drop_lock_for_reps(ldev, mlx5_lag_get_filter(ldev, dev)); mlx5_rescan_drivers_locked(dev); mlx5_lag_retake_lock_after_reps(ldev); } =20 -static void mlx5_lag_rescan_devices_locked(struct mlx5_lag *ldev, bool ena= ble) +static void mlx5_lag_rescan_devices_locked_filter(struct mlx5_lag *ldev, + bool enable, u32 filter) { struct mlx5_core_dev *devs[MLX5_MAX_PORTS]; struct lag_func *pf; int num_devs =3D 0; int i; =20 - mlx5_lag_assert_locked_transition(ldev); + mlx5_lag_assert_locked_transition(ldev, filter); =20 - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, filter) { pf =3D mlx5_lag_pf(ldev, i); if (pf->dev->priv.flags & MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV) continue; @@ -1101,30 +1187,40 @@ static void mlx5_lag_rescan_devices_locked(struct m= lx5_lag *ldev, bool enable) devs[num_devs++] =3D pf->dev; } =20 - mlx5_lag_drop_lock_for_reps(ldev); + mlx5_lag_drop_lock_for_reps(ldev, filter); for (i =3D 0; i < num_devs; i++) mlx5_rescan_drivers_locked(devs[i]); mlx5_lag_retake_lock_after_reps(ldev); } =20 +void mlx5_lag_add_devices_filter(struct mlx5_lag *ldev, u32 filter) +{ + mlx5_lag_rescan_devices_locked_filter(ldev, true, filter); +} + void mlx5_lag_add_devices(struct mlx5_lag *ldev) { - mlx5_lag_rescan_devices_locked(ldev, true); + mlx5_lag_add_devices_filter(ldev, MLX5_LAG_FILTER_PORTS); +} + +void mlx5_lag_remove_devices_filter(struct mlx5_lag *ldev, u32 filter) +{ + mlx5_lag_rescan_devices_locked_filter(ldev, false, filter); } =20 void mlx5_lag_remove_devices(struct mlx5_lag *ldev) { - mlx5_lag_rescan_devices_locked(ldev, false); + mlx5_lag_remove_devices_filter(ldev, MLX5_LAG_FILTER_PORTS); } =20 static int mlx5_lag_reload_ib_reps_unlocked(struct mlx5_lag *ldev, u32 fla= gs, - bool cont_on_fail) + u32 filter, bool cont_on_fail) { struct lag_func *pf; int ret; int i; =20 - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, filter) { pf =3D mlx5_lag_pf(ldev, i); if (!(pf->dev->priv.flags & flags)) { struct mlx5_eswitch *esw; @@ -1142,7 +1238,7 @@ static int mlx5_lag_reload_ib_reps_unlocked(struct ml= x5_lag *ldev, u32 flags, } =20 static int mlx5_lag_reload_ib_reps(struct mlx5_lag *ldev, u32 flags, - bool cont_on_fail) + u32 filter, bool cont_on_fail) { int ret; =20 @@ -1152,21 +1248,18 @@ static int mlx5_lag_reload_ib_reps(struct mlx5_lag = *ldev, u32 flags, * load/unload callbacks can re-enter LAG netdev add/remove and take * ldev->lock. Keep the ordering reps_lock -> ldev->lock. */ - mlx5_lag_drop_lock_for_reps(ldev); - ret =3D mlx5_lag_reload_ib_reps_unlocked(ldev, flags, cont_on_fail); + mlx5_lag_drop_lock_for_reps(ldev, filter); + ret =3D mlx5_lag_reload_ib_reps_unlocked(ldev, flags, filter, + cont_on_fail); mlx5_lag_retake_lock_after_reps(ldev); =20 return ret; } =20 int mlx5_lag_reload_ib_reps_from_locked(struct mlx5_lag *ldev, u32 flags, - bool cont_on_fail) + u32 filter, bool cont_on_fail) { - int ret; - - ret =3D mlx5_lag_reload_ib_reps(ldev, flags, cont_on_fail); - - return ret; + return mlx5_lag_reload_ib_reps(ldev, flags, filter, cont_on_fail); } =20 void mlx5_disable_lag(struct mlx5_lag *ldev) @@ -1182,7 +1275,7 @@ void mlx5_disable_lag(struct mlx5_lag *ldev) return; =20 if (shared_fdb) { - mlx5_lag_shared_fdb_destroy(ldev); + mlx5_lag_shared_fdb_destroy(ldev, 0); return; } =20 @@ -1420,7 +1513,8 @@ static void mlx5_do_bond(struct mlx5_lag *ldev) =20 if (shared_fdb) { err =3D mlx5_lag_shared_fdb_create(ldev, &tracker, - MLX5_LAG_MODE_SRIOV); + MLX5_LAG_MODE_SRIOV, + 0); if (err) return; } else { @@ -2261,7 +2355,8 @@ bool mlx5_lag_is_active(struct mlx5_core_dev *dev) =20 spin_lock_irqsave(&lag_lock, flags); ldev =3D mlx5_lag_dev(dev); - res =3D ldev && __mlx5_lag_is_active(ldev); + res =3D ldev && (__mlx5_lag_is_active(ldev) || + __mlx5_lag_is_sd_active(ldev, dev)); spin_unlock_irqrestore(&lag_lock, flags); =20 return res; @@ -2294,10 +2389,17 @@ bool mlx5_lag_is_master(struct mlx5_core_dev *dev) =20 spin_lock_irqsave(&lag_lock, flags); ldev =3D mlx5_lag_dev(dev); - idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); - if (ldev && __mlx5_lag_is_active(ldev) && idx >=3D 0) { - pf =3D mlx5_lag_pf(ldev, idx); - res =3D pf && dev =3D=3D pf->dev; + if (ldev) { + u32 filter; + + filter =3D mlx5_lag_get_filter(ldev, dev); + idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); + if ((__mlx5_lag_is_active(ldev) || + __mlx5_lag_is_sd_active(ldev, dev)) && idx >=3D 0) { + pf =3D mlx5_lag_pf(ldev, idx); + res =3D pf && dev =3D=3D pf->dev; + } } spin_unlock_irqrestore(&lag_lock, flags); =20 @@ -2324,11 +2426,16 @@ bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *d= ev) { struct mlx5_lag *ldev; unsigned long flags; - bool res; + bool res =3D false; =20 spin_lock_irqsave(&lag_lock, flags); ldev =3D mlx5_lag_dev(dev); - res =3D ldev && test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &ldev->mode_flags= ); + if (ldev) { + res =3D test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, + &ldev->mode_flags); + if (__mlx5_lag_is_sd(ldev, dev) && !__mlx5_lag_is_active(ldev)) + res =3D __mlx5_lag_is_sd_active(ldev, dev); + } spin_unlock_irqrestore(&lag_lock, flags); =20 return res; @@ -2429,7 +2536,7 @@ struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(str= uct mlx5_core_dev *dev, int =20 if (*i =3D=3D MLX5_MAX_PORTS) goto unlock; - mlx5_ldev_for_each(idx, *i, ldev) { + mlx5_lag_for_each(idx, *i, ldev, mlx5_lag_get_filter(ldev, dev)) { pf =3D mlx5_lag_pf(ldev, idx); if (pf->dev !=3D dev) break; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index 70baa7997364..cbe201529661 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -148,6 +148,14 @@ mlx5_lag_pf_by_dev(struct mlx5_lag *ldev, struct mlx5_= core_dev *dev) return NULL; } =20 +static inline bool +__mlx5_lag_is_sd(struct mlx5_lag *ldev, struct mlx5_core_dev *dev) +{ + struct lag_func *pf =3D mlx5_lag_pf_by_dev(ldev, dev); + + return pf && pf->group_id !=3D 0; +} + static inline bool __mlx5_lag_is_active(struct mlx5_lag *ldev) { @@ -163,25 +171,31 @@ mlx5_lag_is_ready(struct mlx5_lag *ldev) #ifdef CONFIG_MLX5_ESWITCH int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, struct lag_tracker *tracker, - enum mlx5_lag_mode mode); -void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev); + enum mlx5_lag_mode mode, + u32 group_id); +void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev, u32 group_id); int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev); +void mlx5_lag_destroy_single_fdb(struct mlx5_lag *ldev); bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev); +bool mlx5_lag_shared_fdb_supported_filter(struct mlx5_lag *ldev, u32 filte= r); #else static inline int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, struct lag_tracker *tracker, - enum mlx5_lag_mode mode) + enum mlx5_lag_mode mode, + u32 group_id) { return -EOPNOTSUPP; } =20 -static inline void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev) {} +static inline void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev, + u32 group_id) {} =20 static inline int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) { return -EOPNOTSUPP; } =20 +static inline void mlx5_lag_destroy_single_fdb(struct mlx5_lag *ldev) {} static inline bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) { return false; @@ -211,11 +225,13 @@ void mlx5_ldev_add_debugfs(struct mlx5_core_dev *dev); void mlx5_ldev_remove_debugfs(struct dentry *dbg); void mlx5_disable_lag(struct mlx5_lag *ldev); void mlx5_lag_remove_devices(struct mlx5_lag *ldev); +void mlx5_lag_remove_devices_filter(struct mlx5_lag *ldev, u32 filter); int mlx5_deactivate_lag(struct mlx5_lag *ldev); void mlx5_lag_add_devices(struct mlx5_lag *ldev); void mlx5_lag_rescan_dev_locked(struct mlx5_lag *ldev, struct mlx5_core_dev *dev, bool enable); +void mlx5_lag_add_devices_filter(struct mlx5_lag *ldev, u32 filter); struct mlx5_devcom_comp_dev *mlx5_lag_get_devcom_comp(struct mlx5_lag *lde= v); =20 #ifdef CONFIG_MLX5_ESWITCH @@ -238,8 +254,8 @@ static inline bool mlx5_lag_is_supported(struct mlx5_co= re_dev *dev) } =20 /* Iterator filter constants for mlx5_lag_for_each() */ -#define MLX5_LAG_FILTER_ALL 0 /* iterate ALL devices */ -#define MLX5_LAG_FILTER_PORTS U32_MAX /* iterate ports only (XA_MARK_PORT= ) */ +#define MLX5_LAG_FILTER_PORTS 0 /* iterate ports only (XA_MARK_PORT= ) */ +#define MLX5_LAG_FILTER_ALL U32_MAX /* iterate ALL devices */ /* any other value =3D iterate devices with that specific group_id */ =20 #define mlx5_lag_for_each(i, start_index, ldev, filter) \ @@ -264,10 +280,12 @@ int mlx5_get_pre_lag_func(struct mlx5_lag *ldev, int = start_idx, int end_idx, u32 filter); int mlx5_get_next_lag_func(struct mlx5_lag *ldev, int start_idx, u32 filte= r); int mlx5_lag_get_dev_index_by_seq(struct mlx5_lag *ldev, int seq); +int mlx5_lag_get_dev_index_by_seq_filter(struct mlx5_lag *ldev, int seq, + u32 filter); int mlx5_lag_num_devs(struct mlx5_lag *ldev); int mlx5_lag_num_netdevs(struct mlx5_lag *ldev); int mlx5_lag_reload_ib_reps_from_locked(struct mlx5_lag *ldev, u32 flags, - bool cont_on_fail); + u32 filter, bool cont_on_fail); int mlx5_ldev_add_mdev(struct mlx5_lag *ldev, struct mlx5_core_dev *dev, u32 group_id); void mlx5_ldev_remove_mdev(struct mlx5_lag *ldev, struct mlx5_core_dev *de= v); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/= net/ethernet/mellanox/mlx5/core/lag/mpesw.c index 64e2d1dd5308..2cb44084e239 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -85,14 +85,15 @@ static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) !MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table) || !MLX5_CAP_GEN(dev0, create_lag_when_not_master_up) || !mlx5_lag_check_prereq(ldev) || - !mlx5_lag_shared_fdb_supported(ldev)) + !mlx5_lag_shared_fdb_supported_filter(ldev, MLX5_LAG_FILTER_ALL)) return -EOPNOTSUPP; =20 err =3D mlx5_mpesw_metadata_set(ldev); if (err) return err; =20 - err =3D mlx5_lag_shared_fdb_create(ldev, NULL, MLX5_LAG_MODE_MPESW); + err =3D mlx5_lag_shared_fdb_create(ldev, NULL, MLX5_LAG_MODE_MPESW, + MLX5_LAG_FILTER_ALL); if (err) { mlx5_core_warn(dev0, "Failed to create LAG in MPESW mode (%d)\n", err); mlx5_mpesw_metadata_cleanup(ldev); @@ -106,7 +107,7 @@ void mlx5_lag_disable_mpesw(struct mlx5_lag *ldev) { if (ldev->mode =3D=3D MLX5_LAG_MODE_MPESW) { mlx5_mpesw_metadata_cleanup(ldev); - mlx5_lag_shared_fdb_destroy(ldev); + mlx5_lag_shared_fdb_destroy(ldev, MLX5_LAG_FILTER_ALL); } } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/dri= vers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c index b5cbe3409720..74d17664f54c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c @@ -8,19 +8,19 @@ #include "lag.h" #include "eswitch.h" =20 -bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) +bool mlx5_lag_shared_fdb_supported_filter(struct mlx5_lag *ldev, u32 filte= r) { + int idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); struct mlx5_core_dev *dev0, *dev; bool ret =3D false; - int idx; int i; =20 - idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); if (idx < 0) return false; =20 dev0 =3D mlx5_lag_pf(ldev, idx)->dev; - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, filter) { if (i =3D=3D idx) continue; dev =3D mlx5_lag_pf(ldev, i)->dev; @@ -42,9 +42,16 @@ bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) return ret; } =20 -int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) +bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) { - int master_idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); + return mlx5_lag_shared_fdb_supported_filter(ldev, + MLX5_LAG_FILTER_PORTS); +} + +static int mlx5_lag_create_single_fdb_filter(struct mlx5_lag *ldev, u32 fi= lter) +{ + int master_idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); struct mlx5_eswitch *master_esw; struct mlx5_core_dev *dev0; int i, j; @@ -55,7 +62,7 @@ int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) =20 dev0 =3D mlx5_lag_pf(ldev, master_idx)->dev; master_esw =3D dev0->priv.eswitch; - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, filter) { struct mlx5_eswitch *slave_esw; =20 if (i =3D=3D master_idx) @@ -71,7 +78,7 @@ int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) } return 0; err: - mlx5_ldev_for_each_reverse(j, i, 0, ldev) { + mlx5_lag_for_each_reverse(j, i, 0, ldev, filter) { struct mlx5_eswitch *slave_esw; =20 if (j =3D=3D master_idx) @@ -82,59 +89,145 @@ int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) return err; } =20 +static void mlx5_lag_destroy_single_fdb_filter(struct mlx5_lag *ldev, + u32 filter) +{ + int master_idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); + struct mlx5_eswitch *master_esw; + struct mlx5_eswitch *peer_esw; + int i; + + if (master_idx < 0) + return; + + master_esw =3D mlx5_lag_pf(ldev, master_idx)->dev->priv.eswitch; + mlx5_lag_for_each(i, 0, ldev, filter) { + if (i =3D=3D master_idx) + continue; + + peer_esw =3D mlx5_lag_pf(ldev, i)->dev->priv.eswitch; + mlx5_eswitch_offloads_single_fdb_del_one(master_esw, peer_esw); + } +} + +int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) +{ + return mlx5_lag_create_single_fdb_filter(ldev, MLX5_LAG_FILTER_ALL); +} + +void mlx5_lag_destroy_single_fdb(struct mlx5_lag *ldev) +{ + mlx5_lag_destroy_single_fdb_filter(ldev, MLX5_LAG_FILTER_ALL); +} + +/** + * mlx5_lag_shared_fdb_create - Create shared FDB LAG + * @ldev: LAG device + * @tracker: LAG tracker (NULL for SD) + * @mode: LAG mode (unused for SD) + * @group_id: SD group ID; 0 (MLX5_LAG_FILTER_PORTS) for ports LAG; + * MLX5_LAG_FILTER_ALL for all-device (mpesw) LAG + * + * When group_id is 0 (MLX5_LAG_FILTER_PORTS) or MLX5_LAG_FILTER_ALL, + * activates a FW LAG with shared FDB. + * When group_id is a specific SD group ID, creates a software-only shared + * FDB scoped to that group (no FW LAG commands). + */ int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, struct lag_tracker *tracker, - enum mlx5_lag_mode mode) + enum mlx5_lag_mode mode, + u32 group_id) { - int idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); + u32 filter =3D group_id ? group_id : MLX5_LAG_FILTER_PORTS; + int idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); struct mlx5_core_dev *dev0; + struct lag_func *pf; int err; + int i; =20 if (idx < 0) return -EINVAL; =20 dev0 =3D mlx5_lag_pf(ldev, idx)->dev; =20 - mlx5_lag_remove_devices(ldev); - - err =3D mlx5_activate_lag(ldev, tracker, mode, true); - if (err) { - mlx5_core_warn(dev0, "Failed to create LAG in shared FDB mode (%d)\n", - err); - goto err_add_devices; + mlx5_lag_remove_devices_filter(ldev, filter); + + if (filter =3D=3D MLX5_LAG_FILTER_PORTS || filter =3D=3D MLX5_LAG_FILTER_= ALL) { + err =3D mlx5_activate_lag(ldev, tracker, mode, true); + if (err) { + mlx5_core_warn(dev0, + "Failed to create LAG in shared FDB mode (%d)\n", + err); + goto err_add_devices; + } + } else { + err =3D mlx5_lag_create_single_fdb_filter(ldev, group_id); + if (err) { + mlx5_core_warn(dev0, + "Failed to create SD shared FDB (%d)\n", + err); + goto err_add_devices; + } + mlx5_lag_for_each(i, 0, ldev, filter) { + pf =3D mlx5_lag_pf(ldev, i); + pf->sd_fdb_active =3D true; + } + BLOCKING_INIT_NOTIFIER_HEAD(&dev0->priv.lag_nh); } =20 mlx5_lag_rescan_dev_locked(ldev, dev0, true); - err =3D mlx5_lag_reload_ib_reps_from_locked(ldev, 0, false); + err =3D mlx5_lag_reload_ib_reps_from_locked(ldev, 0, filter, false); if (err) { mlx5_core_err(dev0, "Failed to enable lag\n"); goto err_rescan_drivers; } =20 - mlx5_lag_set_vports_agg_speed(ldev); + if (filter =3D=3D MLX5_LAG_FILTER_PORTS || filter =3D=3D MLX5_LAG_FILTER_= ALL) + mlx5_lag_set_vports_agg_speed(ldev); return 0; =20 err_rescan_drivers: mlx5_lag_rescan_dev_locked(ldev, dev0, false); - mlx5_deactivate_lag(ldev); + if (filter =3D=3D MLX5_LAG_FILTER_PORTS || filter =3D=3D MLX5_LAG_FILTER_= ALL) { + mlx5_deactivate_lag(ldev); + } else { + mlx5_lag_for_each(i, 0, ldev, filter) { + pf =3D mlx5_lag_pf(ldev, i); + pf->sd_fdb_active =3D false; + } + mlx5_lag_destroy_single_fdb_filter(ldev, group_id); + } err_add_devices: - mlx5_lag_add_devices(ldev); - mlx5_lag_reload_ib_reps_from_locked(ldev, 0, true); + mlx5_lag_add_devices_filter(ldev, filter); + mlx5_lag_reload_ib_reps_from_locked(ldev, 0, filter, true); return err; } =20 -void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev) +void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev, u32 group_id) { + u32 filter =3D group_id ? group_id : MLX5_LAG_FILTER_PORTS; + struct lag_func *pf; int err; + int i; =20 - mlx5_lag_remove_devices(ldev); + mlx5_lag_remove_devices_filter(ldev, filter); =20 - err =3D mlx5_deactivate_lag(ldev); - if (err) - return; + if (filter =3D=3D MLX5_LAG_FILTER_PORTS || filter =3D=3D MLX5_LAG_FILTER_= ALL) { + err =3D mlx5_deactivate_lag(ldev); + if (err) + return; + } else { + mlx5_lag_for_each(i, 0, ldev, filter) { + pf =3D mlx5_lag_pf(ldev, i); + pf->sd_fdb_active =3D false; + } + mlx5_lag_destroy_single_fdb_filter(ldev, group_id); + } =20 - mlx5_lag_add_devices(ldev); + mlx5_lag_add_devices_filter(ldev, filter); mlx5_lag_reload_ib_reps_from_locked(ldev, MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV, - true); + filter, true); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index 6e199161b008..bbd77ae11e84 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -57,6 +57,16 @@ static struct mlx5_core_dev *mlx5_sd_get_primary(struct = mlx5_core_dev *dev) return sd->primary ? dev : sd->primary_dev; } =20 +struct mlx5_devcom_comp_dev *mlx5_sd_get_devcom(struct mlx5_core_dev *dev) +{ + struct mlx5_sd *sd =3D mlx5_get_sd(dev); + + if (!sd) + return NULL; + + return sd->devcom; +} + struct mlx5_core_dev * mlx5_sd_primary_get_peer(struct mlx5_core_dev *primary, int idx) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.h index 9bfd5b9756b5..2ab259095d7e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h @@ -21,6 +21,16 @@ void mlx5_sd_put_adev(struct auxiliary_device *actual_ad= ev, int mlx5_sd_init(struct mlx5_core_dev *dev); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 07/13] net/mlx5: SD, introduce Socket Direct LAG Date: Wed, 27 May 2026 15:54:21 +0300 Message-ID: <20260527125427.385976-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E60:EE_|LV8PR12MB9665:EE_ X-MS-Office365-Filtering-Correlation-Id: b1742eb9-0c35-4e12-5c4e-08debbef5030 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700016|1800799024|82310400026|11063799006|22082099003|18002099003|56012099006; X-Microsoft-Antispam-Message-Info: 6VsoD6sz82hajTOs/9G8tuax3hhuR8H7FYMhdPRLp4VIovJRYPKnw8AKay5/zR9DMsdTTpYbr/w/frWg6RGZz54Wvg9ZvAxK44iC1UfEyQ2J0Wl0eGKlaLDxKm2EwerOO/Hv9uMN72GzA2PLzW5/iYD9s8aVsbYc9ndReZ6nB2h7JRUyvhZ8cyJBKitVqHlPw9oJaQmd2WwLs+K3S27ose8Ki2gJBnnrV7KK8cw0qezLw98IPYan0AV7Q1o0/7yyvvuz105VBBxyGKygJ1q2DwHCZMWAyI0/YVnBtTVxynybyAaJK8awdolHcZkdnB91SK+m3LbVL4OxMxjbHcOvx8JFwSqA+tFLjXuNB+eMdBFk35F1xPa8Q1Uj9/PcfvNCywD0TCtFj0uwESCqB+Dk9sjX0Xk65LkCeK9M4L2N5K2hHDmYR/RmVSz3IwTtxllk2ji0kMR5Lj0Q3lcKubXZhN2xT64H2Wop1ejckW/6UHlezAAnm65zr0/yAEzoCdjvEJ8+NPwrjdbPqA/UIhduk7ivTEnLRriOHeLT5WnO5dObVyOfhzr408Q8ieSqCSzRvVLDW6bxoAdOc9Vpb3+ZzjerZ4OubkR4TCdH3bjhCLqCaGo9kaOixsj7NjHiHSH698/hacw3GAk2dTKP6exU0vqMIEHnF/gO3BcUPzpNjvusQnq/sGqNt2aSJLtoNDc2ATr+aJymMi6eDgie82O0N0Cjm3HQHtuN8cgadPvjnos= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700016)(1800799024)(82310400026)(11063799006)(22082099003)(18002099003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Q0TdYtol8VF6rQ99XOl0S4tLE451hjfDRKLJJnVNSgjAW+3+gwWADFCysZeTaAXTX00VGTmiM6cC/JIBEBYgQwzOkITXKf7+8Rnvo9lGx9cQPitPPSV/Ry9JTJIpuqqapnrk2wP6c7E9/T6+GV2CsbJy+0cr/vDBM2L82o2pCPLrtCLK8f5kvX3B4kQxWht5wmLQRamsHnHZxVCNjJwo+AxLtemzeroBXG5OeLZSell7CTJcOzQqb0sDtAvcE8dC3aLN6VEEJUGkqEBKum4g+71X8aV9L7nNhXatNv9Hjz4nGuUgq/ZZhXD38ljv5MjcuV6Zozs0RprUarP6tQQV4IkMqI2yO0HlVMg/XtlVqjaqdS6vjDowXWk8yNX5XWWezTBm9Ko5An0w9Uu41gnaRe6Q6tkfqLe++i4SSNEMWsk6uDqNPk1pTcGs4CFTNq0H X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:56:04.9183 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1742eb9-0c35-4e12-5c4e-08debbef5030 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E60.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9665 Content-Type: text/plain; charset="utf-8" From: Shay Drory Register SD secondary devices with the existing LAG structure by adding them to the primary's ldev xarray with a shared group_id. This ties the SD LAG lifecycle to the SD group lifecycle. Add sd_lag_state debugfs entry for LAG state visibility. To avoid race between this entry and LAG deletion, have debugfs creation and deletion done last on SD init and first on SD cleanup. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 135 ++++++++++++++++-- 1 file changed, 121 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index bbd77ae11e84..e341d814873a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -2,6 +2,7 @@ /* Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserve= d. */ =20 #include "lib/sd.h" +#include "../lag/lag.h" #include "mlx5_core.h" #include "lib/mlx5.h" #include "fs_cmd.h" @@ -223,6 +224,108 @@ static void sd_cleanup(struct mlx5_core_dev *dev) kfree(sd); } =20 +static int sd_lag_state_show(struct seq_file *file, void *priv) +{ + struct mlx5_core_dev *dev =3D file->private; + struct mlx5_lag *ldev; + struct lag_func *pf; + bool active =3D false; + int i; + + ldev =3D mlx5_lag_dev(dev); + if (!ldev) + return -EINVAL; + + mutex_lock(&ldev->lock); + mlx5_ldev_for_each(i, 0, ldev) { + pf =3D mlx5_lag_pf(ldev, i); + if (pf->dev =3D=3D dev) { + active =3D pf->sd_fdb_active; + break; + } + } + mutex_unlock(&ldev->lock); + + seq_printf(file, "%s\n", active ? "active" : "disabled"); + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(sd_lag_state); + +/* SD LAG integration is optional. If LAG isn't available on this device + * (e.g. lag caps are off), or registering secondaries fails, just warn + * and continue - SD can operate without the LAG-side bookkeeping. + */ +static void sd_lag_init(struct mlx5_core_dev *dev) +{ + struct mlx5_core_dev *primary =3D mlx5_sd_get_primary(dev); + struct mlx5_sd *sd =3D mlx5_get_sd(primary); + struct mlx5_core_dev *pos, *to; + struct mlx5_lag *ldev; + struct lag_func *pf; + int err; + int i; + + ldev =3D mlx5_lag_dev(primary); + if (!ldev) { + sd_warn(primary, "%s: no ldev (LAG caps off?), skipping\n", + __func__); + return; + } + + mutex_lock(&ldev->lock); + pf =3D mlx5_lag_pf_by_dev(ldev, primary); + if (!pf) { + sd_warn(primary, "%s: primary not registered in ldev, skipping\n", + __func__); + goto out; + } + + pf->group_id =3D sd->group_id; + + mlx5_sd_for_each_secondary(i, primary, pos) { + err =3D mlx5_ldev_add_mdev(ldev, pos, sd->group_id); + if (err) { + sd_warn(primary, "%s: failed to add secondary %s to ldev: %d\n", + __func__, dev_name(pos->device), err); + goto err; + } + } + +out: + mutex_unlock(&ldev->lock); + return; + +err: + to =3D pos; + mlx5_sd_for_each_secondary_to(i, primary, to, pos) + mlx5_ldev_remove_mdev(ldev, pos); + pf->group_id =3D 0; + mutex_unlock(&ldev->lock); +} + +static void sd_lag_cleanup(struct mlx5_core_dev *dev) +{ + struct mlx5_core_dev *primary =3D mlx5_sd_get_primary(dev); + struct mlx5_core_dev *pos; + struct mlx5_lag *ldev; + struct lag_func *pf; + int i; + + ldev =3D mlx5_lag_dev(primary); + if (!ldev) + return; + + mutex_lock(&ldev->lock); + mlx5_sd_for_each_secondary(i, primary, pos) + mlx5_ldev_remove_mdev(ldev, pos); + + pf =3D mlx5_lag_pf_by_dev(ldev, primary); + if (pf) + pf->group_id =3D 0; + mutex_unlock(&ldev->lock); +} + static int sd_register(struct mlx5_core_dev *dev) { struct mlx5_devcom_comp_dev *devcom, *pos; @@ -473,27 +576,32 @@ int mlx5_sd_init(struct mlx5_core_dev *dev) if (err) goto err_sd_unregister; =20 + mlx5_sd_for_each_secondary(i, primary, pos) { + err =3D sd_cmd_set_secondary(pos, primary, alias_key); + if (err) + goto err_unset_secondaries; + } + + sd_lag_init(primary); + primary_sd->dfs =3D debugfs_create_dir("multi-pf", mlx5_debugfs_get_dev_root(primary)); - debugfs_create_x32("group_id", 0400, primary_sd->dfs, - &primary_sd->group_id); - debugfs_create_file("primary", 0400, primary_sd->dfs, primary, - &dev_fops); - mlx5_sd_for_each_secondary(i, primary, pos) { char name[32]; =20 - err =3D sd_cmd_set_secondary(pos, primary, alias_key); - if (err) - goto err_unset_secondaries; - snprintf(name, sizeof(name), "secondary_%d", i - 1); debugfs_create_file(name, 0400, primary_sd->dfs, pos, &dev_fops); - } =20 + debugfs_create_file("sd_lag_state", 0400, primary_sd->dfs, primary, + &sd_lag_state_fops); + debugfs_create_x32("group_id", 0400, primary_sd->dfs, + &primary_sd->group_id); + debugfs_create_file("primary", 0400, primary_sd->dfs, primary, + &dev_fops); + sd_info(primary, "group id %#x, size %d, combined\n", sd->group_id, mlx5_devcom_comp_get_size(sd->devcom)); sd_print_group(primary); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 08/13] net/mlx5: LAG, block RoCE and VF LAG for SD devices Date: Wed, 27 May 2026 15:54:22 +0300 Message-ID: <20260527125427.385976-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E62:EE_|MN0PR12MB6247:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b516d7e-bd34-4d04-c99c-08debbef52be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700016|82310400026|6133799003|11063799006|5023799004|3023799007|22082099003|18002099003|56012099006; X-Microsoft-Antispam-Message-Info: WLU3k4EY2wUwhxv6DxKFJlfFLuGg5sBi7mPVn6FxFMiORD/CL4xbqf/9QH+osyFADVhYqZOpBJ5xZaL8AP3kqoi3LLzBIEwwdMI8m2glJfp9NG0Eg0P6Lf2roWJy1288YSyiGNYXCijuVvehgp9/6tZJN6TMbVhNUe/vekfRLCu5+StDtJL0sjWxpiSw6uL88gISlnufnf3YyM62EB/M0KSZezt8dVGGuhdc+4JzgkQHn+QFH2ibsgoJ3QYXUV/ivagIyE2d34TcioHCJJdsGl909WgZ+fz+fcgNH7GnD76MHgLq6OLkPIrulrGUOVs91eMbT9JrOA0bAt8XYTWSNGNBrmRS2szPWzmgxw7rbvyuRxCs40B8FrKvZysB12Emh34GjYQMhgbc6rQOnULLMI+l/4D3J0hsty7x/bdOMFXAdNK2ctAbN/3ChFa9E9jAiGXio71N7paooUu006GpOt5JEBjVWTxeRAVXvrbf4ERet/3Y4oM+eLTjyEMnMmfazDN3/Oi52whSrF1F+VViWT9BL2PjutPzMCo2MaH+RQYmmfiKiIzAyWlAuedVH7dIcE6ypIBy2HOX85zh0Y+6QwIgb14ObMluxfvfdbMmbzuYokcFnTAFGff8kdvYM4yenlQqAdoGGPrKzbZpYNqN3jSpdyCO1Qolc9ngM3qj7Jd6O7Rzxp1cT/torQy2aDd4WUDxaYMsn3ciANmkLOh2Zz61oNkGXZ1Wmn3WMYmJviY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700016)(82310400026)(6133799003)(11063799006)(5023799004)(3023799007)(22082099003)(18002099003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2pFPkEUk5Gii3XVGem80AoY1+6wlhLmyyr1uTwfDFHQTiPIQVjUK3ZDhE87JrtAFrrZscb9oXSUhsVZdywDyQ84HCApq8Z0yc7z2jqWHvQGQ9xHGE0bj2LBawDwvcM3ObA8Uq7yW5vbgp6r0jiAihj+7sN02pU6HMruFqCeWqGpiFiWezj63eAxXuTXbAqY1Yxh3KdeHRUXF5NixgSZN/GlT2Hiv5Rv0YU9kFLJhvF07+2b3B+SjCGvpQd5CGzi2zFrjvZItlNw9yp+QTh4bDge/bQTQeK5VFbC5IX9R4MSwB5NhrON/6QCwr0r8rKyG/a6/a/2UviKxfltScE00Kn9ho5MLbY3i4B9oWYdQxkpdU2mXtDTn7WZfjY/K/Tgf0esmaw2SCu3m9oPubLnnAPofwFEjGYC1Vfmzs5uFF4MmtMVaFyo6rjS2Uzw7Fjpc X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:56:09.2011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b516d7e-bd34-4d04-c99c-08debbef52be X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E62.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6247 Content-Type: text/plain; charset="utf-8" From: Shay Drory Socket Direct devices manage their own LAG via SD LAG infrastructure. Block the standard netdev-event-driven LAG path (RoCE LAG and VF LAG) for SD devices to prevent conflicting LAG configurations. Expose mlx5_sd_is_supported() as a public helper that encapsulates all SD eligibility checks. Use it in mlx5_lag_dev_alloc() to skip netdev notifier registration for SD-capable devices at alloc time. Some sd code is reordered to expose the new function, no logic is changed. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 13 ++-- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 60 ++++++++++++++----- .../net/ethernet/mellanox/mlx5/core/lib/sd.h | 11 ++++ 3 files changed, 63 insertions(+), 21 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 3decb49e9f19..a2c7e2927431 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -293,11 +293,14 @@ static struct mlx5_lag *mlx5_lag_dev_alloc(struct mlx= 5_core_dev *dev) INIT_DELAYED_WORK(&ldev->bond_work, mlx5_do_bond_work); INIT_WORK(&ldev->speed_update_work, mlx5_mpesw_speed_update_work); =20 - ldev->nb.notifier_call =3D mlx5_lag_netdev_event; - write_pnet(&ldev->net, mlx5_core_net(dev)); - if (register_netdevice_notifier_net(read_pnet(&ldev->net), &ldev->nb)) { - ldev->nb.notifier_call =3D NULL; - mlx5_core_err(dev, "Failed to register LAG netdev notifier\n"); + if (!mlx5_sd_is_supported(dev)) { + ldev->nb.notifier_call =3D mlx5_lag_netdev_event; + write_pnet(&ldev->net, mlx5_core_net(dev)); + if (register_netdevice_notifier_net(read_pnet(&ldev->net), + &ldev->nb)) { + ldev->nb.notifier_call =3D NULL; + mlx5_core_err(dev, "Failed to register LAG netdev notifier\n"); + } } ldev->mode =3D MLX5_LAG_MODE_NONE; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index e341d814873a..8991db3a19cf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -115,7 +115,28 @@ static bool ft_create_alias_supported(struct mlx5_core= _dev *dev) return true; } =20 -static bool mlx5_sd_is_supported(struct mlx5_core_dev *dev, u8 host_buses) +static int mlx5_query_sd(struct mlx5_core_dev *dev, bool *sdm, + u8 *host_buses) +{ + u32 out[MLX5_ST_SZ_DW(mpir_reg)]; + int err; + + err =3D mlx5_query_mpir_reg(dev, out); + if (err) + return err; + + *sdm =3D MLX5_GET(mpir_reg, out, sdm); + *host_buses =3D MLX5_GET(mpir_reg, out, host_buses); + + return 0; +} + +static u32 mlx5_sd_group_id(struct mlx5_core_dev *dev, u8 sd_group) +{ + return (u32)((MLX5_CAP_GEN(dev, native_port_num) << 8) | sd_group); +} + +static bool mlx5_sd_caps_supported(struct mlx5_core_dev *dev, u8 host_buse= s) { /* Honor the SW implementation limit */ if (host_buses > MLX5_SD_MAX_GROUP_SZ) @@ -142,25 +163,32 @@ static bool mlx5_sd_is_supported(struct mlx5_core_dev= *dev, u8 host_buses) return true; } =20 -static int mlx5_query_sd(struct mlx5_core_dev *dev, bool *sdm, - u8 *host_buses) +bool mlx5_sd_is_supported(struct mlx5_core_dev *dev) { - u32 out[MLX5_ST_SZ_DW(mpir_reg)]; + u8 host_buses, sd_group; + bool sdm; int err; =20 - err =3D mlx5_query_mpir_reg(dev, out); - if (err) - return err; + /* Feature is currently implemented for PFs only */ + if (!mlx5_core_is_pf(dev)) + return false; =20 - *sdm =3D MLX5_GET(mpir_reg, out, sdm); - *host_buses =3D MLX5_GET(mpir_reg, out, host_buses); + /* Block on embedded CPU PFs */ + if (mlx5_core_is_ecpf(dev)) + return false; =20 - return 0; -} + err =3D mlx5_query_nic_vport_sd_group(dev, &sd_group); + if (err || !sd_group) + return false; =20 -static u32 mlx5_sd_group_id(struct mlx5_core_dev *dev, u8 sd_group) -{ - return (u32)((MLX5_CAP_GEN(dev, native_port_num) << 8) | sd_group); + if (!MLX5_CAP_MCAM_REG(dev, mpir)) + return false; + + err =3D mlx5_query_sd(dev, &sdm, &host_buses); + if (err || !sdm) + return false; + + return mlx5_sd_caps_supported(dev, host_buses); } =20 static int sd_init(struct mlx5_core_dev *dev) @@ -198,8 +226,8 @@ static int sd_init(struct mlx5_core_dev *dev) =20 group_id =3D mlx5_sd_group_id(dev, sd_group); =20 - if (!mlx5_sd_is_supported(dev, host_buses)) { - sd_warn(dev, "can't support requested netdev combining for group id 0x%x= ), skipping\n", + if (!mlx5_sd_caps_supported(dev, host_buses)) { + sd_warn(dev, "can't support requested netdev combining for group id 0x%x= , skipping\n", group_id); return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.h index 2ab259095d7e..bf59903ab23f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h @@ -4,6 +4,8 @@ #ifndef __MLX5_LIB_SD_H__ #define __MLX5_LIB_SD_H__ =20 +#include + #define MLX5_SD_MAX_GROUP_SZ 2 =20 struct mlx5_sd; @@ -18,6 +20,15 @@ struct auxiliary_device *mlx5_sd_get_adev(struct mlx5_co= re_dev *dev, void mlx5_sd_put_adev(struct auxiliary_device *actual_adev, struct auxiliary_device *adev); =20 +#ifdef CONFIG_MLX5_CORE_EN +bool mlx5_sd_is_supported(struct mlx5_core_dev *dev); +#else +static inline bool mlx5_sd_is_supported(struct mlx5_core_dev *dev) +{ + return false; +} +#endif + int mlx5_sd_init(struct mlx5_core_dev *dev); void mlx5_sd_cleanup(struct mlx5_core_dev *dev); =20 --=20 2.44.0 From nobody Mon Jun 8 18:55:59 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010007.outbound.protection.outlook.com [52.101.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3E6F40C5DA; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 09/13] net/mlx5: LAG, block multipath LAG for SD devices Date: Wed, 27 May 2026 15:54:23 +0300 Message-ID: <20260527125427.385976-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E63:EE_|IA1PR12MB8080:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ca3c54c-997c-4efb-76ee-08debbef5704 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|7416014|82310400026|56012099006|11063799006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: ojBC4H4M8DCccmGQuyWnqWEHBEZJS8IZotRfOiAgAdaGQ2o/kj/icjq/rZu1BKv3plPl82ZrGELu+0J+feEUzfdEiu7foewSQs95mEcAFkhfYPR1JnpMu9z1jjEyboinR/z7vQpeqvgGXKuRDM/PzXsKVsY7eIsMRgIzYClr4cYusdk6lG8GMrGr1zOLyKnXZCyzE+4jyDH0kYSv1iIg9xLmQpigiQeyk8fHuSPQAYBt9gTw7ASFe1A4zysOpJx5ryp6bXEH2zMu4G52fQLCveesLYyP0feIuxPYocsBnzhOkwiWaZcsLCdlDkAIW/A2DcILM0C4w/W1wAEuJNNXwd1S5r9EkNhq9yq7Ekn0tGfRnTiLuEk1ZEkmD2BApwUwBYM3Wi2HWrwXASH3iCGcvWCpAHyM6xlgMzXHxlrn5rVfSru2RT3hhGQQu5+j4y3+wqKtf+mBY7JR9W7B8wfu6pzPF46OgATSmQSz4Vyt3ImjZ5LJWJ/9ZhBHZn4jKPzLPP2hpE3l2IiSuMyxj83via8fHNKYZIOn2UouRZPJXGDp5eEPBxjZgxxoVcskfOrIZfr+y4t7UUJB0M4jPybJISlWH8PBBZqX4jouiVep2GwBXH2p7Vnvm2OXZoAFgMVfjQFno01RbmfQfgEIJtB8dMM6xsqs8hnHOKUS1Z63srq264yOp6Z6+eYL9ZNialxJTpBq1CBKylcR9hklrsMyI+D/kbVoqAzwd3sv4RlWq7E= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(7416014)(82310400026)(56012099006)(11063799006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SzOuJpNMFE+4fALt2PqwNObxb66uUSjU1wBaUN5ejOqpq2dE0bsOrbozLfHyi8BLMe/sfVjINujCOtHoP6/wwNwbA8b2JDJXLzY5af4kqRh3n3GZTwL9H+0xkFawsWuTNhJbBqZNIg6NKe5KMuOycKMYfrnFL16EtlQq6RHIKEjOG5pgSIwLNdzHI4uZw9LMDfvOT0AW8iJA5o0hcvl6FHsI/CUSGUwAZbpYV3aE4U0RyYYUaJVMX/C72Azv83AbXhasiVRJu106KMn5vej4wcmfz791VZUPJxhR1hYM1U93mkDLl8uNoVhRVSCja2PXknYypV6w8A9SaWkDH4UdhfChR9GfWywkS5DD4dpPtyF1zOpSRKRJlOoEtICePOvgkYJY+cK8k9nCts9ULOkRIEqRXYzKVebqazM6r8rz7HwQrWbGfhnQEC8qgQEl7VYC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:56:16.3680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ca3c54c-997c-4efb-76ee-08debbef5704 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E63.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8080 Content-Type: text/plain; charset="utf-8" From: Shay Drory SD devices are not compatible with multipath LAG since they use dedicated SD LAG for cross-socket connectivity. Add an SD check to the multipath prereq validation to prevent multipath LAG activation on SD-configured ports. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c b/drivers/net= /ethernet/mellanox/mlx5/core/lag/mp.c index f42e051fa7e7..65c76bd748c6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mp.c @@ -26,6 +26,10 @@ static bool mlx5_lag_multipath_check_prereq(struct mlx5_= lag *ldev) if (__mlx5_lag_is_active(ldev) && !__mlx5_lag_is_multipath(ldev)) return false; =20 + if (__mlx5_lag_is_sd(ldev, mlx5_lag_pf(ldev, idx0)->dev) || + __mlx5_lag_is_sd(ldev, mlx5_lag_pf(ldev, idx1)->dev)) + return false; + if (ldev->ports > MLX5_LAG_MULTIPATH_OFFLOADS_SUPPORTED_PORTS) return false; =20 --=20 2.44.0 From nobody Mon Jun 8 18:55:59 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011057.outbound.protection.outlook.com [40.93.194.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1CB840F8C6; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 10/13] net/mlx5: SD, keep netdev resources on same PF in switchdev mode Date: Wed, 27 May 2026 15:54:24 +0300 Message-ID: <20260527125427.385976-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB71:EE_|SN7PR12MB8148:EE_ X-MS-Office365-Filtering-Correlation-Id: d648af9b-302b-432c-d90c-08debbef591a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|82310400026|1800799024|11063799006|18002099003|22082099003|56012099006; X-Microsoft-Antispam-Message-Info: n8cGs1Pre3SnaEVbcwh7H6aVqZppEC7vU/Uye67zpPHkVLtoabeOBLCJCHrHYHL4rN+UTVtl7V0deuSyRqX2xOju7fSISC6JOtyE1/7xyIvANG9o2/0GQzsxqWFUrbnxrLwYnhhgE43b5h5/jBfKjT1CxE4rQSPUQYTPR1ud1Xp7F5Vtx2o7QIUJ+V0R4IkHoU8KQsqy54xRbjxW+/6CCLc4p1l+yyAKLCBVxN5rHihIjHjOX1cbIHergH1GWeMEpL0+ASTAc4eV/HNmaU/p37DO48UsKkzpBTiUtqAiwwJRPJw6PPeGQOqfYBR/ZkejzBGEw3sRjWtYqifKHb6OsYT/5YEEmTuj+urdbfxSyNfJfDDE3B1dhfzeMWCUu4pKopETPE6su5++1b8VBziw3Dz8lTsxGsZXE4VGdb7PiPD56KfT5KOjYheN2OB1ssjkfMQKxSP9iMhvC0BuuzB92M/Nb9FVqmkxjGGWvUHtts14CgCYxwAc3voNEaDtSZpC2ZRRIX0ppEo4wPEPjLq3OxBfGdTqmEAz4EsJxrKtupzuskY1rD75Yp6xnCo1wvKXC6n/5Ijv2E8MiJLw/3x9b612a88Z/hrElACZUnlJEWrngzQW/83h8ag2TJEiH5aRfyBI+X8lI1Q+ivHVzAcB4UTj3dcszGqjgMEiNWLmtyJsUs99X6X6qogPObyUuLKEBfI8iNprLy3vv29kSTcoO8yCCWTFs3CVeX+8fTDT+EM= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(82310400026)(1800799024)(11063799006)(18002099003)(22082099003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BImaJqjo8kMR0EnBGUQhrLhac3zYM3eYjkXpbqTaOu3kY/tW8pCYZ+f+zPTt5jhsxXO9AmZ8s7lQ9eA6PQ40gaqk9dIkXguPn6taYIZYnyWlELhAVEkPcCLfgVon4RhmMREOaFAWHYg1Rhh1Aeyo55VJt5Ida+WNKr5BtzOH+bzOKWNOC9nNpekduSQEOxsyTc9u27BXNQtpRJ0VfDI51FUFNUB8/71e344SzX+47ZIq7W2BLYPoXwaJBsEnCv2AFn4omFf/sf3ZlirL+0+gQNUUE8uKD/nCT9d4JgPtXxveo2g68f8RublebCfMGpQPfgdJnA5n+Q81F1jku3iJ4X8IrftRdFUAYeUcMhS9T5PmAjrlUiTPGIM1qeDrNMHqpqb/Nh/s7M8QTHx196BKTjrxEAa1dWdghQbWN75BQI9JugXOy6BU/25lVVhZ0xdb X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:56:19.7791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d648af9b-302b-432c-d90c-08debbef591a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB71.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8148 Content-Type: text/plain; charset="utf-8" From: Shay Drory In SD switchdev mode, network device resources such as channels and completion vectors must remain on the same PF rather than being distributed across SD group members. Modify mlx5_sd_ch_ix_get_dev_ix() to return 0 and mlx5_sd_ch_ix_get_vec_ix() to return the channel index directly when in switchdev mode, keeping resources local to the requesting PF. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index 8991db3a19cf..ec606851feb8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -6,6 +6,7 @@ #include "mlx5_core.h" #include "lib/mlx5.h" #include "fs_cmd.h" +#include #include #include =20 @@ -85,11 +86,17 @@ mlx5_sd_primary_get_peer(struct mlx5_core_dev *primary,= int idx) =20 int mlx5_sd_ch_ix_get_dev_ix(struct mlx5_core_dev *dev, int ch_ix) { + if (is_mdev_switchdev_mode(dev)) + return 0; + return ch_ix % mlx5_sd_get_host_buses(dev); } =20 int mlx5_sd_ch_ix_get_vec_ix(struct mlx5_core_dev *dev, int ch_ix) { + if (is_mdev_switchdev_mode(dev)) + return ch_ix; + return ch_ix / mlx5_sd_get_host_buses(dev); } =20 --=20 2.44.0 From nobody Mon Jun 8 18:55:59 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011025.outbound.protection.outlook.com [52.101.57.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB4CC407CC5; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 11/13] net/mlx5e: TC, track peer flow slots with bitmap Date: Wed, 27 May 2026 15:54:25 +0300 Message-ID: <20260527125427.385976-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E60:EE_|IA1PR12MB9522:EE_ X-MS-Office365-Filtering-Correlation-Id: 63b4ea75-52b1-4ad8-4817-08debbef5fe9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|7416014|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: 9hjE5Fq+1qMV5qEY9Qvc5Sv6VuHVY1dvtTbHhuKw0Wfj7kTu6ZXynOWtsf1PDpl4ZUWvyfvJb2+HBnHOXkInddlFie1MKWKS1xjFmZkvRt03EUNDXNyoTlY0e2aGuPUVIrWiL7mla+ISZVBMORIqqJPwxGB00JHkwgq4+eXdrymSkNC7I1gjfuU2pPdOTWf/J/Gmi7GhFylwrtPhM7cW/0yzpDjndPvdrt27xxfwQ51ddN0A/oFDtNFZnwe4ONccEU3bsMrVGZXgLAyw9r0S/OG8RiRRiq9VNSlhYlKQV8nsn6PdmQgbU2ZoDnk2B3dBKG0PXVgbUrc8awUJCxnjVeTBo5miJvhEygfruKEjv3600gluYjdjy7iA//pWJw+SyTHVJzEAg5z4d0UnA021aDtoM1NAWYtHp1YIZlL5aP2iaqoYOHp8qC6FD2srNRGwXhodAtCY9HpgqT2PXUcaNmle1g5Q4ehV0/tew/oOo+JPHX770SG7pB2hnoY//Aj8fuPMFfqCpK6FBsCi3AfU/dl4zXRzomA4lYdsRx0amXkg+yaj/bSOTDsP0BvtK+/spvsZvesA4I/kk6iBpcQR1LHLfggBLQFrJHPuQ4U0Mx3KCSp6jzbL1vz2xhx0jxEkpK4I5/HiU7UxHeFqCLqNzxC4OmUdOaN0C8q0gx3ahrBJv1IslDDlEa+c02EhZBhPlER52BWXllgClzN2iyfLVUVs+NgHq9t2CoGJAnJGgZE= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(7416014)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nH7tGnwjyExo7U4UzBhPccvVFRBD9VNHxFuE4PucuixT7gvH3lZ0ZcUu6y+H90krcQjQ1xnhGjyFofzAOghsBts9nAMJ0DWsyEdOzlnMrohhUmSXBWr7cgBz7wyVVtBwDKCRdK6QQLFMPzSuinox7y7/6TpykuRwQr1lweeNOmsXGz9knKsRW3ASXywH5HRZNDCm8q3YfH1/PNvUO8Cyaz8Q8PHK7BY+8SOAE2GnZdsFKW5opqyfpkfQ3rgFcZb9RJQfoW9FOV7/1QrN+3CFrjW7G1MgrAWSuZGhVavfr9OzAtcxG9w2pjFK10j8iFk7pJBY8VukG4JPk7rdLWSh5K9WcyJfQEfSTJduNnIwKHb5xabJuIqtlyEookN1VkTGVYVFbPykJ3+vbw6NauN+g9HkitIpuvS8vvgR9O+m2DvACNhR3PHXsldjcl/eWBes X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:56:31.2835 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63b4ea75-52b1-4ad8-4817-08debbef5fe9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E60.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9522 Content-Type: text/plain; charset="utf-8" From: Shay Drory With SD devices joining the LAG, peer flows are not created for all devcom peers - SD devices skip peers that belong to a different SD group. However, the delete path iterated all devcom peers unconditionally, attempting to delete from slots that were never populated. Track which peer slots are populated using a bitmap in mlx5e_tc_flow. The delete path now iterates only set bits, matching exactly the slots that were set up during flow creation. Signed-off-by: Shay Drory Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h | 3 +++ drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 10 +++------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h b/drivers= /net/ethernet/mellanox/mlx5/core/en/tc_priv.h index efb34de4cb7a..a0434ceebe69 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h @@ -97,6 +97,9 @@ struct mlx5e_tc_flow { struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */ struct list_head hairpin; /* flows sharing the same hairpin */ struct list_head peer[MLX5_MAX_PORTS]; /* flows with peer flow */ + DECLARE_BITMAP(peer_used, MLX5_MAX_PORTS); /* tracks populated peer + * slots + */ struct list_head unready; /* flows not ready to be offloaded (e.g * due to missing route) */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tc.c index 3846c16c3138..2a16368a948e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -2128,6 +2128,7 @@ static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_t= c_flow *flow, =20 mutex_lock(&esw->offloads.peer_mutex); list_del(&flow->peer[peer_index]); + clear_bit(peer_index, flow->peer_used); mutex_unlock(&esw->offloads.peer_mutex); =20 list_for_each_entry_safe(peer_flow, tmp, &flow->peer_flows, peer_flows) { @@ -2147,16 +2148,10 @@ static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e= _tc_flow *flow, =20 static void mlx5e_tc_del_fdb_peers_flow(struct mlx5e_tc_flow *flow) { - struct mlx5_devcom_comp_dev *devcom; - struct mlx5_devcom_comp_dev *pos; - struct mlx5_eswitch *peer_esw; int i; =20 - devcom =3D flow->priv->mdev->priv.eswitch->devcom; - mlx5_devcom_for_each_peer_entry(devcom, peer_esw, pos) { - i =3D mlx5_lag_get_dev_seq(peer_esw->dev); + for_each_set_bit(i, flow->peer_used, MLX5_MAX_PORTS) mlx5e_tc_del_fdb_peer_flow(flow, i); - } } =20 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv, @@ -4618,6 +4613,7 @@ static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls= _offload *f, flow_flag_set(flow, DUP); mutex_lock(&esw->offloads.peer_mutex); list_add_tail(&flow->peer[i], &esw->offloads.peer_flows[i]); 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Wed, 27 May 2026 05:56:10 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 12/13] net/mlx5e: TC, enable steering for SD LAG Date: Wed, 27 May 2026 15:54:26 +0300 Message-ID: <20260527125427.385976-13-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB72:EE_|DS7PR12MB6166:EE_ X-MS-Office365-Filtering-Correlation-Id: 15016823-2d71-4b7b-eef0-08debbef5e25 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|7416014|11063799006|22082099003|18002099003|6133799003|56012099006; X-Microsoft-Antispam-Message-Info: RDfKRGJ3OfOV8dQeVtLgrXQQA2FpbEIOr5IpX606FIAGe0FKLpxKfLtVEo+cjt4PI5oihKX8uwBLw78tM5LUvCyypOD6ZaOYJRPt0vItqIjMpWAJkvOaEevNrHku88pxW/uqhl3RUZf2EzQ6yT3RbK8q8kGdLA8djtlSS/ondDGheeCQJVFAJTNiBMC8O9yPdfo/m4QoJN1ew11yvoALsMPxcW6xYbt7cty9GmekA3fJbPuGnYcRbLz1v5vT/0v2RbZmCBuhauWjXCtD6i2ekAZRmM1S0vdxK3O0ums2siAQ6RBG9tkDqZlN75FokXsF0iFtjBMGskzBECwvz3lJ1DIQmvI4DPMRjwUCSU8OsQMoJv+3cW3slC+lgttCQu9S9QUhGv4mSs12ltQbpIS3q05xtcjKjn6Og+GAva5EOOhTND7nayBGZYrT8KP3RpBCTFxb6/Q/+pedXkoVZ7tmXRZ5P/+VkERVwXlwQ7N5RZ7uMUO/ovHeHFBxn56Y+3y/odtHkgo5swPdAXSxptfF5cfenb60FjHLzKuMza2DesVEnxE6gqkhL26f7pITQC7MgwMluz5ue/sJaj2HQEt2zgVhT/FtdO5J7/HBW5gyrfq9sxzHdJjzcdS25aKxhWeMtpefAG3x0SSqGAQv5pxSkdsNib1oaoajSHcpV7U9goYCS3Z59YOE6NDL1t3aP8sdXYIZGrs//z5Gr8zwPxtepFcFZM6qkN9+IfQVScjoljA= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(7416014)(11063799006)(22082099003)(18002099003)(6133799003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Nl08BXdR4Mik0P1MvSXhd0nd+Pgg2n44R91mOlijIZvU23354XAjFZcpTlD/vkPlN8E6a2PvYplxVIHYb7apDVkLyLbCRy0VlvCysLv29dZ7y2/G1Uu8Nf73GjcA46rhvjb7X5XNEW9krLWnjRLeQG8cgTLW4enDIkD+xddATb4tb7Wj3W57/LNiPD1j3UmOWcU6PXUSt4ibz3V3pTeV+CDY0IT3IdYXtZn9jKX3AmH7iVVIIWIUb9DFljdgrbiFa1yfuCyXBUoMCrTzUgSnqsoeGqCQE1qOieUX76UqI/5QZGe5Sa2S9aAqvUyTz9TB4ADSY8r+0SQUGsR1i84nnMd9lyxQ2RXcEJOhty1PwVWAXYAiLeVTWcrQDRlh5OLF81S9YbJ1eZKnSVOu+TesbxlTXoPn9xlrhviUb6p5lmXqzZfemEkpJndT+QaYEbyi X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:56:28.2443 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15016823-2d71-4b7b-eef0-08debbef5e25 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6166 Content-Type: text/plain; charset="utf-8" From: Shay Drory Enable TC flow steering for SD LAG mode by extending multiport eligibility checks and peer flow handling. SD LAG operates similarly to MPESW for TC offloads - flows on secondary devices need peer flow creation on the primary, and multiport forwarding rules are eligible when either MPESW or SD LAG is active. Add mlx5_lag_is_sd() helper to query SD LAG mode, and mlx5_sd_is_primary() to identify the primary device. Redirect uplink priv/proto_dev queries to the primary device's eswitch in SD configurations. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/tc_priv.h | 4 ++ .../net/ethernet/mellanox/mlx5/core/en_tc.c | 53 +++++++++++++++++-- .../mellanox/mlx5/core/eswitch_offloads.c | 8 +++ .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 14 +++++ .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 1 + .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 15 +++++- .../net/ethernet/mellanox/mlx5/core/lib/sd.h | 2 + 7 files changed, 92 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h b/drivers= /net/ethernet/mellanox/mlx5/core/en/tc_priv.h index a0434ceebe69..28cab4bf525c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_priv.h @@ -104,6 +104,10 @@ struct mlx5e_tc_flow { * due to missing route) */ struct list_head peer_flows; /* flows on peer */ + int peer_index; /* peer-flow index pinned at add time, used at del + * time so removal is independent of LAG state + * changes between add and del. + */ struct net_device *orig_dev; /* netdev adding flow first */ int tmp_entry_index; struct list_head tmp_list; /* temporary flow list used by neigh update */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tc.c index 2a16368a948e..910492eb51f2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -71,6 +71,7 @@ #include #include "lag/lag.h" #include "lag/mp.h" +#include "lib/sd.h" =20 #define MLX5E_TC_TABLE_NUM_GROUPS 4 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18) @@ -2132,7 +2133,7 @@ static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_t= c_flow *flow, mutex_unlock(&esw->offloads.peer_mutex); =20 list_for_each_entry_safe(peer_flow, tmp, &flow->peer_flows, peer_flows) { - if (peer_index !=3D mlx5_lag_get_dev_seq(peer_flow->priv->mdev)) + if (peer_index !=3D peer_flow->peer_index) continue; =20 list_del(&peer_flow->peer_flows); @@ -4196,9 +4197,26 @@ static bool is_lag_dev(struct mlx5e_priv *priv, same_hw_reps(priv, peer_netdev)); } =20 +static bool is_sd_eligible(struct mlx5e_priv *priv, + struct net_device *peer_netdev) +{ + struct mlx5e_priv *peer_priv; + + peer_priv =3D netdev_priv(peer_netdev); + return same_hw_reps(priv, peer_netdev) && + mlx5_lag_is_sd(priv->mdev) && + (mlx5_sd_get_primary(priv->mdev) =3D=3D + mlx5_sd_get_primary(peer_priv->mdev)); +} + static bool is_multiport_eligible(struct mlx5e_priv *priv, struct net_devi= ce *out_dev) { - return same_hw_reps(priv, out_dev) && mlx5_lag_is_mpesw(priv->mdev); + struct mlx5_core_dev *primary =3D mlx5_sd_get_primary(priv->mdev); + + if (!primary) + return false; + + return same_hw_reps(priv, out_dev) && mlx5_lag_is_mpesw(primary); } =20 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv, @@ -4207,6 +4225,9 @@ bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv= *priv, if (is_merged_eswitch_vfs(priv, out_dev)) return true; =20 + if (is_sd_eligible(priv, out_dev)) + return true; + if (is_multiport_eligible(priv, out_dev)) return true; =20 @@ -4351,7 +4372,7 @@ static struct rhashtable *get_tc_ht(struct mlx5e_priv= *priv, return &tc->ht; } =20 -static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow) +static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow, bool *is_sd) { struct mlx5_esw_flow_attr *esw_attr =3D flow->attr->esw_attr; struct mlx5_flow_attr *attr =3D flow->attr; @@ -4372,6 +4393,13 @@ static bool is_peer_flow_needed(struct mlx5e_tc_flow= *flow) if (mlx5_lag_is_mpesw(esw_attr->in_mdev)) return true; =20 + if (mlx5_lag_is_sd(esw_attr->in_mdev) && + !mlx5_sd_is_primary(esw_attr->in_mdev)) { + if (!mlx5_lag_is_mpesw(mlx5_sd_get_primary(esw_attr->in_mdev))) + *is_sd =3D true; + return true; + } + return false; } =20 @@ -4609,6 +4637,7 @@ static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls= _offload *f, goto out; } =20 + peer_flow->peer_index =3D i; list_add_tail(&peer_flow->peer_flows, &flow->peer_flows); flow_flag_set(flow, DUP); mutex_lock(&esw->offloads.peer_mutex); @@ -4628,19 +4657,26 @@ mlx5e_add_fdb_flow(struct mlx5e_priv *priv, struct mlx5e_tc_flow **__flow) { struct mlx5_devcom_comp_dev *devcom =3D priv->mdev->priv.eswitch->devcom,= *pos; + struct netlink_ext_ack *extack =3D f->common.extack; struct mlx5e_rep_priv *rpriv =3D priv->ppriv; struct mlx5_eswitch_rep *in_rep =3D rpriv->rep; struct mlx5_core_dev *in_mdev =3D priv->mdev; struct mlx5_eswitch *peer_esw; struct mlx5e_tc_flow *flow; + bool is_sd =3D false; int err; =20 + if (mlx5_lag_is_sd(in_mdev) && !mlx5_lag_is_active(in_mdev)) { + NL_SET_ERR_MSG_MOD(extack, "SD shared FDB not yet active"); + return -EOPNOTSUPP; + } + flow =3D __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep, in_mdev); if (IS_ERR(flow)) return PTR_ERR(flow); =20 - if (!is_peer_flow_needed(flow)) { + if (!is_peer_flow_needed(flow, &is_sd)) { *__flow =3D flow; return 0; } @@ -4651,6 +4687,15 @@ mlx5e_add_fdb_flow(struct mlx5e_priv *priv, } =20 mlx5_devcom_for_each_peer_entry(devcom, peer_esw, pos) { + if (is_sd) { + /* SD shared FDB: only the matching SD primary. */ + if (mlx5_sd_get_primary(in_mdev) !=3D + mlx5_sd_get_primary(peer_esw->dev)) + continue; + } else { + if (!mlx5_sd_is_primary(peer_esw->dev)) + continue; + } err =3D mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags, peer_esw); if (err) goto peer_clean; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index d65f30bb2f80..830fc910a080 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4690,8 +4690,11 @@ EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps_nes= ted); =20 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type) { + struct mlx5_core_dev *primary =3D mlx5_sd_get_primary(esw->dev); struct mlx5_eswitch_rep *rep; =20 + if (primary) + esw =3D primary->priv.eswitch; rep =3D mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK); return rep->rep_data[rep_type].priv; } @@ -4713,6 +4716,11 @@ EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev); =20 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_t= ype) { + struct mlx5_core_dev *primary =3D mlx5_sd_get_primary(esw->dev); + + if (primary) + esw =3D primary->priv.eswitch; + return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type); } EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index a2c7e2927431..dd3f18f85466 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -2425,6 +2425,20 @@ bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev) } EXPORT_SYMBOL(mlx5_lag_is_sriov); =20 +bool mlx5_lag_is_sd(struct mlx5_core_dev *dev) +{ + struct mlx5_lag *ldev; + unsigned long flags; + bool res; + + spin_lock_irqsave(&lag_lock, flags); + ldev =3D mlx5_lag_dev(dev); + res =3D ldev && __mlx5_lag_is_sd(ldev, dev); + spin_unlock_irqrestore(&lag_lock, flags); + + return res; +} + bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev) { struct mlx5_lag *ldev; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index cbe201529661..e412bb85027c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -202,6 +202,7 @@ static inline bool mlx5_lag_shared_fdb_supported(struct= mlx5_lag *ldev) } #endif bool mlx5_lag_check_prereq(struct mlx5_lag *ldev); +bool mlx5_lag_is_sd(struct mlx5_core_dev *dev); int mlx5_lag_demux_init(struct mlx5_core_dev *dev, struct mlx5_flow_table_attr *ft_attr); void mlx5_lag_demux_cleanup(struct mlx5_core_dev *dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index ec606851feb8..25286ecd724e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -49,13 +49,16 @@ static int mlx5_sd_get_host_buses(struct mlx5_core_dev = *dev) return sd->host_buses; } =20 -static struct mlx5_core_dev *mlx5_sd_get_primary(struct mlx5_core_dev *dev) +struct mlx5_core_dev *mlx5_sd_get_primary(struct mlx5_core_dev *dev) { struct mlx5_sd *sd =3D mlx5_get_sd(dev); =20 if (!sd) return dev; =20 + if (!mlx5_devcom_comp_is_ready(sd->devcom)) + return NULL; + return sd->primary ? dev : sd->primary_dev; } =20 @@ -69,6 +72,16 @@ struct mlx5_devcom_comp_dev *mlx5_sd_get_devcom(struct m= lx5_core_dev *dev) return sd->devcom; } =20 +bool mlx5_sd_is_primary(struct mlx5_core_dev *dev) +{ + struct mlx5_sd *sd =3D mlx5_get_sd(dev); + + if (!sd) + return true; + + return sd->primary; +} + struct mlx5_core_dev * mlx5_sd_primary_get_peer(struct mlx5_core_dev *primary, int idx) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.h index bf59903ab23f..011702ff6f02 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h @@ -10,6 +10,8 @@ =20 struct mlx5_sd; =20 +struct mlx5_core_dev *mlx5_sd_get_primary(struct mlx5_core_dev *dev); +bool mlx5_sd_is_primary(struct mlx5_core_dev *dev); struct mlx5_core_dev *mlx5_sd_primary_get_peer(struct mlx5_core_dev *prima= ry, int idx); int mlx5_sd_ch_ix_get_dev_ix(struct mlx5_core_dev *dev, int ch_ix); int mlx5_sd_ch_ix_get_vec_ix(struct mlx5_core_dev *dev, int ch_ix); --=20 2.44.0 From nobody Mon Jun 8 18:55:59 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012035.outbound.protection.outlook.com [40.107.200.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BA2921E091; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Shay Drory , Or Har-Toov , Edward Srouji , Maher Sanalla , Simon Horman , Parav Pandit , Patrisious Haddad , Kees Cook , Moshe Shemesh , , , , Gal Pressman Subject: [PATCH net-next 13/13] net/mlx5e: Verify unique vhca_id count instead of range Date: Wed, 27 May 2026 15:54:27 +0300 Message-ID: <20260527125427.385976-14-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260527125427.385976-1-tariqt@nvidia.com> References: <20260527125427.385976-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E61:EE_|BL1PR12MB5948:EE_ X-MS-Office365-Filtering-Correlation-Id: 64ec7503-2d74-4d09-d31b-08debbef68bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700016|1800799024|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: AiwUFlWLW+CSTd6Jh3gGNvLIMK1V1yDdktlRIWitkn8RklPRMSHfAwdSb3Hxub37gwPFBFL0NtsLJa9bMQHcc1lRvKIRkrz+yAE+QMsgYiiWZGN11IB63H7WdGMl/iWJfOD6SBfHPv1kQ8eBtbrp5qZqVq0C+pQzdrORaHSeWyAcNCNaEDRJbs0UN4Rsqom85xxHH9zpax8KANp94s74JeU8Za1yjXUMgIY0r9upS5GGO+aVMcEEJUiERsF6jPQiHWubYoAmCLitthGCTgzR/koPJB0Znqv93Si1U8vooAVsUtGnB7+t40vVai+MOfiur+qxT/Gmn2Djq5Nl0Lh40nTOY2SbtgNZCg9lr3t74f9xsq+J9wxXn5SXM2adjqvy/T+IzEd2utF0LAErDy39y8gRY8cjpaHX4i9lQWvQgOsVsLabPmeem+fM3Ff4HWxXbMeUlSejSTULxERbhTNIieHo1VpwLx1U8hPqV65thMhlhMeEP2PY3vf9A64mghAE8XJYJQ+3ZXqaSg565IpMXogUhp/tTrKKJRFhIZrmFTxHf8w/TLD2yvNWF5NAueviP+EwCEAB0sc86tEG+g4js1ja9+gfpnINiHk9JgrUOMJQnW4LFyzsOQVSpH59SZ8Ef9FP7Oh+sqsNy572Jskxh8fmmNu9pZgT4o3shgHzmGm551/DxD2Va9mkVIj46rlDmvSGgyI9KNbBypGdLkj555XJtGLX+ADMmXv8MJWtI/o= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700016)(1800799024)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: A/LF/cKVlNb8FB9s4FuBk4AxBt08JKyoIlymmXSdge+qRU5R7Lw1mAGjrInXZWfQqiEWcoQk02HuOQZ5VOFkYXFSwoFIDcy3YpNWfyFH+++fISa+OXXhqduaWOjhV4XZndFiO6M/ITqpwtxXbCPIvQPrQYGJ8vSxVxvLeDFdke7s7z2tiDdgeDy/tsHrBLCdLJtoXSIYX7dnGVti1O0f5YaKjC7ufbNM9m1ZvvlTulmpMHOzOn3wPgRgmS3+G1UhbI1qtJL2js0w0QTFcoqY+eVXTavT7KNc5zhCdgDuS5rpwkoRIm4pfCId0o9dnmusSMOwx/b6nigRQYAOEpbdFW7EbH7X0TPZhzxOE/PSDoPQHF2PSnGlg5J8U+eTi8RNMaOByHGjpvZoF4mkAUUoPGIb5ula5sT/gRJfvkdsGpnY6u3xndnRsfzjeaROg9+p X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 12:56:46.0920 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64ec7503-2d74-4d09-d31b-08debbef68bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E61.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5948 Content-Type: text/plain; charset="utf-8" From: Shay Drory Change verify_num_vhca_ids() to count the number of unique vhca_ids and verify this count doesn't exceed max_num_vhca_id, rather than validating individual vhca_id values are within a specific range. The previous implementation checked if each vhca_id was in the range [0, max_num_vhca_id - 1], which is overly restrictive. The hardware capability max_rqt_vhca_id represents the maximum number of unique vhca_ids that can be used, not a range constraint on individual IDs. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/rqt.c | 27 ++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rqt.c index a3382f6a6b74..8511363f7bec 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c @@ -8,13 +8,28 @@ static bool verify_num_vhca_ids(struct mlx5_core_dev *mde= v, u32 *vhca_ids, unsigned int size) { unsigned int max_num_vhca_id =3D MLX5_CAP_GEN_2(mdev, max_rqt_vhca_id); - int i; + unsigned int unique_count =3D 0; + int i, j; + + /* Count unique vhca_ids */ + for (i =3D 0; i < size; i++) { + bool is_unique =3D true; + + /* Check if vhca_ids[i] was already seen */ + for (j =3D 0; j < i; j++) { + if (vhca_ids[j] =3D=3D vhca_ids[i]) { + is_unique =3D false; + break; + } + } + if (is_unique) + unique_count++; + } =20 - /* Verify that all vhca_ids are in range [0, max_num_vhca_ids - 1] */ - for (i =3D 0; i < size; i++) - if (vhca_ids[i] >=3D max_num_vhca_id) - return false; - return true; + /* Verify that number of unique vhca_ids doesn't exceed + * max_num_vhca_id + */ + return unique_count <=3D max_num_vhca_id; } =20 static bool rqt_verify_vhca_ids(struct mlx5_core_dev *mdev, u32 *vhca_ids, --=20 2.44.0