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charset="utf-8" Add devicetree binding for the AMD/Xilinx Versal System Monitor (SysMon). The Versal SysMon is the successor to the Zynq UltraScale+ AMS block, providing on-chip voltage and temperature monitoring. The hardware supports up to 160 supply voltage measurement points and up to 64 temperature satellites distributed across the SoC, with configurable threshold alarms and oversampling. The device can be accessed via memory-mapped I/O or via an I2C interface. Supply and temperature channels are described as child nodes under container nodes, referencing the standard adc.yaml binding for channel properties. Co-developed-by: Michal Simek Signed-off-by: Michal Simek Signed-off-by: Salih Erim Reviewed-by: Krzysztof Kozlowski --- Changes in v3: - Use single compatible (xlnx,versal-sysmon only), remove xlnx,versal-sysmon-i2c (Krzysztof) - Rename supply-channels container to voltage-channels (Krzysztof) - Use single quotes in patternProperties regex (Krzysztof) - Drop label description from channel properties (Krzysztof) - Drop bipolar from channel properties (Krzysztof) - Remove xlnx,aie-temp property from binding and example (Krzysztof) Changes in v2: - Restructured to container nodes (supply-channels, temperature-channels) with channel@N children referencing adc.yaml - Added xlnx,versal-sysmon-i2c compatible - Descriptions rewritten to describe hardware only - Example simplified to #address-cells =3D <1> - Interrupt example uses GIC_SPI/IRQ_TYPE_LEVEL_HIGH constants - Commit description explains hardware context instead of schema layout - reg required for both MMIO and I2C, interrupts optional - Hex unit-addresses (channel@a not channel@10) per DTSpec - patternProperties regex updated to accept hex digits [0-9a-f] - Example trimmed to minimal variants (one basic + one bipolar supply, one AIE temperature channel) .../bindings/iio/adc/xlnx,versal-sysmon.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,versal-s= ysmon.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,versal-sysmon.y= aml b/Documentation/devicetree/bindings/iio/adc/xlnx,versal-sysmon.yaml new file mode 100644 index 00000000000..1ad58e3d616 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,versal-sysmon.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/xlnx,versal-sysmon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD/Xilinx Versal System Monitor + +maintainers: + - Salih Erim + +description: + The AMD/Xilinx Versal System Monitor (SysMon) is the successor to the + Zynq UltraScale+ AMS block. It provides on-chip voltage and temperature + monitoring with up to 160 voltage measurement points and up to + 64 temperature satellites distributed across the SoC. The hardware + supports configurable threshold alarms and oversampling. The device + can be accessed via memory-mapped I/O or via an I2C interface. + +properties: + compatible: + const: xlnx,versal-sysmon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#io-channel-cells': + const: 1 + + voltage-channels: + type: object + description: + Container for voltage measurement channels. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + '^channel@([0-9a-f]|[1-9][0-9a-f])$': + $ref: adc.yaml + + description: + Measures a voltage rail. The register index and rail + name are assigned by the hardware design tool (Vivado). + + properties: + reg: + minimum: 0 + maximum: 159 + description: + Voltage measurement register index assigned by the hardware + design tool. + + required: + - reg + - label + + unevaluatedProperties: false + + required: + - '#address-cells' + - '#size-cells' + + additionalProperties: false + + temperature-channels: + type: object + description: + Container for temperature satellite measurement channels. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + '^channel@([1-9a-f]|[1-3][0-9a-f]|40)$': + $ref: adc.yaml + + description: + Reads a temperature satellite sensor. Each satellite monitors + a specific region of the SoC die. + + properties: + reg: + minimum: 1 + maximum: 64 + description: + Temperature satellite number (1-based hardware index). + + required: + - reg + - label + + unevaluatedProperties: false + + required: + - '#address-cells' + - '#size-cells' + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + sysmon@f1270000 { + compatible =3D "xlnx,versal-sysmon"; + reg =3D <0xf1270000 0x4000>; + interrupts =3D ; + #io-channel-cells =3D <1>; + + voltage-channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + label =3D "vccaux"; + }; + + channel@3 { + reg =3D <3>; + label =3D "vcc_ram"; + bipolar; + }; + }; + + temperature-channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@a { + reg =3D <10>; + label =3D "aie-temp-ch1"; + }; + }; + }; --=20 2.48.1 From nobody Mon Jun 8 18:55:59 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011054.outbound.protection.outlook.com [52.101.52.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64CBE3FCB2C; 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charset="utf-8" Add the core driver and MMIO platform driver for the AMD/Xilinx Versal System Monitor (SysMon) block. The SysMon block resides in the platform management controller (PMC) and provides on-chip voltage and temperature monitoring through a 10-bit, 200 kSPS ADC. It can monitor up to 160 voltage channels and 64 temperature satellites distributed across the SoC, with a consistent sample rate of 8 kSPS per channel regardless of how many channels are enabled. The driver is split into three compilation units: - versal-sysmon-core: Channel parsing, IIO registration, read_raw - versal-sysmon: MMIO platform driver with custom regmap accessors Voltage results are stored in a 19-bit modified floating-point format and converted to millivolts. Temperature results are stored in Q8.7 signed fixed-point Celsius format and converted to millicelsius. The MMIO regmap backend uses a custom reg_write accessor that automatically unlocks the NPI (NoC programming interface) lock register before each write, as required by the hardware. The regmap is configured with fast_io since the underlying MMIO accessors are safe to call from atomic context. Co-developed-by: Michal Simek Signed-off-by: Michal Simek Signed-off-by: Salih Erim --- Changes in v3: - IWYU: add array_size.h, string.h, types.h to core; audit and fix header and MMIO driver includes (Andy) - Rename _ext to _name in SYSMON_CHAN_TEMP macro parameter (Andy, Jonathan) - Use .info_mask_separate =3D BIT() style in SYSMON_CHAN_TEMP (Andy) - Use s16 parameter in sysmon_q8p7_to_millicelsius (Andy) - Use sign_extend32() in sysmon_supply_rawtoprocessed (Andy) - Split sysmon_read_raw parameters logically across lines (Andy) - Remove redundant (int) casts on regval (Andy) - Split num_supply/num_temp initialization (Andy) - Use __free(fwnode_handle) cleanup, remove goto err_put (Andy) - Use size_add() for overflow-safe allocation (Andy) - Use dev_err_probe() in sysmon_parse_fw error paths (Jonathan) - Move fwnode_irq_get() to core_probe, remove irq parameter from bus driver interfaces (Jonathan) - Use (int)MILLI at call sites, drop SYSMON_MILLI define (Andy, Jonathan) - Remove sysmon->dev, sysmon->indio_dev, sysmon->irq from struct; pass as local variables or use regmap_get_device() (Jonathan) - Use struct device *dev local in sysmon_platform_probe (Andy) - Describe protected data in lock comment (Jonathan) - Add comment explaining RAW+PROCESSED co-exposure (Jonathan) Changes in v2: - Split into core (versal-sysmon-core.c) + MMIO platform driver (versal-sysmon.c) + shared header (versal-sysmon.h) - Uses regmap API instead of direct readl/writel - MMIO regmap uses custom callbacks with NPI unlock in write path - Reverse Christmas Tree variable ordering throughout - Header include order fixed - MAINTAINERS entry folded in with wildcard F: pattern - Kconfig: hidden VERSAL_SYSMON_CORE + VERSAL_SYSMON selects it - Kconfig/Makefile: alphabetical ordering (VERSAL before VF610) - Bounds validation on DT reg values - Named constants replace magic numbers (SYSMON_REG_STRIDE, SYSMON_SUPPLY_MANTISSA_BITS, SYSMON_MILLI) - kernel-doc for exported sysmon_core_probe() and sysmon_parse_fw() - Supply voltage conversion uses proper two's complement sign extension (s16 cast) matching the hardware specification - Register offsets sorted by address in header - Each patch introduces only the defines, fields, and includes it uses (no dead code in any commit) - Removed unused linux/limits.h and linux/units.h includes - Renamed iio_dev_info to sysmon_iio_info - regmap_write return values checked in probe init path MAINTAINERS | 7 + drivers/iio/adc/Kconfig | 20 ++ drivers/iio/adc/Makefile | 2 + drivers/iio/adc/versal-sysmon-core.c | 311 +++++++++++++++++++++++++++ drivers/iio/adc/versal-sysmon.c | 92 ++++++++ drivers/iio/adc/versal-sysmon.h | 64 ++++++ 6 files changed, 496 insertions(+) create mode 100644 drivers/iio/adc/versal-sysmon-core.c create mode 100644 drivers/iio/adc/versal-sysmon.c create mode 100644 drivers/iio/adc/versal-sysmon.h diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd1..46762c8496d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29216,6 +29216,13 @@ F: Documentation/devicetree/bindings/memory-contro= llers/xlnx,versal-net-ddrmc5.y F: drivers/edac/versalnet_edac.c F: include/linux/cdx/edac_cdx_pcol.h =20 +XILINX VERSAL SYSMON DRIVER +M: Salih Erim +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/adc/xlnx,versal-sysmon.yaml +F: drivers/iio/adc/versal-sysmon* + XILINX WATCHDOG DRIVER M: Srinivas Neeli R: Shubhrajyoti Datta diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index a9dedbb8eb4..c7f19057484 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1943,6 +1943,26 @@ config TWL6030_GPADC This driver can also be built as a module. If so, the module will be called twl6030-gpadc. =20 +config VERSAL_SYSMON_CORE + tristate + select REGMAP + +config VERSAL_SYSMON + tristate "AMD Versal SysMon driver" + depends on ARCH_ZYNQMP || COMPILE_TEST + depends on HAS_IOMEM + select VERSAL_SYSMON_CORE + help + Say yes here to have support for the AMD/Xilinx Versal System + Monitor (SysMon). This driver provides voltage and temperature + monitoring through the IIO subsystem. + + The SysMon measures up to 160 supply voltages and reads up to + 64 temperature satellites distributed across the SoC. + + To compile this driver as a module, choose M here: the module + will be called versal-sysmon. + config VF610_ADC tristate "Freescale vf610 ADC driver" depends on HAS_IOMEM diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 097357d146b..d7696b1b157 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -167,6 +167,8 @@ obj-$(CONFIG_TI_TLC4541) +=3D ti-tlc4541.o obj-$(CONFIG_TI_TSC2046) +=3D ti-tsc2046.o obj-$(CONFIG_TWL4030_MADC) +=3D twl4030-madc.o obj-$(CONFIG_TWL6030_GPADC) +=3D twl6030-gpadc.o +obj-$(CONFIG_VERSAL_SYSMON_CORE) +=3D versal-sysmon-core.o +obj-$(CONFIG_VERSAL_SYSMON) +=3D versal-sysmon.o obj-$(CONFIG_VF610_ADC) +=3D vf610_adc.o obj-$(CONFIG_VIPERBOARD_ADC) +=3D viperboard_adc.o obj-$(CONFIG_XILINX_AMS) +=3D xilinx-ams.o diff --git a/drivers/iio/adc/versal-sysmon-core.c b/drivers/iio/adc/versal-= sysmon-core.c new file mode 100644 index 00000000000..ebe052f6982 --- /dev/null +++ b/drivers/iio/adc/versal-sysmon-core.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Versal SysMon core driver + * + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "versal-sysmon.h" + +/* + * Both RAW and PROCESSED are exposed: RAW is needed for event thresholds + * (which operate in hardware register format), PROCESSED gives userspace + * the converted millivolt or millicelsius value. + */ +#define SYSMON_CHAN_TEMP(_chan, _address, _name) { \ + .type =3D IIO_TEMP, \ + .indexed =3D 1, \ + .address =3D _address, \ + .channel =3D _chan, \ + .info_mask_separate =3D \ + BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_PROCESSED), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D 15, \ + .storagebits =3D 16, \ + .endianness =3D IIO_CPU, \ + }, \ + .datasheet_name =3D _name, \ +} + +/* Static temperature channels (always present) */ +static const struct iio_chan_spec temp_channels[] =3D { + SYSMON_CHAN_TEMP(0, SYSMON_TEMP_MAX, "temp"), + SYSMON_CHAN_TEMP(1, SYSMON_TEMP_MIN, "min"), + SYSMON_CHAN_TEMP(2, SYSMON_TEMP_MAX_MAX, "max_max"), + SYSMON_CHAN_TEMP(3, SYSMON_TEMP_MIN_MIN, "min_min"), +}; + +static void sysmon_q8p7_to_millicelsius(s16 raw_data, int *val) +{ + *val =3D (raw_data * (int)MILLI) >> SYSMON_FRACTIONAL_SHIFT; +} + +static void sysmon_supply_rawtoprocessed(int raw_data, int *val) +{ + int mantissa, format, exponent; + + mantissa =3D FIELD_GET(SYSMON_MANTISSA_MASK, raw_data); + exponent =3D SYSMON_SUPPLY_MANTISSA_BITS - FIELD_GET(SYSMON_MODE_MASK, ra= w_data); + format =3D FIELD_GET(SYSMON_FMT_MASK, raw_data); + /* + * When format bit is set the mantissa is two's complement + * (per hardware spec); sign-extend to int for correct arithmetic. + */ + if (format) + mantissa =3D sign_extend32(mantissa, 15); + + *val =3D (mantissa * (int)MILLI) >> exponent; +} + +static int sysmon_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct sysmon *sysmon =3D iio_priv(indio_dev); + unsigned int regval; + int ret; + + if (mask !=3D IIO_CHAN_INFO_RAW && mask !=3D IIO_CHAN_INFO_PROCESSED) + return -EINVAL; + + guard(mutex)(&sysmon->lock); + + switch (chan->type) { + case IIO_TEMP: + ret =3D regmap_read(sysmon->regmap, chan->address, ®val); + if (ret) + return ret; + if (mask =3D=3D IIO_CHAN_INFO_PROCESSED) + sysmon_q8p7_to_millicelsius(regval, val); + else + *val =3D regval; + return IIO_VAL_INT; + + case IIO_VOLTAGE: + ret =3D regmap_read(sysmon->regmap, + (chan->address * SYSMON_REG_STRIDE) + + SYSMON_SUPPLY_BASE, ®val); + if (ret) + return ret; + if (mask =3D=3D IIO_CHAN_INFO_PROCESSED) + sysmon_supply_rawtoprocessed(regval, val); + else + *val =3D regval; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + +static int sysmon_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + char *label) +{ + if (chan->datasheet_name) + return sysfs_emit(label, "%s\n", chan->datasheet_name); + + return -EINVAL; +} + +static const struct iio_info sysmon_iio_info =3D { + .read_raw =3D sysmon_read_raw, + .read_label =3D sysmon_read_label, +}; + +/** + * sysmon_parse_fw() - Parse firmware nodes and configure IIO channels. + * @indio_dev: IIO device instance + * @dev: Parent device + * + * Reads voltage-channels and temperature-channels container nodes from + * firmware and builds the IIO channel array. Static temperature channels + * are prepended, followed by supply and satellite channels from DT. + * + * Return: 0 on success, negative errno on failure. + */ +static int sysmon_parse_fw(struct iio_dev *indio_dev, struct device *dev) +{ + struct fwnode_handle *supply_node __free(fwnode_handle) =3D + device_get_named_child_node(dev, "voltage-channels"); + struct fwnode_handle *temp_node __free(fwnode_handle) =3D + device_get_named_child_node(dev, "temperature-channels"); + unsigned int num_supply =3D 0, num_temp =3D 0; + unsigned int idx, temp_chan_idx, volt_chan_idx; + struct iio_chan_spec *sysmon_channels; + const char *label; + u32 reg; + int ret; + + if (supply_node) + num_supply =3D fwnode_get_child_node_count(supply_node); + if (temp_node) + num_temp =3D fwnode_get_child_node_count(temp_node); + + sysmon_channels =3D devm_kcalloc(dev, + size_add(ARRAY_SIZE(temp_channels), + num_supply + num_temp), + sizeof(*sysmon_channels), GFP_KERNEL); + if (!sysmon_channels) + return -ENOMEM; + + /* Static temperature channels first (fixed indices) */ + idx =3D 0; + memcpy(sysmon_channels, temp_channels, sizeof(temp_channels)); + idx +=3D ARRAY_SIZE(temp_channels); + + /* Supply channels from DT */ + fwnode_for_each_child_node_scoped(supply_node, child) { + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret < 0) + return dev_err_probe(dev, ret, + "missing reg for supply channel\n"); + + if (reg > SYSMON_SUPPLY_IDX_MAX) + return dev_err_probe(dev, -EINVAL, + "supply reg %u exceeds max %u\n", + reg, SYSMON_SUPPLY_IDX_MAX); + + ret =3D fwnode_property_read_string(child, "label", &label); + if (ret < 0) + return dev_err_probe(dev, ret, + "missing label for supply channel\n"); + + sysmon_channels[idx++] =3D (struct iio_chan_spec) { + .type =3D IIO_VOLTAGE, + .indexed =3D 1, + .address =3D reg, + .info_mask_separate =3D + BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_PROCESSED), + .scan_type =3D { + .realbits =3D 19, + .storagebits =3D 32, + .endianness =3D IIO_CPU, + .sign =3D fwnode_property_read_bool(child, + "bipolar") ? 's' : 'u', + }, + .datasheet_name =3D label, + }; + } + + /* Temperature satellite channels from DT */ + fwnode_for_each_child_node_scoped(temp_node, child) { + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret < 0) + return dev_err_probe(dev, ret, + "missing reg for temp channel\n"); + + if (reg < 1 || reg > SYSMON_TEMP_SAT_MAX) + return dev_err_probe(dev, -EINVAL, + "temp reg %u out of range [1..%u]\n", + reg, SYSMON_TEMP_SAT_MAX); + + ret =3D fwnode_property_read_string(child, "label", &label); + if (ret < 0) + return dev_err_probe(dev, ret, + "missing label for temp channel\n"); + + sysmon_channels[idx++] =3D (struct iio_chan_spec) { + .type =3D IIO_TEMP, + .indexed =3D 1, + .address =3D SYSMON_TEMP_SAT_BASE + + ((reg - 1) * SYSMON_REG_STRIDE), + .info_mask_separate =3D + BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_PROCESSED), + .scan_type =3D { + .sign =3D 's', + .realbits =3D 15, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, + .datasheet_name =3D label, + }; + } + + indio_dev->num_channels =3D idx; + indio_dev->info =3D &sysmon_iio_info; + + /* + * Assign per-type sequential channel numbers. + * IIO sysfs uses type prefix (in_tempN, in_voltageN) + * so numbers only need to be unique within each type. + */ + temp_chan_idx =3D 0; + volt_chan_idx =3D 0; + for (idx =3D 0; idx < indio_dev->num_channels; idx++) { + if (sysmon_channels[idx].type =3D=3D IIO_TEMP) + sysmon_channels[idx].channel =3D temp_chan_idx++; + else + sysmon_channels[idx].channel =3D volt_chan_idx++; + } + + indio_dev->channels =3D sysmon_channels; + + return 0; +} + +/** + * sysmon_core_probe() - Initialize Versal SysMon core + * @dev: Parent device + * @regmap: Register map for hardware access + * + * Return: 0 on success, negative errno on failure. + */ +int sysmon_core_probe(struct device *dev, struct regmap *regmap) +{ + struct iio_dev *indio_dev; + struct sysmon *sysmon; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*sysmon)); + if (!indio_dev) + return -ENOMEM; + + sysmon =3D iio_priv(indio_dev); + sysmon->regmap =3D regmap; + + ret =3D devm_mutex_init(dev, &sysmon->lock); + if (ret) + return ret; + + /* Disable all interrupts and clear pending status */ + ret =3D regmap_write(sysmon->regmap, SYSMON_IDR, SYSMON_INTR_ALL_MASK); + if (ret) + return ret; + ret =3D regmap_write(sysmon->regmap, SYSMON_ISR, SYSMON_INTR_ALL_MASK); + if (ret) + return ret; + + indio_dev->name =3D "versal-sysmon"; + indio_dev->modes =3D INDIO_DIRECT_MODE; + + ret =3D sysmon_parse_fw(indio_dev, dev); + if (ret) + return ret; + + return devm_iio_device_register(dev, indio_dev); +} +EXPORT_SYMBOL_GPL(sysmon_core_probe); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD Versal SysMon Core Driver"); +MODULE_AUTHOR("Salih Erim "); diff --git a/drivers/iio/adc/versal-sysmon.c b/drivers/iio/adc/versal-sysmo= n.c new file mode 100644 index 00000000000..8473288e7db --- /dev/null +++ b/drivers/iio/adc/versal-sysmon.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Versal SysMon MMIO platform driver + * + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include + +#include "versal-sysmon.h" + +struct sysmon_mmio { + void __iomem *base; +}; + +static int sysmon_mmio_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct sysmon_mmio *mmio =3D context; + + *val =3D readl(mmio->base + reg); + return 0; +} + +static int sysmon_mmio_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct sysmon_mmio *mmio =3D context; + + /* NPI must be unlocked before any register write except to NPI_LOCK */ + if (reg !=3D SYSMON_NPI_LOCK) + writel(SYSMON_NPI_UNLOCK_CODE, mmio->base + SYSMON_NPI_LOCK); + writel(val, mmio->base + reg); + + return 0; +} + +static const struct regmap_config sysmon_mmio_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D SYSMON_REG_STRIDE, + .max_register =3D SYSMON_MAX_REG, + .reg_read =3D sysmon_mmio_reg_read, + .reg_write =3D sysmon_mmio_reg_write, + .fast_io =3D true, +}; + +static int sysmon_platform_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sysmon_mmio *mmio; + struct regmap *regmap; + + mmio =3D devm_kzalloc(dev, sizeof(*mmio), GFP_KERNEL); + if (!mmio) + return -ENOMEM; + + mmio->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmio->base)) + return PTR_ERR(mmio->base); + + regmap =3D devm_regmap_init(dev, NULL, mmio, + &sysmon_mmio_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return sysmon_core_probe(dev, regmap); +} + +static const struct of_device_id sysmon_of_match_table[] =3D { + { .compatible =3D "xlnx,versal-sysmon" }, + { } +}; +MODULE_DEVICE_TABLE(of, sysmon_of_match_table); + +static struct platform_driver sysmon_platform_driver =3D { + .probe =3D sysmon_platform_probe, + .driver =3D { + .name =3D "versal-sysmon", + .of_match_table =3D sysmon_of_match_table, + }, +}; +module_platform_driver(sysmon_platform_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD Versal SysMon Platform Driver"); +MODULE_AUTHOR("Salih Erim "); diff --git a/drivers/iio/adc/versal-sysmon.h b/drivers/iio/adc/versal-sysmo= n.h new file mode 100644 index 00000000000..d24d2481915 --- /dev/null +++ b/drivers/iio/adc/versal-sysmon.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * AMD Versal SysMon driver + * + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _VERSAL_SYSMON_H_ +#define _VERSAL_SYSMON_H_ + +#include +#include +#include + +struct device; +struct iio_dev; +struct regmap; + +/* Register offsets (sorted by address) */ +#define SYSMON_NPI_LOCK 0x000C +#define SYSMON_ISR 0x0044 +#define SYSMON_IDR 0x0050 +#define SYSMON_TEMP_MAX 0x1030 +#define SYSMON_TEMP_MIN 0x1034 +#define SYSMON_SUPPLY_BASE 0x1040 +#define SYSMON_TEMP_MIN_MIN 0x1F8C +#define SYSMON_TEMP_MAX_MAX 0x1F90 +#define SYSMON_TEMP_SAT_BASE 0x1FAC +#define SYSMON_MAX_REG 0x24C0 + +/* NPI unlock value written to SYSMON_NPI_LOCK */ +#define SYSMON_NPI_UNLOCK_CODE 0xF9E8D7C6 + +/* Register stride: 4 bytes per 32-bit register */ +#define SYSMON_REG_STRIDE 4 + +#define SYSMON_SUPPLY_IDX_MAX 159 +#define SYSMON_TEMP_SAT_MAX 64 +#define SYSMON_INTR_ALL_MASK GENMASK(31, 0) + +/* Supply voltage conversion register fields */ +#define SYSMON_MANTISSA_MASK GENMASK(15, 0) +#define SYSMON_FMT_MASK BIT(16) +#define SYSMON_MODE_MASK GENMASK(18, 17) + +/* Q8.7 fractional shift */ +#define SYSMON_FRACTIONAL_SHIFT 7U +#define SYSMON_SUPPLY_MANTISSA_BITS 16 + +/** + * struct sysmon - Driver data for Versal SysMon + * @regmap: register map for hardware access + * @lock: protects regmap access + */ +struct sysmon { + struct regmap *regmap; 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charset="utf-8" Add an I2C transport driver for the Versal SysMon block. The SysMon provides an I2C slave interface that allows an external master to read voltage and temperature measurements through the same register map used by the MMIO path. The I2C command frame is an 8-byte structure containing a 4-byte data payload, a 2-byte register offset, and a 1-byte instruction field. Read operations send the frame with a read instruction, then receive a 4-byte response containing the register value. Events are not supported on the I2C path because there is no interrupt line and the I2C regmap backend cannot be called from atomic context. Co-developed-by: Conall O'Griofa Signed-off-by: Conall O'Griofa Signed-off-by: Salih Erim --- Changes in v3: - IWYU: fix includes (Andy) - Enum: assign all values explicitly for HW-mapped fields (Andy) - Remove sysmon_i2c wrapper struct, pass i2c_client directly (Andy) - Use sizeof() for I2C buffer lengths instead of defines (Andy) - Use =3D { } instead of =3D { 0 } for initializers (Andy) - Use single compatible xlnx,versal-sysmon (Krzysztof) - Adapt to core_probe interface change: irq moved to core, remove irq parameter from bus driver (Jonathan) Changes in v2: - New patch (I2C was deferred to Series B in v1) - Uses regmap API with custom I2C read/write callbacks - Shares core module with MMIO driver via sysmon_core_probe() - No event support (I2C has no interrupt line) - Separate VERSAL_SYSMON_I2C Kconfig symbol - Reverse Christmas Tree variable ordering in read/write functions drivers/iio/adc/Kconfig | 13 +++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/versal-sysmon-i2c.c | 153 ++++++++++++++++++++++++++++ 3 files changed, 167 insertions(+) create mode 100644 drivers/iio/adc/versal-sysmon-i2c.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index c7f19057484..8f9fc9de74a 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1963,6 +1963,19 @@ config VERSAL_SYSMON To compile this driver as a module, choose M here: the module will be called versal-sysmon. =20 +config VERSAL_SYSMON_I2C + tristate "AMD Versal SysMon I2C driver" + depends on I2C + select VERSAL_SYSMON_CORE + help + Say yes here to have support for the AMD/Xilinx Versal System + Monitor (SysMon) via I2C interface. This driver enables voltage + and temperature monitoring when the Versal chip has SysMon + configured with I2C access. + + To compile this driver as a module, choose M here: the module + will be called versal-sysmon-i2c. + config VF610_ADC tristate "Freescale vf610 ADC driver" depends on HAS_IOMEM diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d7696b1b157..5abb611fe46 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -169,6 +169,7 @@ obj-$(CONFIG_TWL4030_MADC) +=3D twl4030-madc.o obj-$(CONFIG_TWL6030_GPADC) +=3D twl6030-gpadc.o obj-$(CONFIG_VERSAL_SYSMON_CORE) +=3D versal-sysmon-core.o obj-$(CONFIG_VERSAL_SYSMON) +=3D versal-sysmon.o +obj-$(CONFIG_VERSAL_SYSMON_I2C) +=3D versal-sysmon-i2c.o obj-$(CONFIG_VF610_ADC) +=3D vf610_adc.o obj-$(CONFIG_VIPERBOARD_ADC) +=3D viperboard_adc.o obj-$(CONFIG_XILINX_AMS) +=3D xilinx-ams.o diff --git a/drivers/iio/adc/versal-sysmon-i2c.c b/drivers/iio/adc/versal-s= ysmon-i2c.c new file mode 100644 index 00000000000..92d149f517e --- /dev/null +++ b/drivers/iio/adc/versal-sysmon-i2c.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Versal SysMon I2C driver + * + * Copyright (C) 2023 - 2026, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include + +#include "versal-sysmon.h" + +#define SYSMON_I2C_INSTR_READ BIT(2) +#define SYSMON_I2C_INSTR_WRITE BIT(3) + +#define SYSMON_I2C_DATA0_MASK GENMASK(7, 0) +#define SYSMON_I2C_DATA1_MASK GENMASK(15, 8) +#define SYSMON_I2C_DATA2_MASK GENMASK(23, 16) +#define SYSMON_I2C_DATA3_MASK GENMASK(31, 24) + +#define SYSMON_I2C_OFS_LOW_MASK GENMASK(9, 2) +#define SYSMON_I2C_OFS_HIGH_MASK GENMASK(15, 10) + +/* Byte positions within the 8-byte I2C command frame (HW-defined) */ +enum sysmon_i2c_payload_idx { + SYSMON_I2C_DATA0_IDX =3D 0, + SYSMON_I2C_DATA1_IDX =3D 1, + SYSMON_I2C_DATA2_IDX =3D 2, + SYSMON_I2C_DATA3_IDX =3D 3, + SYSMON_I2C_OFS_LOW_IDX =3D 4, + SYSMON_I2C_OFS_HIGH_IDX =3D 5, + SYSMON_I2C_INSTR_IDX =3D 6, +}; + +static int sysmon_i2c_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct i2c_client *client =3D context; + u8 write_buf[8] =3D { }; + u8 read_buf[4]; + int ret; + + write_buf[SYSMON_I2C_OFS_LOW_IDX] =3D + FIELD_GET(SYSMON_I2C_OFS_LOW_MASK, reg); + write_buf[SYSMON_I2C_OFS_HIGH_IDX] =3D + FIELD_GET(SYSMON_I2C_OFS_HIGH_MASK, reg); + write_buf[SYSMON_I2C_INSTR_IDX] =3D SYSMON_I2C_INSTR_READ; + + ret =3D i2c_master_send(client, write_buf, sizeof(write_buf)); + if (ret < 0) + return ret; + if (ret !=3D sizeof(write_buf)) + return -EIO; + + ret =3D i2c_master_recv(client, read_buf, sizeof(read_buf)); + if (ret < 0) + return ret; + if (ret !=3D sizeof(read_buf)) + return -EIO; + + *val =3D FIELD_PREP(SYSMON_I2C_DATA0_MASK, + read_buf[SYSMON_I2C_DATA0_IDX]) | + FIELD_PREP(SYSMON_I2C_DATA1_MASK, + read_buf[SYSMON_I2C_DATA1_IDX]) | + FIELD_PREP(SYSMON_I2C_DATA2_MASK, + read_buf[SYSMON_I2C_DATA2_IDX]) | + FIELD_PREP(SYSMON_I2C_DATA3_MASK, + read_buf[SYSMON_I2C_DATA3_IDX]); + + return 0; +} + +static int sysmon_i2c_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct i2c_client *client =3D context; + u8 write_buf[8] =3D { }; + int ret; + + write_buf[SYSMON_I2C_DATA0_IDX] =3D + FIELD_GET(SYSMON_I2C_DATA0_MASK, val); + write_buf[SYSMON_I2C_DATA1_IDX] =3D + FIELD_GET(SYSMON_I2C_DATA1_MASK, val); + write_buf[SYSMON_I2C_DATA2_IDX] =3D + FIELD_GET(SYSMON_I2C_DATA2_MASK, val); + write_buf[SYSMON_I2C_DATA3_IDX] =3D + FIELD_GET(SYSMON_I2C_DATA3_MASK, val); + write_buf[SYSMON_I2C_OFS_LOW_IDX] =3D + FIELD_GET(SYSMON_I2C_OFS_LOW_MASK, reg); + write_buf[SYSMON_I2C_OFS_HIGH_IDX] =3D + FIELD_GET(SYSMON_I2C_OFS_HIGH_MASK, reg); + write_buf[SYSMON_I2C_INSTR_IDX] =3D SYSMON_I2C_INSTR_WRITE; + + ret =3D i2c_master_send(client, write_buf, sizeof(write_buf)); + if (ret < 0) + return ret; + if (ret !=3D sizeof(write_buf)) + return -EIO; + + return 0; +} + +static const struct regmap_config sysmon_i2c_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D SYSMON_REG_STRIDE, + .max_register =3D SYSMON_MAX_REG, + .reg_read =3D sysmon_i2c_reg_read, + .reg_write =3D sysmon_i2c_reg_write, +}; + +static int sysmon_i2c_probe(struct i2c_client *client) +{ + struct regmap *regmap; + + regmap =3D devm_regmap_init(&client->dev, NULL, client, + &sysmon_i2c_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* I2C has no IRQ connection; events are not supported */ + return sysmon_core_probe(&client->dev, regmap); +} + +static const struct of_device_id sysmon_i2c_of_match_table[] =3D { + { .compatible =3D "xlnx,versal-sysmon" }, + { } +}; +MODULE_DEVICE_TABLE(of, sysmon_i2c_of_match_table); + +static const struct i2c_device_id sysmon_i2c_id_table[] =3D { + { "versal-sysmon" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, sysmon_i2c_id_table); + +static struct i2c_driver sysmon_i2c_driver =3D { + .probe =3D sysmon_i2c_probe, + .driver =3D { + .name =3D "versal-sysmon-i2c", + .of_match_table =3D sysmon_i2c_of_match_table, + }, + .id_table =3D sysmon_i2c_id_table, +}; +module_i2c_driver(sysmon_i2c_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD Versal SysMon I2C Driver"); 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charset="utf-8" Add threshold event support for temperature and supply voltage channels. Temperature events: - Rising threshold with configurable value - Over-temperature (OT) alarm with separate threshold - Per-channel hysteresis as a millicelsius value - Event direction is IIO_EV_DIR_RISING (hysteresis mode) Supply voltage events: - Rising/falling threshold per supply channel - Per-channel alarm enable via alarm configuration registers The hardware supports both window and hysteresis alarm modes for temperature. This driver uses hysteresis mode, where the upper threshold triggers the alarm and the lower threshold clears it (re-arm point). The hardware has a single ISR bit per temperature channel with no indication of which threshold was crossed, so hysteresis mode is the natural fit. The lower threshold register is computed internally as (upper - hysteresis). Hysteresis is stored in the driver as a millicelsius value, initialized from the hardware registers at probe. Writing the rising threshold or hysteresis recomputes the lower register. ALARM_CONFIG is hard-coded to hysteresis mode during init. The interrupt handler masks active threshold interrupts (which are level-sensitive) and schedules a delayed worker to poll for condition clear before unmasking. When no hardware IRQ is available, event channels are not created and interrupt init is skipped, since the I2C regmap backend cannot be called from atomic context. When disabling a supply channel alarm, the group interrupt remains active if any other channel in the same alarm group still has an alarm enabled. Signed-off-by: Salih Erim --- Changes in v3: - IWYU: add new includes, group iio headers with blank line (Andy) - Reduce casts in millicelsius_to_q8p7, consistent style with q8p7_to_millicelsius (Andy) - Use clamp_t with typed constants, remove tmp & U16_MAX (Andy) - Use !! to return 0/1 from read_alarm_config (Andy) - Use regmap_set_bits/clear_bits in write_alarm_config (Andy) - Add comment explaining spinlock is safe (I2C never reaches event code path) (Andy) - Add comment explaining IMR negation logic (Andy) - Split read_event_value/write_event_value parameters logically across lines (Andy) - Move mask/shift after regmap_read error check (Andy) - Remove redundant else in read_event_value and write_event_value (Andy) - Use named constant for hysteresis bit, if-else not ternary (Andy) - Loop variable declared in for() scope (Andy) - Add error checks in sysmon_handle_event (Andy) - Use IRQ_RETVAL() macro (Andy) - Use devm_delayed_work_autocancel instead of manual INIT + devm_add_action (Andy) - Use FIELD_GET/FIELD_PREP for hysteresis register bits (Jonathan) - Split OT vs TEMP handling with FIELD_GET (Jonathan) - Rework hysteresis: store as millicelsius value, hardcode ALARM_CONFIG to hysteresis mode, compute lower threshold from (upper - hysteresis), initialize from HW at probe (Jonathan) - Remove falling threshold for temperature; single event spec per channel with IIO_EV_DIR_RISING (Jonathan) - Push IIO_EV_DIR_RISING events for temperature, IIO_EV_DIR_EITHER for voltage (Jonathan) Changes in v2: - Reverse Christmas Tree variable ordering in all functions - Named constants for hysteresis bits: SYSMON_OT_HYST_BIT, SYSMON_TEMP_HYST_BIT instead of magic 0x1/0x2 - SYSMON_ALARM_BITS_PER_REG replaces magic number 32 - SYSMON_ALARM_OFFSET() helper macro deduplicates alarm register offset computation - BIT() macro for shift expressions in conversion functions - Hysteresis input validated to single-bit range (0 or 1) - Event channels only created when irq > 0 (I2C safety) - Group alarm interrupt stays active while any channel in the group has an alarm enabled - write_event_value returns -EINVAL for unhandled types - IRQ_NONE returned for spurious interrupts - Q8.7 write path uses multiplication instead of left-shift to avoid undefined behavior with negative temperatures - (u16) mask prevents garbage in reserved register bits - regmap_write return values checked for IER/IDR writes - devm cleanup ordering: cancel_work before request_irq drivers/iio/adc/versal-sysmon-core.c | 655 ++++++++++++++++++++++++++- drivers/iio/adc/versal-sysmon.h | 48 +- 2 files changed, 697 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/versal-sysmon-core.c b/drivers/iio/adc/versal-= sysmon-core.c index ebe052f6982..04977c9c887 100644 --- a/drivers/iio/adc/versal-sysmon-core.c +++ b/drivers/iio/adc/versal-sysmon-core.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include @@ -18,10 +20,19 @@ #include #include =20 +#include #include =20 #include "versal-sysmon.h" =20 +/* OT and TEMP hysteresis mode bits in SYSMON_TEMP_EV_CFG */ +#define SYSMON_OT_HYST_MASK BIT(0) +#define SYSMON_TEMP_HYST_MASK BIT(1) + +/* Compute alarm register offset from a channel address */ +#define SYSMON_ALARM_OFFSET(addr) \ + (SYSMON_ALARM_REG + ((addr) / SYSMON_ALARM_BITS_PER_REG) * SYSMON_REG_STR= IDE) + /* * Both RAW and PROCESSED are exposed: RAW is needed for event thresholds * (which operate in hardware register format), PROCESSED gives userspace @@ -44,6 +55,62 @@ .datasheet_name =3D _name, \ } =20 +#define SYSMON_CHAN_TEMP_EVENT(_chan, _address, _name, _events) {\ + .type =3D IIO_TEMP, \ + .indexed =3D 1, \ + .address =3D _address, \ + .channel =3D _chan, \ + .event_spec =3D _events, \ + .num_event_specs =3D ARRAY_SIZE(_events), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D 15, \ + .storagebits =3D 16, \ + .endianness =3D IIO_CPU, \ + }, \ + .datasheet_name =3D _name, \ +} + +enum sysmon_alarm_bit { + SYSMON_BIT_ALARM0 =3D 0, + SYSMON_BIT_ALARM1 =3D 1, + SYSMON_BIT_ALARM2 =3D 2, + SYSMON_BIT_ALARM3 =3D 3, + SYSMON_BIT_ALARM4 =3D 4, + SYSMON_BIT_OT =3D 8, + SYSMON_BIT_TEMP =3D 9, +}; + +/* Temperature event specification: rising threshold + hysteresis only */ +static const struct iio_event_spec sysmon_temp_events[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_separate =3D BIT(IIO_EV_INFO_ENABLE) | + BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_HYSTERESIS), + }, +}; + +/* Supply event specifications */ +static const struct iio_event_spec sysmon_supply_events[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_FALLING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_EITHER, + .mask_separate =3D BIT(IIO_EV_INFO_ENABLE), + }, +}; + /* Static temperature channels (always present) */ static const struct iio_chan_spec temp_channels[] =3D { SYSMON_CHAN_TEMP(0, SYSMON_TEMP_MAX, "temp"), @@ -52,11 +119,24 @@ static const struct iio_chan_spec temp_channels[] =3D { SYSMON_CHAN_TEMP(3, SYSMON_TEMP_MIN_MIN, "min_min"), }; =20 +/* Temperature event channels (threshold alarms) */ +static const struct iio_chan_spec temp_event_channels[] =3D { + SYSMON_CHAN_TEMP_EVENT(4, SYSMON_ADDR_TEMP_EVENT, "temp", + sysmon_temp_events), + SYSMON_CHAN_TEMP_EVENT(5, SYSMON_ADDR_OT_EVENT, "ot", + sysmon_temp_events), +}; + static void sysmon_q8p7_to_millicelsius(s16 raw_data, int *val) { *val =3D (raw_data * (int)MILLI) >> SYSMON_FRACTIONAL_SHIFT; } =20 +static void sysmon_millicelsius_to_q8p7(u32 *raw_data, int val) +{ + *raw_data =3D (val << SYSMON_FRACTIONAL_SHIFT) / (int)MILLI; +} + static void sysmon_supply_rawtoprocessed(int raw_data, int *val) { int mantissa, format, exponent; @@ -74,6 +154,49 @@ static void sysmon_supply_rawtoprocessed(int raw_data, = int *val) *val =3D (mantissa * (int)MILLI) >> exponent; } =20 +static void sysmon_supply_processedtoraw(int val, u32 reg_val, u32 *raw_da= ta) +{ + int exponent =3D FIELD_GET(SYSMON_MODE_MASK, reg_val); + int format =3D FIELD_GET(SYSMON_FMT_MASK, reg_val); + int scale, tmp; + + scale =3D BIT(SYSMON_SUPPLY_MANTISSA_BITS - exponent); + tmp =3D (val * scale) / (int)MILLI; + + if (format) + tmp =3D clamp_t(int, tmp, S16_MIN, S16_MAX); + else + tmp =3D clamp_t(int, tmp, 0, U16_MAX); + + *raw_data =3D (u16)tmp; +} + +static int sysmon_temp_thresh_offset(int address, + enum iio_event_direction dir) +{ + switch (address) { + case SYSMON_ADDR_TEMP_EVENT: + return (dir =3D=3D IIO_EV_DIR_RISING) ? SYSMON_TEMP_TH_UP : + SYSMON_TEMP_TH_LOW; + case SYSMON_ADDR_OT_EVENT: + return (dir =3D=3D IIO_EV_DIR_RISING) ? SYSMON_OT_TH_UP : + SYSMON_OT_TH_LOW; + default: + return -EINVAL; + } +} + +static int sysmon_supply_thresh_offset(int address, + enum iio_event_direction dir) +{ + if (dir =3D=3D IIO_EV_DIR_RISING) + return (address * SYSMON_REG_STRIDE) + SYSMON_SUPPLY_TH_UP; + if (dir =3D=3D IIO_EV_DIR_FALLING) + return (address * SYSMON_REG_STRIDE) + SYSMON_SUPPLY_TH_LOW; + + return -EINVAL; +} + static int sysmon_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -115,6 +238,258 @@ static int sysmon_read_raw(struct iio_dev *indio_dev, } } =20 +static int sysmon_get_event_mask(unsigned long address) +{ + if (address =3D=3D SYSMON_ADDR_TEMP_EVENT) + return BIT(SYSMON_BIT_TEMP); + if (address =3D=3D SYSMON_ADDR_OT_EVENT) + return BIT(SYSMON_BIT_OT); + + return BIT(address / SYSMON_ALARM_BITS_PER_REG); +} + +static int sysmon_read_alarm_config(struct sysmon *sysmon, + unsigned long address) +{ + u32 shift =3D address % SYSMON_ALARM_BITS_PER_REG; + u32 offset =3D SYSMON_ALARM_OFFSET(address); + unsigned int reg_val; + int ret; + + ret =3D regmap_read(sysmon->regmap, offset, ®_val); + if (ret) + return ret; + + return !!(reg_val & BIT(shift)); +} + +static int sysmon_write_alarm_config(struct sysmon *sysmon, + unsigned long address, bool enable) +{ + u32 shift =3D address % SYSMON_ALARM_BITS_PER_REG; + u32 offset =3D SYSMON_ALARM_OFFSET(address); + + if (enable) + return regmap_set_bits(sysmon->regmap, offset, BIT(shift)); + + return regmap_clear_bits(sysmon->regmap, offset, BIT(shift)); +} + +static int sysmon_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + u32 alarm_event_mask =3D sysmon_get_event_mask(chan->address); + struct sysmon *sysmon =3D iio_priv(indio_dev); + unsigned int imr; + int config_value; + int ret; + + ret =3D regmap_read(sysmon->regmap, SYSMON_IMR, &imr); + if (ret) + return ret; + + /* IMR bits are 1=3Dmasked, invert to get 1=3Denabled */ + imr =3D ~imr; + + if (chan->type =3D=3D IIO_VOLTAGE) { + config_value =3D sysmon_read_alarm_config(sysmon, chan->address); + if (config_value < 0) + return config_value; + return config_value && (imr & alarm_event_mask); + } + + return !!(imr & alarm_event_mask); +} + +static int sysmon_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + u32 offset =3D SYSMON_ALARM_OFFSET(chan->address); + u32 ier =3D sysmon_get_event_mask(chan->address); + struct sysmon *sysmon =3D iio_priv(indio_dev); + unsigned int alarm_config; + int ret; + + guard(mutex)(&sysmon->lock); + + if (chan->type =3D=3D IIO_VOLTAGE) { + ret =3D sysmon_write_alarm_config(sysmon, chan->address, state); + if (ret) + return ret; + + ret =3D regmap_read(sysmon->regmap, offset, &alarm_config); + if (ret) + return ret; + + if (alarm_config) + return regmap_write(sysmon->regmap, SYSMON_IER, ier); + + return regmap_write(sysmon->regmap, SYSMON_IDR, ier); + } + + if (chan->type =3D=3D IIO_TEMP) { + if (state) { + ret =3D regmap_write(sysmon->regmap, SYSMON_IER, ier); + if (ret) + return ret; + sysmon->temp_mask &=3D ~ier; + } else { + ret =3D regmap_write(sysmon->regmap, SYSMON_IDR, ier); + if (ret) + return ret; + sysmon->temp_mask |=3D ier; + } + } + + return 0; +} + +/* + * Recompute the lower threshold register from upper threshold and + * cached hysteresis. Called when either upper threshold or hysteresis + * is written. + */ +static int sysmon_update_temp_lower(struct sysmon *sysmon, int address) +{ + unsigned int upper_reg; + int upper_mc, lower_mc, hysteresis; + u32 raw_val; + int upper_off, lower_off, ret; + + upper_off =3D sysmon_temp_thresh_offset(address, IIO_EV_DIR_RISING); + if (upper_off < 0) + return upper_off; + lower_off =3D sysmon_temp_thresh_offset(address, IIO_EV_DIR_FALLING); + if (lower_off < 0) + return lower_off; + + if (address =3D=3D SYSMON_ADDR_OT_EVENT) + hysteresis =3D sysmon->ot_hysteresis; + else + hysteresis =3D sysmon->temp_hysteresis; + + ret =3D regmap_read(sysmon->regmap, upper_off, &upper_reg); + if (ret) + return ret; + sysmon_q8p7_to_millicelsius(upper_reg, &upper_mc); + + lower_mc =3D upper_mc - hysteresis; + sysmon_millicelsius_to_q8p7(&raw_val, lower_mc); + + return regmap_write(sysmon->regmap, lower_off, raw_val); +} + +static int sysmon_read_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + struct sysmon *sysmon =3D iio_priv(indio_dev); + unsigned int reg_val; + int offset; + int ret; + + guard(mutex)(&sysmon->lock); + + if (chan->type =3D=3D IIO_TEMP) { + if (info =3D=3D IIO_EV_INFO_VALUE) { + /* Only rising threshold is exposed */ + offset =3D sysmon_temp_thresh_offset(chan->address, + IIO_EV_DIR_RISING); + if (offset < 0) + return offset; + ret =3D regmap_read(sysmon->regmap, offset, ®_val); + if (ret) + return ret; + sysmon_q8p7_to_millicelsius(reg_val, val); + return IIO_VAL_INT; + } + if (info =3D=3D IIO_EV_INFO_HYSTERESIS) { + if (chan->address =3D=3D SYSMON_ADDR_OT_EVENT) + *val =3D sysmon->ot_hysteresis; + else + *val =3D sysmon->temp_hysteresis; + return IIO_VAL_INT; + } + } + + if (chan->type =3D=3D IIO_VOLTAGE) { + offset =3D sysmon_supply_thresh_offset(chan->address, dir); + if (offset < 0) + return offset; + ret =3D regmap_read(sysmon->regmap, offset, ®_val); + if (ret) + return ret; + sysmon_supply_rawtoprocessed(reg_val, val); + return IIO_VAL_INT; + } + + return -EINVAL; +} + +static int sysmon_write_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + struct sysmon *sysmon =3D iio_priv(indio_dev); + unsigned int reg_val; + u32 raw_val; + int offset; + int ret; + + guard(mutex)(&sysmon->lock); + + if (chan->type =3D=3D IIO_TEMP) { + if (info =3D=3D IIO_EV_INFO_VALUE) { + /* Only rising threshold is exposed */ + offset =3D sysmon_temp_thresh_offset(chan->address, + IIO_EV_DIR_RISING); + if (offset < 0) + return offset; + sysmon_millicelsius_to_q8p7(&raw_val, val); + ret =3D regmap_write(sysmon->regmap, offset, raw_val); + if (ret) + return ret; + /* Recompute lower =3D upper - hysteresis */ + return sysmon_update_temp_lower(sysmon, + chan->address); + } + if (info =3D=3D IIO_EV_INFO_HYSTERESIS) { + if (val < 0) + return -EINVAL; + if (chan->address =3D=3D SYSMON_ADDR_OT_EVENT) + sysmon->ot_hysteresis =3D val; + else + sysmon->temp_hysteresis =3D val; + return sysmon_update_temp_lower(sysmon, + chan->address); + } + } + + if (chan->type =3D=3D IIO_VOLTAGE) { + offset =3D sysmon_supply_thresh_offset(chan->address, dir); + if (offset < 0) + return offset; + ret =3D regmap_read(sysmon->regmap, offset, ®_val); + if (ret) + return ret; + sysmon_supply_processedtoraw(val, reg_val, &raw_val); + return regmap_write(sysmon->regmap, offset, raw_val); + } + + return -EINVAL; +} + static int sysmon_read_label(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, char *label) @@ -128,20 +503,248 @@ static int sysmon_read_label(struct iio_dev *indio_d= ev, static const struct iio_info sysmon_iio_info =3D { .read_raw =3D sysmon_read_raw, .read_label =3D sysmon_read_label, + .read_event_config =3D sysmon_read_event_config, + .write_event_config =3D sysmon_write_event_config, + .read_event_value =3D sysmon_read_event_value, + .write_event_value =3D sysmon_write_event_value, }; =20 +static void sysmon_push_event(struct iio_dev *indio_dev, u32 address) +{ + const struct iio_chan_spec *chan; + enum iio_event_direction dir; + + for (unsigned int i =3D 0; i < indio_dev->num_channels; i++) { + if (indio_dev->channels[i].address !=3D address) + continue; + + chan =3D &indio_dev->channels[i]; + /* Temp uses hysteresis mode (rising only), voltage uses window */ + dir =3D (chan->type =3D=3D IIO_TEMP) ? IIO_EV_DIR_RISING : + IIO_EV_DIR_EITHER; + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(chan->type, + chan->channel, + IIO_EV_TYPE_THRESH, + dir), + iio_get_time_ns(indio_dev)); + } +} + +static int sysmon_handle_event(struct iio_dev *indio_dev, u32 event) +{ + u32 alarm_flag_offset =3D SYSMON_ALARM_FLAG + (event * SYSMON_REG_STRIDE); + u32 alarm_reg_offset =3D SYSMON_ALARM_REG + (event * SYSMON_REG_STRIDE); + struct sysmon *sysmon =3D iio_priv(indio_dev); + unsigned long alarm_flag_reg; + unsigned int reg_val; + u32 address, bit; + int ret; + + switch (event) { + case SYSMON_BIT_TEMP: + sysmon_push_event(indio_dev, SYSMON_ADDR_TEMP_EVENT); + ret =3D regmap_write(sysmon->regmap, SYSMON_IDR, + BIT(SYSMON_BIT_TEMP)); + if (ret) + return ret; + sysmon->masked_temp |=3D BIT(SYSMON_BIT_TEMP); + break; + + case SYSMON_BIT_OT: + sysmon_push_event(indio_dev, SYSMON_ADDR_OT_EVENT); + ret =3D regmap_write(sysmon->regmap, SYSMON_IDR, + BIT(SYSMON_BIT_OT)); + if (ret) + return ret; + sysmon->masked_temp |=3D BIT(SYSMON_BIT_OT); + break; + + case SYSMON_BIT_ALARM0: + case SYSMON_BIT_ALARM1: + case SYSMON_BIT_ALARM2: + case SYSMON_BIT_ALARM3: + case SYSMON_BIT_ALARM4: + ret =3D regmap_read(sysmon->regmap, alarm_flag_offset, ®_val); + if (ret) + return ret; + alarm_flag_reg =3D reg_val; + + for_each_set_bit(bit, &alarm_flag_reg, + SYSMON_ALARM_BITS_PER_REG) { + address =3D bit + (SYSMON_ALARM_BITS_PER_REG * event); + sysmon_push_event(indio_dev, address); + ret =3D regmap_update_bits(sysmon->regmap, + alarm_reg_offset, + BIT(bit), 0); + if (ret) + return ret; + } + ret =3D regmap_write(sysmon->regmap, alarm_flag_offset, + alarm_flag_reg); + if (ret) + return ret; + break; + + default: + break; + } + + return 0; +} + +static void sysmon_handle_events(struct iio_dev *indio_dev, + unsigned long events) +{ + unsigned int bit; + + for_each_set_bit(bit, &events, SYSMON_NO_OF_EVENTS) + sysmon_handle_event(indio_dev, bit); +} + +static void sysmon_unmask_temp(struct sysmon *sysmon, unsigned int isr) +{ + unsigned int unmask, status; + + status =3D isr & SYSMON_TEMP_INTR_MASK; + + unmask =3D (sysmon->masked_temp ^ status) & sysmon->masked_temp; + sysmon->masked_temp &=3D status; + + unmask &=3D ~sysmon->temp_mask; + + regmap_write(sysmon->regmap, SYSMON_IER, unmask); +} + +/* + * Versal threshold interrupts are level-sensitive. Active threshold + * interrupts are masked in the handler and polled via delayed work + * until the condition clears, then unmasked. + */ +static void sysmon_unmask_worker(struct work_struct *work) +{ + struct sysmon *sysmon =3D container_of(work, struct sysmon, + sysmon_unmask_work.work); + unsigned int isr; + + spin_lock_irq(&sysmon->irq_lock); + regmap_read(sysmon->regmap, SYSMON_ISR, &isr); + regmap_write(sysmon->regmap, SYSMON_ISR, isr); + sysmon_unmask_temp(sysmon, isr); + spin_unlock_irq(&sysmon->irq_lock); + + if (sysmon->masked_temp) + schedule_delayed_work(&sysmon->sysmon_unmask_work, + msecs_to_jiffies(SYSMON_UNMASK_WORK_DELAY_MS)); + else + regmap_write(sysmon->regmap, SYSMON_STATUS_RESET, 1); +} + +static irqreturn_t sysmon_iio_irq(int irq, void *data) +{ + struct iio_dev *indio_dev =3D data; + struct sysmon *sysmon; + unsigned int isr, imr; + + sysmon =3D iio_priv(indio_dev); + spin_lock(&sysmon->irq_lock); + + regmap_read(sysmon->regmap, SYSMON_ISR, &isr); + regmap_read(sysmon->regmap, SYSMON_IMR, &imr); + + isr &=3D ~imr; + regmap_write(sysmon->regmap, SYSMON_ISR, isr); + + if (isr) { + sysmon_handle_events(indio_dev, isr); + schedule_delayed_work(&sysmon->sysmon_unmask_work, + msecs_to_jiffies(SYSMON_UNMASK_WORK_DELAY_MS)); + } + + spin_unlock(&sysmon->irq_lock); + + return IRQ_RETVAL(isr); +} + +static int sysmon_init_interrupt(struct sysmon *sysmon, + struct device *dev, + struct iio_dev *indio_dev, + int irq) +{ + unsigned int imr; + int ret; + + /* Events not supported without IRQ (e.g. I2C path) */ + if (!irq) + return 0; + + ret =3D devm_delayed_work_autocancel(dev, &sysmon->sysmon_unmask_work, + sysmon_unmask_worker); + if (ret) + return ret; + + ret =3D regmap_read(sysmon->regmap, SYSMON_IMR, &imr); + if (ret) + return ret; + sysmon->temp_mask =3D imr & SYSMON_TEMP_INTR_MASK; + + return devm_request_irq(dev, irq, sysmon_iio_irq, 0, + "sysmon-irq", indio_dev); +} + +/* + * Initialize the cached hysteresis for a temperature channel from the + * current hardware threshold registers: hysteresis =3D upper - lower. + */ +static int sysmon_init_hysteresis(struct sysmon *sysmon, int address, + int *hysteresis) +{ + unsigned int upper_reg, lower_reg; + int upper_mc, lower_mc; + int upper_off, lower_off; + int ret; + + upper_off =3D sysmon_temp_thresh_offset(address, IIO_EV_DIR_RISING); + if (upper_off < 0) + return upper_off; + lower_off =3D sysmon_temp_thresh_offset(address, IIO_EV_DIR_FALLING); + if (lower_off < 0) + return lower_off; + + ret =3D regmap_read(sysmon->regmap, upper_off, &upper_reg); + if (ret) + return ret; + ret =3D regmap_read(sysmon->regmap, lower_off, &lower_reg); + if (ret) + return ret; + + sysmon_q8p7_to_millicelsius(upper_reg, &upper_mc); + sysmon_q8p7_to_millicelsius(lower_reg, &lower_mc); + *hysteresis =3D upper_mc - lower_mc; + + return 0; +} + /** * sysmon_parse_fw() - Parse firmware nodes and configure IIO channels. * @indio_dev: IIO device instance * @dev: Parent device + * @has_irq: true if an IRQ is available (enables event channels) * * Reads voltage-channels and temperature-channels container nodes from * firmware and builds the IIO channel array. Static temperature channels - * are prepended, followed by supply and satellite channels from DT. + * and event channels are prepended, followed by supply and satellite + * channels from DT. + * + * Event channels and per-channel event specs are only added when the + * device has an IRQ. I2C devices have no interrupt line, and the I2C + * regmap cannot be called from atomic context, so events are not + * supported on that path. * * Return: 0 on success, negative errno on failure. */ -static int sysmon_parse_fw(struct iio_dev *indio_dev, struct device *dev) +static int sysmon_parse_fw(struct iio_dev *indio_dev, struct device *dev, + bool has_irq) { struct fwnode_handle *supply_node __free(fwnode_handle) =3D device_get_named_child_node(dev, "voltage-channels"); @@ -150,6 +753,7 @@ static int sysmon_parse_fw(struct iio_dev *indio_dev, s= truct device *dev) unsigned int num_supply =3D 0, num_temp =3D 0; unsigned int idx, temp_chan_idx, volt_chan_idx; struct iio_chan_spec *sysmon_channels; + unsigned int num_events; const char *label; u32 reg; int ret; @@ -159,8 +763,11 @@ static int sysmon_parse_fw(struct iio_dev *indio_dev, = struct device *dev) if (temp_node) num_temp =3D fwnode_get_child_node_count(temp_node); =20 + num_events =3D has_irq ? ARRAY_SIZE(temp_event_channels) : 0; + sysmon_channels =3D devm_kcalloc(dev, - size_add(ARRAY_SIZE(temp_channels), + size_add(ARRAY_SIZE(temp_channels) + + num_events, num_supply + num_temp), sizeof(*sysmon_channels), GFP_KERNEL); if (!sysmon_channels) @@ -171,6 +778,13 @@ static int sysmon_parse_fw(struct iio_dev *indio_dev, = struct device *dev) memcpy(sysmon_channels, temp_channels, sizeof(temp_channels)); idx +=3D ARRAY_SIZE(temp_channels); =20 + /* Temperature event channels (only when IRQ is available) */ + if (has_irq) { + memcpy(sysmon_channels + idx, temp_event_channels, + sizeof(temp_event_channels)); + idx +=3D ARRAY_SIZE(temp_event_channels); + } + /* Supply channels from DT */ fwnode_for_each_child_node_scoped(supply_node, child) { ret =3D fwnode_property_read_u32(child, "reg", ®); @@ -195,6 +809,10 @@ static int sysmon_parse_fw(struct iio_dev *indio_dev, = struct device *dev) .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED), + .event_spec =3D has_irq ? + sysmon_supply_events : NULL, + .num_event_specs =3D has_irq ? + ARRAY_SIZE(sysmon_supply_events) : 0, .scan_type =3D { .realbits =3D 19, .storagebits =3D 32, @@ -274,6 +892,8 @@ int sysmon_core_probe(struct device *dev, struct regmap= *regmap) { struct iio_dev *indio_dev; struct sysmon *sysmon; + bool has_irq; + int irq; int ret; =20 indio_dev =3D devm_iio_device_alloc(dev, sizeof(*sysmon)); @@ -286,6 +906,7 @@ int sysmon_core_probe(struct device *dev, struct regmap= *regmap) ret =3D devm_mutex_init(dev, &sysmon->lock); if (ret) return ret; + spin_lock_init(&sysmon->irq_lock); =20 /* Disable all interrupts and clear pending status */ ret =3D regmap_write(sysmon->regmap, SYSMON_IDR, SYSMON_INTR_ALL_MASK); @@ -295,13 +916,39 @@ int sysmon_core_probe(struct device *dev, struct regm= ap *regmap) if (ret) return ret; =20 + irq =3D fwnode_irq_get(dev_fwnode(dev), 0); + has_irq =3D irq > 0; + indio_dev->name =3D "versal-sysmon"; indio_dev->modes =3D INDIO_DIRECT_MODE; =20 - ret =3D sysmon_parse_fw(indio_dev, dev); + ret =3D sysmon_parse_fw(indio_dev, dev, has_irq); if (ret) return ret; =20 + if (has_irq) { + /* Set hysteresis mode for both temperature channels */ + ret =3D regmap_set_bits(sysmon->regmap, SYSMON_TEMP_EV_CFG, + SYSMON_OT_HYST_MASK | + SYSMON_TEMP_HYST_MASK); + if (ret) + return ret; + + /* Initialize cached hysteresis from hardware registers */ + ret =3D sysmon_init_hysteresis(sysmon, SYSMON_ADDR_TEMP_EVENT, + &sysmon->temp_hysteresis); + if (ret) + return ret; + ret =3D sysmon_init_hysteresis(sysmon, SYSMON_ADDR_OT_EVENT, + &sysmon->ot_hysteresis); + if (ret) + return ret; + + ret =3D sysmon_init_interrupt(sysmon, dev, indio_dev, irq); + if (ret) + return ret; + } + return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_GPL(sysmon_core_probe); diff --git a/drivers/iio/adc/versal-sysmon.h b/drivers/iio/adc/versal-sysmo= n.h index d24d2481915..a78362f95e6 100644 --- a/drivers/iio/adc/versal-sysmon.h +++ b/drivers/iio/adc/versal-sysmon.h @@ -11,7 +11,9 @@ =20 #include #include +#include #include +#include =20 struct device; struct iio_dev; @@ -20,12 +22,24 @@ struct regmap; /* Register offsets (sorted by address) */ #define SYSMON_NPI_LOCK 0x000C #define SYSMON_ISR 0x0044 +#define SYSMON_IMR 0x0048 +#define SYSMON_IER 0x004C #define SYSMON_IDR 0x0050 #define SYSMON_TEMP_MAX 0x1030 #define SYSMON_TEMP_MIN 0x1034 #define SYSMON_SUPPLY_BASE 0x1040 +#define SYSMON_ALARM_FLAG 0x1018 +#define SYSMON_ALARM_REG 0x1940 +#define SYSMON_TEMP_TH_LOW 0x1970 +#define SYSMON_TEMP_TH_UP 0x1974 +#define SYSMON_OT_TH_LOW 0x1978 +#define SYSMON_OT_TH_UP 0x197C +#define SYSMON_SUPPLY_TH_LOW 0x1980 +#define SYSMON_SUPPLY_TH_UP 0x1C80 +#define SYSMON_TEMP_EV_CFG 0x1F84 #define SYSMON_TEMP_MIN_MIN 0x1F8C #define SYSMON_TEMP_MAX_MAX 0x1F90 +#define SYSMON_STATUS_RESET 0x1F94 #define SYSMON_TEMP_SAT_BASE 0x1FAC #define SYSMON_MAX_REG 0x24C0 =20 @@ -37,8 +51,12 @@ struct regmap; =20 #define SYSMON_SUPPLY_IDX_MAX 159 #define SYSMON_TEMP_SAT_MAX 64 +#define SYSMON_NO_OF_EVENTS 32 #define SYSMON_INTR_ALL_MASK GENMASK(31, 0) =20 +/* ISR/IMR temperature and OT alarm mask (bits 9:8) */ +#define SYSMON_TEMP_INTR_MASK GENMASK(9, 8) + /* Supply voltage conversion register fields */ #define SYSMON_MANTISSA_MASK GENMASK(15, 0) #define SYSMON_FMT_MASK BIT(16) @@ -48,15 +66,41 @@ struct regmap; #define SYSMON_FRACTIONAL_SHIFT 7U #define SYSMON_SUPPLY_MANTISSA_BITS 16 =20 +/* Event address IDs for temp event channels */ +#define SYSMON_ADDR_TEMP_EVENT 160 +#define SYSMON_ADDR_OT_EVENT 161 + +/* Bits per alarm register */ +#define SYSMON_ALARM_BITS_PER_REG 32 + +#define SYSMON_UNMASK_WORK_DELAY_MS 500 + /** * struct sysmon - Driver data for Versal SysMon * @regmap: register map for hardware access - * @lock: protects regmap access + * @lock: protects regmap access and cached state + * @irq_lock: protects interrupt mask register updates (MMIO path only) + * @masked_temp: currently masked temperature alarm bits + * @temp_mask: temperature interrupt configuration mask + * @temp_hysteresis: cached DEVICE_TEMP hysteresis in millicelsius + * @ot_hysteresis: cached OT hysteresis in millicelsius + * @sysmon_unmask_work: re-enables events after alarm condition clears */ struct sysmon { struct regmap *regmap; - /* Protects regmap access */ + /* Protects regmap access and cached state */ struct mutex lock; + /* + * Protects interrupt mask register updates. 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Wed, 27 May 2026 06:42:26 -0500 From: Salih Erim To: Jonathan Cameron , Andy Shevchenko CC: David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Conall O'Griofa , Michal Simek , Guenter Roeck , Salih Erim , , , , Salih Erim Subject: [PATCH v3 5/5] iio: adc: versal-sysmon: add oversampling support Date: Wed, 27 May 2026 12:42:11 +0100 Message-ID: <20260527114211.174288-6-salih.erim@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260527114211.174288-1-salih.erim@amd.com> References: <20260527114211.174288-1-salih.erim@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|SJ1PR12MB6266:EE_ X-MS-Office365-Filtering-Correlation-Id: bc807d91-6427-4f25-41b9-08debbe50865 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700016|18002099003|22082099003|6133799003|11063799006|56012099006; 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charset="utf-8" Add support for reading and writing the oversampling ratio through the IIO oversampling_ratio attribute. The hardware supports averaging 2, 4, 8, or 16 samples, plus a ratio of 1 (no averaging). Temperature and supply channels share oversampling configuration at the type level (all temperature channels share one ratio, all supply channels share another), exposed through info_mask_shared_by_type. The hardware encoding uses sample_count / 2 in a 4-bit field within the CONFIG register. Per-channel averaging enable registers must also be updated to activate or deactivate averaging. Signed-off-by: Salih Erim --- Changes in v3: - No changes Changes in v2: - EN_AVG per-channel bitmask registers written with all-ones instead of boolean 1 when oversampling is enabled - EN_AVG write errors propagated to userspace - Oversampling limited to satellite temp and supply channels; static temp channels do not participate - Oversampling exposes actual sample counts (1,2,4,8,16) to userspace with internal HW register translation - write_raw_get_fmt returns IIO_VAL_INT for oversampling ratio - HW encoding documented (sample_count/2, not log2) - oversampling_avail is const int[] (type match fix) drivers/iio/adc/versal-sysmon-core.c | 136 +++++++++++++++++++++++++++ drivers/iio/adc/versal-sysmon.h | 17 ++++ 2 files changed, 153 insertions(+) diff --git a/drivers/iio/adc/versal-sysmon-core.c b/drivers/iio/adc/versal-= sysmon-core.c index 04977c9c887..7775a4cfa6d 100644 --- a/drivers/iio/adc/versal-sysmon-core.c +++ b/drivers/iio/adc/versal-sysmon-core.c @@ -25,6 +25,12 @@ =20 #include "versal-sysmon.h" =20 +/* + * Oversampling ratio values exposed to userspace via IIO. + * Actual number of samples averaged: 1=3Dnone, 2=3D2x, 4=3D4x, 8=3D8x, 16= =3D16x. + */ +static const int sysmon_oversampling_avail[] =3D { 1, 2, 4, 8, 16 }; + /* OT and TEMP hysteresis mode bits in SYSMON_TEMP_EV_CFG */ #define SYSMON_OT_HYST_MASK BIT(0) #define SYSMON_TEMP_HYST_MASK BIT(1) @@ -205,6 +211,12 @@ static int sysmon_read_raw(struct iio_dev *indio_dev, unsigned int regval; int ret; =20 + if (mask =3D=3D IIO_CHAN_INFO_OVERSAMPLING_RATIO) { + *val =3D (chan->type =3D=3D IIO_TEMP) ? sysmon->temp_oversampling : + sysmon->supply_oversampling; + return IIO_VAL_INT; + } + if (mask !=3D IIO_CHAN_INFO_RAW && mask !=3D IIO_CHAN_INFO_PROCESSED) return -EINVAL; =20 @@ -490,6 +502,117 @@ static int sysmon_write_event_value(struct iio_dev *i= ndio_dev, return -EINVAL; } =20 +static int sysmon_set_avg_enable(struct sysmon *sysmon, + u32 base, u32 count, u32 val) +{ + int ret; + + for (unsigned int i =3D 0; i < count; i++) { + ret =3D regmap_write(sysmon->regmap, + base + (i * SYSMON_REG_STRIDE), val); + if (ret) + return ret; + } + + return 0; +} + +static int sysmon_osr_write(struct sysmon *sysmon, int channel_type, int v= al) +{ + /* + * HW register encoding is sample_count / 2: + * 0=3Dnone, 1=3D2x, 2=3D4x, 4=3D8x, 8=3D16x (not log2-based). + */ + int hw_val =3D val >> 1; + int ret; + + if (channel_type =3D=3D IIO_TEMP) { + ret =3D regmap_update_bits(sysmon->regmap, SYSMON_CONFIG, + SYSMON_TEMP_SAT_CONFIG_MASK, + FIELD_PREP(SYSMON_TEMP_SAT_CONFIG_MASK, + hw_val)); + if (ret) + return ret; + ret =3D sysmon_set_avg_enable(sysmon, SYSMON_TEMP_EN_AVG_BASE, + SYSMON_TEMP_EN_AVG_COUNT, + hw_val ? ~0U : 0); + if (ret) + return ret; + } else if (channel_type =3D=3D IIO_VOLTAGE) { + ret =3D regmap_update_bits(sysmon->regmap, SYSMON_CONFIG, + SYSMON_SUPPLY_CONFIG_MASK, + FIELD_PREP(SYSMON_SUPPLY_CONFIG_MASK, + hw_val)); + if (ret) + return ret; + ret =3D sysmon_set_avg_enable(sysmon, SYSMON_SUPPLY_EN_AVG_BASE, + SYSMON_SUPPLY_EN_AVG_COUNT, + hw_val ? ~0U : 0); + if (ret) + return ret; + } else { + return -EINVAL; + } + + return 0; +} + +static int sysmon_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct sysmon *sysmon =3D iio_priv(indio_dev); + int i, ret; + + if (mask !=3D IIO_CHAN_INFO_OVERSAMPLING_RATIO) + return -EINVAL; + + for (i =3D 0; i < ARRAY_SIZE(sysmon_oversampling_avail); i++) { + if (val =3D=3D sysmon_oversampling_avail[i]) + break; + } + if (i =3D=3D ARRAY_SIZE(sysmon_oversampling_avail)) + return -EINVAL; + + guard(mutex)(&sysmon->lock); + + ret =3D sysmon_osr_write(sysmon, chan->type, val); + if (ret) + return ret; + + if (chan->type =3D=3D IIO_TEMP) + sysmon->temp_oversampling =3D val; + else + sysmon->supply_oversampling =3D val; + + return 0; +} + +static int sysmon_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + if (mask =3D=3D IIO_CHAN_INFO_OVERSAMPLING_RATIO) + return IIO_VAL_INT; + + return -EINVAL; +} + +static int sysmon_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, + int *length, long mask) +{ + if (mask !=3D IIO_CHAN_INFO_OVERSAMPLING_RATIO) + return -EINVAL; + + *vals =3D sysmon_oversampling_avail; + *type =3D IIO_VAL_INT; + *length =3D ARRAY_SIZE(sysmon_oversampling_avail); + + return IIO_AVAIL_LIST; +} + static int sysmon_read_label(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, char *label) @@ -502,6 +625,9 @@ static int sysmon_read_label(struct iio_dev *indio_dev, =20 static const struct iio_info sysmon_iio_info =3D { .read_raw =3D sysmon_read_raw, + .write_raw =3D sysmon_write_raw, + .write_raw_get_fmt =3D sysmon_write_raw_get_fmt, + .read_avail =3D sysmon_read_avail, .read_label =3D sysmon_read_label, .read_event_config =3D sysmon_read_event_config, .write_event_config =3D sysmon_write_event_config, @@ -809,6 +935,10 @@ static int sysmon_parse_fw(struct iio_dev *indio_dev, = struct device *dev, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED), + .info_mask_shared_by_type =3D + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_type_available =3D + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), .event_spec =3D has_irq ? sysmon_supply_events : NULL, .num_event_specs =3D has_irq ? @@ -849,6 +979,10 @@ static int sysmon_parse_fw(struct iio_dev *indio_dev, = struct device *dev, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED), + .info_mask_shared_by_type =3D + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_type_available =3D + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), .scan_type =3D { .sign =3D 's', .realbits =3D 15, @@ -902,6 +1036,8 @@ int sysmon_core_probe(struct device *dev, struct regma= p *regmap) =20 sysmon =3D iio_priv(indio_dev); sysmon->regmap =3D regmap; + sysmon->temp_oversampling =3D 1; + sysmon->supply_oversampling =3D 1; =20 ret =3D devm_mutex_init(dev, &sysmon->lock); if (ret) diff --git a/drivers/iio/adc/versal-sysmon.h b/drivers/iio/adc/versal-sysmo= n.h index a78362f95e6..cf69be62709 100644 --- a/drivers/iio/adc/versal-sysmon.h +++ b/drivers/iio/adc/versal-sysmon.h @@ -25,11 +25,13 @@ struct regmap; #define SYSMON_IMR 0x0048 #define SYSMON_IER 0x004C #define SYSMON_IDR 0x0050 +#define SYSMON_CONFIG 0x0100 #define SYSMON_TEMP_MAX 0x1030 #define SYSMON_TEMP_MIN 0x1034 #define SYSMON_SUPPLY_BASE 0x1040 #define SYSMON_ALARM_FLAG 0x1018 #define SYSMON_ALARM_REG 0x1940 +#define SYSMON_SUPPLY_EN_AVG_BASE 0x1958 #define SYSMON_TEMP_TH_LOW 0x1970 #define SYSMON_TEMP_TH_UP 0x1974 #define SYSMON_OT_TH_LOW 0x1978 @@ -41,6 +43,7 @@ struct regmap; #define SYSMON_TEMP_MAX_MAX 0x1F90 #define SYSMON_STATUS_RESET 0x1F94 #define SYSMON_TEMP_SAT_BASE 0x1FAC +#define SYSMON_TEMP_EN_AVG_BASE 0x24B4 #define SYSMON_MAX_REG 0x24C0 =20 /* NPI unlock value written to SYSMON_NPI_LOCK */ @@ -57,6 +60,16 @@ struct regmap; /* ISR/IMR temperature and OT alarm mask (bits 9:8) */ #define SYSMON_TEMP_INTR_MASK GENMASK(9, 8) =20 +/* Config register: supply oversampling field (bits 17:14) */ +#define SYSMON_SUPPLY_CONFIG_MASK GENMASK(17, 14) + +/* Config register: temp satellite oversampling field (bits 27:24) */ +#define SYSMON_TEMP_SAT_CONFIG_MASK GENMASK(27, 24) + +/* Per-channel averaging enable register counts */ +#define SYSMON_SUPPLY_EN_AVG_COUNT 5 +#define SYSMON_TEMP_EN_AVG_COUNT 2 + /* Supply voltage conversion register fields */ #define SYSMON_MANTISSA_MASK GENMASK(15, 0) #define SYSMON_FMT_MASK BIT(16) @@ -85,6 +98,8 @@ struct regmap; * @temp_hysteresis: cached DEVICE_TEMP hysteresis in millicelsius * @ot_hysteresis: cached OT hysteresis in millicelsius * @sysmon_unmask_work: re-enables events after alarm condition clears + * @temp_oversampling: current temp oversampling ratio + * @supply_oversampling: current supply oversampling ratio */ struct sysmon { struct regmap *regmap; @@ -101,6 +116,8 @@ struct sysmon { int temp_hysteresis; int ot_hysteresis; struct delayed_work sysmon_unmask_work; + unsigned int temp_oversampling; + unsigned int supply_oversampling; }; =20 int sysmon_core_probe(struct device *dev, struct regmap *regmap); --=20 2.48.1