From nobody Mon Jun 8 18:55:25 2026 Received: from mail-qt1-f175.google.com (mail-qt1-f175.google.com [209.85.160.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 207DA3EF655 for ; Wed, 27 May 2026 10:00:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779876034; cv=none; b=B1Kj4hL6BjyTMKbAPOjeAr63n8uhEmB32rCxt44V7jnUwycDdUL5bUlSQn3RRU6QgpZEUHPEpyb3d4K6bAa593whmpC6MY5xYkQVHik9PNAkZiMl2kFpiCdDuX+RuReE4gIJmKxxkic/Hs3xw1/YqUfwsIjbYcMgm1aTdEeVOzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779876034; c=relaxed/simple; bh=r2Oc/r+PMuNLixSl7YLDQDpNQPpFD2m4Iu3WX55tZww=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=bJav+sOZiYmnPN7IFGW1pCVEw6mw0BfJ6TWE269fv22iI6ql0ylcXopDBDQMWhhSM8MEc9lgKuKD0bQ77UvC8bJ3SQ3FlC/oTMMXrK/359ub33bzJXJyc49nOmfmHO8jwynGfKrwgFZNW4vqRbEaIepSPewrF9MI6or3uaG23sk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NXhOb7Z6; arc=none smtp.client-ip=209.85.160.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NXhOb7Z6" Received: by mail-qt1-f175.google.com with SMTP id d75a77b69052e-512f750d4b2so123672611cf.1 for ; Wed, 27 May 2026 03:00:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779876031; x=1780480831; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=TYYX7F9TU2UqvnQ4rqTvcIfA7/lt//2BpmT7qAbp7ck=; b=NXhOb7Z6k/J2unCfvD3Mkpe/T9b9R80kmfQI/NVQcms/4MQhfE19m0NB3NUAI2aiZt 7Cr1Z0u3/+Z/1/6G4VO1Ay6rEnzVzTWnffg7lwVY0cIxeD2Flyf2jmgpz0BhoGHGTsO2 M2BGdQMO2kBzTyKIm68SkI59Fam0oWTlrUdn90H2Hc/BOh/HoOpGLUOl+lXMReqFoMwi +GDVJS9DtCfBtcwadn/rFU0zTSBuTmDgvchDpKrLStGucOhphYJ2mwtBrgS0uMygG9Hd YhyQnCcP+eMSjq5ngj1vN+MSLz0e7gdmNtI5Y7tSRsKthAysqG9OMN2NUszFF+5+TA8Z rgqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779876031; x=1780480831; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=TYYX7F9TU2UqvnQ4rqTvcIfA7/lt//2BpmT7qAbp7ck=; b=TVw8jg+sylY12K2yiipqD2+6iDvdpWN6NMaE6QsYAv0XXFhnJ7f4kuWXbI7IQCcAPL pCBF3ub5bCJXlzprQbABn199wxJCecKT2kbA9AVKqxfKOpuzDZxZ0lufI+isLO8KhEAV AVZpPFaieiMp81JXgEl9sVjluqAW6yst00NjRFKA3072krEN+6EqdBf2keCKgkF2lUbg WCGVtKxRSEmnh4PlzXMsh3TyMbU6jXB6GHgpeoX614ph8J8vGpNoFZ7sgD+hL6rNqv6O Gzbf9VkCshUcSbB4GfccH7xSguezuUoEujXalbCOnBtkV0GHmWwjVWjKGjjj1eGmprYz Q8Ug== X-Forwarded-Encrypted: i=1; AFNElJ+mlkLPndSCWPSKKT3zDqsGXjXUN0RbsUescuE9413k9RWq49hqlDIXMqoNksaFWMKbKdC6ypphivG8waQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzExKQ9Uf5b5MJGcdkT4WCdmCYAoK+ZpbMO1cyvN0dcuIAR2MCZ odhABf03CWh6c9BhJo8IT0TZdQVFgBjvQ2s7vqDyyRCeUnGDQ34m1Baj X-Gm-Gg: Acq92OEo8P+LR64YzCDfn7zUuStQ3+sa++KAB+mTRyKP0X5bRbFBIWB8Gk8HTXJihc8 jK4JRYJU7XZiohMN/ytd9+rEp4Yq0V2Qa64ZPd9yMFBTovb/LXl8cH9FKLgBlFUVKfBj4urYG8s 4H1kMNSzS+XplIB3p66OJkI/V/kNgpN8IUcdFMenRdke7OvgDLltVWokHIAINwhr+vEJF3cjKrG xfuaE2C1hiG48PB0ZnMIN/9PglbFoyZb8Xr3px5uRCnNJ78EaZ++Jmrzg+tfWf9LZ/fWrGjMECB svl87zETY5tjfGuSWN+Y0UnupIV5uMLxjNf1LwdwcszWP7/nSeUSGJ9j98ph8hrk7JwDfKF8AtD e17ArWWOVdzIsFfCmcHQoGpeZPaowyfJ5or8EbJm4fCI2IlVD/T2CrsTjb9wkKYtweAypTDvztw VDb+SNF7bOT+/fy4cpzcNfuuwC7joOmwFDj1Sc2s7DxSYUmX26Kj6IV9bmZbw8ovdzO5KvW5gUM OmyAA== X-Received: by 2002:a05:622a:350:b0:50f:b724:85e3 with SMTP id d75a77b69052e-516d42bfc09mr313428371cf.17.1779876030931; Wed, 27 May 2026 03:00:30 -0700 (PDT) Received: from localhost.localdomain ([94.156.149.59]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51706adc63dsm39366011cf.16.2026.05.27.03.00.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 03:00:30 -0700 (PDT) From: Qing Wu To: ses1er@gmail.com Cc: Miquel Raynal , Michal Simek , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] mtd: spinand: dosilicon: Add support for additional models Date: Wed, 27 May 2026 06:00:21 -0400 Message-ID: <20260527100021.76247-1-ses1er@gmail.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for additional Dosilicon SPI NAND chips. Datasheets for chips included in this patch: https://www.dosilicon.com/SPI%= 20NAND%20Flash.html Tested on a TP-Link TL-7DR7250 with a Dosilicon DS35Q1GB (0xE5 0xF1) Signed-off-by: Qing Wu --- Changes in v3: - Changed title - Updated 2 bytes for BBM - Link to v2: https://lore.kernel.org/all/20260520003733.82514-1-ses1er@gma= il.com/ Changes in v2: - Fixed compilation errors. - Link to v1: https://lore.kernel.org/all/20260217211427.9120-1-ses1er@gmai= l.com --- drivers/mtd/nand/spi/dosilicon.c | 218 ++++++++++++++++++++++++++++--- 1 file changed, 203 insertions(+), 15 deletions(-) diff --git a/drivers/mtd/nand/spi/dosilicon.c b/drivers/mtd/nand/spi/dosili= con.c index f99899866ceb..fcd967c1bcbc 100644 --- a/drivers/mtd/nand/spi/dosilicon.c +++ b/drivers/mtd/nand/spi/dosilicon.c @@ -9,21 +9,27 @@ =20 #define SPINAND_MFR_DOSILICON 0xE5 =20 +#define DOSICON_STATUS_ECC_MASK GENMASK(6, 4) +#define DOSICON_STATUS_ECC_NO_BITFLIPS (0 << 4) +#define DOSICON_STATUS_ECC_1TO3_BITFLIPS (1 << 4) +#define DOSICON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) +#define DOSICON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) + static SPINAND_OP_VARIANTS(read_cache_variants, - SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0), - SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0, 0), - SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0), - SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0)); + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); =20 static SPINAND_OP_VARIANTS(write_cache_variants, - SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0), - SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0)); + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); =20 static SPINAND_OP_VARIANTS(update_cache_variants, - SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), - SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); =20 -static int ds35xx_ooblayout_ecc(struct mtd_info *mtd, int section, +static int ds35xxga_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { if (section > 3) @@ -35,7 +41,7 @@ static int ds35xx_ooblayout_ecc(struct mtd_info *mtd, int= section, return 0; } =20 -static int ds35xx_ooblayout_free(struct mtd_info *mtd, int section, +static int ds35xxga_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { if (section > 3) @@ -53,11 +59,67 @@ static int ds35xx_ooblayout_free(struct mtd_info *mtd, = int section, return 0; } =20 -static const struct mtd_ooblayout_ops ds35xx_ooblayout =3D { - .ecc =3D ds35xx_ooblayout_ecc, - .free =3D ds35xx_ooblayout_free, +static const struct mtd_ooblayout_ops ds35xxga_ooblayout =3D { + .ecc =3D ds35xxga_ooblayout_ecc, + .free =3D ds35xxga_ooblayout_free, }; =20 +static int ds35xxgb_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset =3D 64; + region->length =3D 64; + + return 0; +} + +static int ds35xxgb_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* Reserve 2 bytes for the BBM. */ + region->offset =3D 2; + region->length =3D 62; + + return 0; +} + +static const struct mtd_ooblayout_ops ds35xxgb_ooblayout =3D { + .ecc =3D ds35xxgb_ooblayout_ecc, + .free =3D ds35xxgb_ooblayout_free, +}; + +static int ds35xxgb_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (status & DOSICON_STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + case DOSICON_STATUS_ECC_1TO3_BITFLIPS: + return 3; + + case DOSICON_STATUS_ECC_4TO6_BITFLIPS: + return 6; + + case DOSICON_STATUS_ECC_7TO8_BITFLIPS: + return 8; + + default: + break; + } + + return -EINVAL; +} + static const struct spinand_info dosilicon_spinand_table[] =3D { SPINAND_INFO("DS35Q1GA", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), @@ -67,7 +129,16 @@ static const struct spinand_info dosilicon_spinand_tabl= e[] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&ds35xx_ooblayout, NULL)), + SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)), + SPINAND_INFO("DS35Q2GA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)), SPINAND_INFO("DS35M1GA", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), @@ -76,7 +147,124 @@ static const struct spinand_info dosilicon_spinand_tab= le[] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&ds35xx_ooblayout, NULL)), + SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)), + SPINAND_INFO("DS35M2GA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxga_ooblayout, NULL)), + SPINAND_INFO("DS35Q2GB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35M1GB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q1GB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF1), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q4GM", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF4), + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q12B", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF5), + NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35M12B", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5), + NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q1GD-IB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35M4GB-IB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64), + NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q4GB-IB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB4), + NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q12C-IB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75), + NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35M12C-IB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), + NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q2GBS", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), }; =20 static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = =3D {