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charset="utf-8" The __pdc_enable_intr() function contains a version branch that selects between two distinct enable mechanisms: a bank-based IRQ_ENABLE_BANK register for HW < 3.2, and a per-pin enable bit in IRQ_i_CFG for HW >=3D 3.2. These two paths share no code and serve different hardware. Split them into two focused static functions: pdc_enable_intr_bank() for HW < 3.2 and pdc_enable_intr_cfg() for HW >=3D 3.2. No functional change. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha --- drivers/irqchip/qcom-pdc.c | 42 +++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 32b77fa93f73..a72e32896e64 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -97,28 +97,38 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 enab= le) pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable); } =20 -static void __pdc_enable_intr(int pin_out, bool on) +static void pdc_enable_intr_bank(int pin_out, bool on) { unsigned long enable; + u32 index, mask; =20 - if (pdc_version < PDC_VERSION_3_2) { - u32 index, mask; + index =3D pin_out / 32; + mask =3D pin_out % 32; =20 - index =3D pin_out / 32; - mask =3D pin_out % 32; + enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); + __assign_bit(mask, &enable, on); =20 - enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); - __assign_bit(mask, &enable, on); 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charset="utf-8" The QCOM_PDC_SIZE constant (0x30000) was introduced to work around old sm8150 DTs that described a too-small PDC register region, causing the driver to silently expand the ioremap to cover three DRV regions. Now that the preceding DT fixes have corrected all platforms to describe only the APSS DRV region (0x10000), the oversized clamp is no longer needed. Replace QCOM_PDC_SIZE with PDC_DRV_SIZE (0x10000) in the clamp so the minimum mapped size matches a single DRV region. The clamp and warning are intentionally kept to preserve backward compatibility with any old DTs that may still describe a smaller region. While at it, rename PDC_DRV_OFFSET to PDC_DRV_SIZE since the constant represents the size of a DRV region and is used as both the ioremap minimum size and the offset to the previous DRV region. Reviewed-by: Dmitry Baryshkov Signed-off-by: Mukesh Ojha --- drivers/irqchip/qcom-pdc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index a72e32896e64..21e2b4b884ee 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -21,7 +21,7 @@ #include =20 #define PDC_MAX_GPIO_IRQS 256 -#define PDC_DRV_OFFSET 0x10000 +#define PDC_DRV_SIZE 0x10000 =20 /* Valid only on HW version < 3.2 */ #define IRQ_ENABLE_BANK 0x10 @@ -358,7 +358,6 @@ static int pdc_setup_pin_mapping(struct device_node *np) return 0; } =20 -#define QCOM_PDC_SIZE 0x30000 =20 static int qcom_pdc_probe(struct platform_device *pdev, struct device_node= *parent) { @@ -372,7 +371,7 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare if (of_address_to_resource(node, 0, &res)) return -EINVAL; =20 - res_size =3D max_t(resource_size_t, resource_size(&res), QCOM_PDC_SIZE); + res_size =3D max_t(resource_size_t, resource_size(&res), PDC_DRV_SIZE); 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charset="utf-8" The PDC hardware version register encodes major, minor and step fields in byte-sized fields at bits [23:16], [15:8] and [7:0] respectively. The existing PDC_VERSION_3_2 constant was a bare magic number (0x30200) with no indication of this encoding. Add GENMASK-based field definitions for each sub-field and a PDC_VERSION(maj, min, step) constructor macro using FIELD_PREP, making the encoding self-documenting. Replace the magic constant with PDC_VERSION(3, 2, 0). Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha --- drivers/irqchip/qcom-pdc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 21e2b4b884ee..9ad2c22342e1 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -3,6 +3,7 @@ * Copyright (c) 2017-2019, The Linux Foundation. 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charset="utf-8" The IRQ_ENABLE_BANK register is a bank of 32-bit words where each bit represents one PDC pin. The bank index and bit position within the bank are encoded in the flat pin number as bits [31:5] and [4:0] respectively. Replace the open-coded division and modulo with FIELD_GET() and GENMASK() to make the bit extraction self-documenting and consistent with the FIELD_PREP() style already used in the PDC_VERSION() macro. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha --- drivers/irqchip/qcom-pdc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 9ad2c22342e1..17ca26d66fea 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -27,6 +27,8 @@ /* Valid only on HW version < 3.2 */ #define IRQ_ENABLE_BANK 0x10 #define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_= IRQS)) +#define IRQ_ENABLE_BANK_INDEX_MASK GENMASK(31, 5) +#define IRQ_ENABLE_BANK_BIT_MASK GENMASK(4, 0) #define IRQ_i_CFG 0x110 =20 /* Valid only on HW version >=3D 3.2 */ @@ -110,8 +112,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on) unsigned long enable; u32 index, mask; =20 - index =3D pin_out / 32; - mask =3D pin_out % 32; + index =3D FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out); + mask =3D FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out); =20 enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); __assign_bit(mask, &enable, on); --=20 2.53.0