From nobody Mon Jun 8 18:55:59 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C55F63CD8AA for ; Wed, 27 May 2026 07:53:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779868438; cv=none; b=ho8Db++IT3a1nKMpykrGxH5Yyk7+zWoMf1Z21GxoiSHC7QJ9dEQjzlRt1SJWEVxjZsMInWq0/tODcxxZnJ9zOD8StmXhtuyiTofLRtbZiY/XY3kl1/cAQJrWyutqibn/c4z4Q/R8ep4kL6SaTlTOocNoxZXfSuFA1mz6ESN9+WA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779868438; c=relaxed/simple; bh=vPyICblfgnjXAUpA/kgzPBpRENNQhFjoCMkxnDEMWAk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=D5uUU2N00RiQJMR7Z8l+KOJM2QhhwSh49rKW9z0PbGCINkDz70hAZb711x+HDBIHHRUPAqiKmnSDGnc1/BMxz8Dvr1E/ald7B35B7Ws+bjRemFxJl0KthE7uQmArm7IEExvhMtQaYCcTJMOwD8XBvnFl4+UZg3pQ2cTKq5WXAs4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=oKBzWnJV; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="oKBzWnJV" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-2ba0714574fso61451895ad.2 for ; Wed, 27 May 2026 00:53:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779868436; x=1780473236; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0iW3LrTqWSMLLa9HDk8vrvTznR1WnuzrMZCgjkfBYas=; b=oKBzWnJV4cnY/kSqhuw1JqbTo1YOZDlTsCPs4uLGm9tGM0S6TFwYK1h39KV2ao92Eo rnUfRJFkTueV7TJ4R3+R0jRPj0JsmjmEdWIJ8HciazeXNZ3vJ4gF5QJfFpnqzEUvR9x1 mCIOhQoBJR4+nP1WcMZYKtQD09QNl1dMPzytPHF+lwStP1zw4nskA8xB7Wawn/zJRRNi UiyDfVbCxyvmcPFrsIV58OAYBPGazbpnJ5UECpbcMGjCJslsJ8LSwu2K3hcKehzLSbsD 8XjapIsqUNSV5DNJbXAftkpUWZshwh3lkXO7ZUPF4VGiREEVpkUFjSDV1JdpRyeOq1Aq xB4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779868436; x=1780473236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0iW3LrTqWSMLLa9HDk8vrvTznR1WnuzrMZCgjkfBYas=; b=MkK/KdzsZ/QrjpeygtRUOt7j0gNduv5jhzYG7kB8s9OMXYLI1QDPxwRipTQFtwVcUm aLovw7THXjOaSq3FlkL9RKJnagQKKtiPgxpcgUeaNoxMxmIPcnHh2AB/MAgWzTB6IP1h 1eCjnedYYBSVMJySJT/lGeGHi5Muw031dQZfeG7dO4bCAajW8+DfMBM2oIKzaOxNO2cc uwYs4Fv9dztgROTFktQvDdJXB9I/XUNPUsXsWYwNoDr0DKIMBxH0ESHx75d8bUr2wnw3 WfTStlQWzTVILXTase0DGoUahIbmfAoGgWP1tagED/XQQ+lxYOlU82XkHwpOHodBuJxv i9TQ== X-Forwarded-Encrypted: i=1; AFNElJ//SDLRuVAkEEKPKWFCPJtObZt/N/g2NlguqfePDXhJ0YjlG1deRMAR9anvtDFEwOU0QZx3wcU7nQxv+xU=@vger.kernel.org X-Gm-Message-State: AOJu0YyyumoSd9tAObsWQjNW94MNsVu0/BPO58uTydcVZbg5PTGbemcB uB5jErEECmKKe9QES3Pg/ak3W+IccdOStf9NwTBZblKSQr7BaXgqax5LWqPTmvW10H0= X-Gm-Gg: Acq92OFrFH4zrGkqKsmwDoxYifa4E8LyE2C75n8o9dRZbNhR+hYPxzV/U+3DLd7VDRK 5c0M8sNoMNa6CM3yr47hSv6NsqYprowkJeqa1WODd5G51ueUomlmIwV3PjtRnyDo+WKQ4zQY9/S 5mTfLgD7A4n1gYLYR47QntYfI8YRP//WojiQeaE5NZqXD2OkFiXRsZvP2yRKCNC/jHMinfcm7cv lpBglGsxPjDWs1kvufan3J6kX7q8C33UItguI+5dk2joTJmBajxdL9pL75Dz57LeJq8ZJU521ka 3oIDnqSXPjpnTNonaflOjT1k8g0WCWzgbo6Q4Wum7cghOyaIazEaDPMia0FUrc86fp935PMml7A kQnAV/dykfztCDYEfUCnItOwN/yL/3xttFAVVjJzLoQ7ezyvy7zgorjXLz0bVGT1ew4MediPS4A F6mmy4PNDyedo86VfziQ== X-Received: by 2002:a17:902:cf0b:b0:2bd:93b0:2c18 with SMTP id d9443c01a7336-2beb0385282mr248861285ad.9.1779868435997; Wed, 27 May 2026 00:53:55 -0700 (PDT) Received: from n151-105-216.byted.org ([240e:b1:e401:3::a4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb56bc151sm147558455ad.24.2026.05.27.00.53.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 00:53:55 -0700 (PDT) From: guzebing To: kbusch@kernel.org, axboe@kernel.dk, hch@lst.de, sagi@grimberg.me Cc: linux-nvme@lists.infradead.org, linux-kernel@vger.kernel.org, Guzebing Subject: [RFC PATCH 1/1] nvme-pci: detect I/O queue depth changes after reset Date: Wed, 27 May 2026 15:53:20 +0800 Message-Id: <20260527075320.3178600-2-guzebing1612@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20260527075320.3178600-1-guzebing1612@gmail.com> References: <20260527075320.3178600-1-guzebing1612@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guzebing Firmware activation may change the controller queue depth reported through CAP.MQES. In the nvme-pci reset path, nvme_pci_enable() rereads CAP and updates dev->q_depth, while existing struct nvme_queue entries keep the old q_depth and SQ/CQ DMA addresses. If the new depth is smaller than the existing nvmeq depth, reset recovery would try to create I/O queues with a depth the controller no longer accepts. Detect this before recreating I/O queues and fail the reset with an explicit error; without this, the failure shows up later as lost I/O queues and namespace removal. If the new depth is larger, warn and continue with the existing queue resources. The larger depth will not be used until the controller is removed and probed again. Signed-off-by: Guzebing --- drivers/nvme/host/pci.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index db5fc9bf66272..4bc112f8a096e 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -3155,6 +3155,33 @@ static bool nvme_pci_update_nr_queues(struct nvme_de= v *dev) return true; } =20 +static int nvme_pci_check_reset_queue_depth(struct nvme_dev *dev) +{ + u32 nvmeq_q_depth; + u32 dev_q_depth =3D dev->q_depth; + + if (dev->ctrl.queue_count <=3D 1) + return 0; + + nvmeq_q_depth =3D dev->queues[1].q_depth; + if (nvmeq_q_depth =3D=3D dev_q_depth) + return 0; + + if (nvmeq_q_depth > dev_q_depth) { + dev_err(dev->ctrl.device, + "IO queue depth decreased after reset (%u -> %u); " + "live reset recovery is unsupported\n", + nvmeq_q_depth, dev_q_depth); + return -EIO; + } + + dev_warn(dev->ctrl.device, + "IO queue depth increased after reset (%u -> %u); " + "remove and probe the controller again to use the new depth\n", + nvmeq_q_depth, dev_q_depth); + return 0; +} + static int nvme_pci_enable(struct nvme_dev *dev) { int result =3D -ENOMEM; @@ -3371,6 +3398,9 @@ static void nvme_reset_work(struct work_struct *work) =20 mutex_lock(&dev->shutdown_lock); result =3D nvme_pci_enable(dev); + if (result) + goto out_unlock; + result =3D nvme_pci_check_reset_queue_depth(dev); if (result) goto out_unlock; nvme_unquiesce_admin_queue(&dev->ctrl); --=20 2.20.1