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Tue, 26 May 2026 22:37:19 -0700 (PDT) Received: from [169.254.0.3] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb569592dsm136338585ad.16.2026.05.26.22.37.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2026 22:37:18 -0700 (PDT) From: Raviteja Laggyshetty Date: Wed, 27 May 2026 05:37:09 +0000 Subject: [PATCH v2 1/3] dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260527-x1e80100_qos-v2-1-305c6539e6d2@oss.qualcomm.com> References: <20260527-x1e80100_qos-v2-0-305c6539e6d2@oss.qualcomm.com> In-Reply-To: <20260527-x1e80100_qos-v2-0-305c6539e6d2@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Abel Vesa , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Raviteja Laggyshetty X-Mailer: b4 0.15.0 X-Authority-Analysis: v=2.4 cv=Ja+Ma0KV c=1 sm=1 tr=0 ts=6a168311 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=NnUtUk1SRsyLyR8-XE8A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: bedoUDuvuWnZJSdFXLXPln0EKrtzYtE1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI3MDA1MiBTYWx0ZWRfX1HmQhaFwS+Rk 25SiNgDOtozEPlzrGYKtLlQT1OQ4+nJXN4rSXWgADvJItW35YMdX9xImG0H5YKEd3iIbJpp65MB JKSN75Am2NueSUtrhfeFSsfT3tDOmfIVn0E7Qde1tnzxyKA0d0AnyQ5tczLwpgONHavRNiTH489 jNv4+D5dMGmrsiTCvQMj90Drx6epPsXL7dDow4neP2ph8+dCPPMsYl7Mq+5+3OSFG2gCb9BNUva BHKZocYOyLYUzFDS5Nud+xO7wqZ+jWZylaWBN8xiBKFliJyhxhtLQ/KxzSi8WkB0hmmQZ4V7cjT wv/7lA+89hglgmY+O78uRLBBWzEWg7tvPhTOrkk8w3q40ECSXQNvxEbL1qJtmTmiDx9DwPbt9Ek xIBU3mhRFMfH+9N4Axv4q1gmCw1Av29P0sEBFrubOMRfQkFf0U8as4a9fsNMW8AId9WXJBHXZvi VPJcnuu/f5mNvB6UsSw== X-Proofpoint-GUID: bedoUDuvuWnZJSdFXLXPln0EKrtzYtE1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-26_05,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605270052 Some interconnect nodes on X1E80100 have QoS registers located inside a block whose interface is clock-gated. For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock-gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski --- .../bindings/interconnect/qcom,x1e80100-rpmh.yaml | 72 ++++++++++++++++++= ++++ 1 file changed, 72 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-r= pmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpm= h.yaml index 0840b0ec6e27..d863cddb21ac 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml @@ -46,6 +46,10 @@ properties: reg: maxItems: 1 =20 + clocks: + minItems: 1 + maxItems: 6 + required: - compatible =20 @@ -65,6 +69,73 @@ allOf: required: - reg =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-usb-north-anoc + then: + properties: + clocks: + items: + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 MP AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-usb-south-anoc + then: + properties: + clocks: + items: + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + - description: aggre USB3 TERT AXI clock + - description: aggre USB4_0 AXI clock + - description: aggre USB4_1 AXI clock + - description: aggre USB4_2 AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-aggre2-noc + - qcom,x1e80100-clk-virt + - qcom,x1e80100-cnoc-cfg + - qcom,x1e80100-cnoc-main + - qcom,x1e80100-gem-noc + - qcom,x1e80100-lpass-ag-noc + - qcom,x1e80100-lpass-lpiaon-noc + - qcom,x1e80100-lpass-lpicx-noc + - qcom,x1e80100-mc-virt + - qcom,x1e80100-mmss-noc + - qcom,x1e80100-nsp-noc + - qcom,x1e80100-pcie-center-anoc + - qcom,x1e80100-pcie-north-anoc + - qcom,x1e80100-pcie-south-anoc + - qcom,x1e80100-system-noc + - qcom,x1e80100-usb-center-anoc + then: + properties: + clocks: false + unevaluatedProperties: false =20 examples: @@ -80,4 +151,5 @@ examples: reg =3D <0x016e0000 0x14400>; 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Tue, 26 May 2026 22:37:24 -0700 (PDT) Received: from [169.254.0.3] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb569592dsm136338585ad.16.2026.05.26.22.37.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2026 22:37:23 -0700 (PDT) From: Raviteja Laggyshetty Date: Wed, 27 May 2026 05:37:10 +0000 Subject: [PATCH v2 2/3] interconnect: qcom: x1e80100: enable QoS configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260527-x1e80100_qos-v2-2-305c6539e6d2@oss.qualcomm.com> References: <20260527-x1e80100_qos-v2-0-305c6539e6d2@oss.qualcomm.com> In-Reply-To: <20260527-x1e80100_qos-v2-0-305c6539e6d2@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Abel Vesa , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Raviteja Laggyshetty , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.15.0 X-Authority-Analysis: v=2.4 cv=Zubd7d7G c=1 sm=1 tr=0 ts=6a168316 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=yo5WBCStKggJxw3bOVAA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI3MDA1MSBTYWx0ZWRfX5s4BEHCaAStx KmsmyCOr15GBDMQzzQqc2taLNKyJBm0fZxxgymD8+BJxpBFeJfxAMT9exWC5I9iMegeQ1J9hiMu UaM3JFKAhumUOblsG0IZtosMnkVClUITMqF/Sw7nGE6wGfN4MIvwJKehiBx8Z6RXm02mzvSvU2v wUia/dsuKMFHVYDO/ofk1UJv1mbZjBS1fQo9i3rBsqWoqF5O+lo5/VIwr7nz+cQ0D2Y3gWQGGKZ U4xagII7HlidX/6NpC+LG2DWWWucOSlz7EBIctGGUx02okn3k6qXk7URiCn61rqn3MZm/4jg9MF vFb/31t8Y1oNDsszlDJj2lb92CMyjQE8kcpgyBtjcn9Ncee/qH9k06ewcyoDn7FqJd1TRWzg7Tn CibMAM6pV0Ipsk6gxd229TcmiFSpTuX5zQOnaa775hBPsUXFfcHMSUAyXmg+MfTfHq3CHjgA2+D 3XkLogBANicGMaBwrXg== X-Proofpoint-ORIG-GUID: aYQTKodLWmFWeWUj42gFG0if8yywe7tG X-Proofpoint-GUID: aYQTKodLWmFWeWUj42gFG0if8yywe7tG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-26_05,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 suspectscore=0 malwarescore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605270051 Enable QoS configuration for master ports with predefined priority and urgency forwarding. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/x1e80100.c | 485 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 485 insertions(+) diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qc= om/x1e80100.c index 2ba2823c7860..8075e0ff2059 100644 --- a/drivers/interconnect/qcom/x1e80100.c +++ b/drivers/interconnect/qcom/x1e80100.c @@ -173,6 +173,13 @@ static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -181,6 +188,13 @@ static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -189,6 +203,13 @@ static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -197,6 +218,13 @@ static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -205,6 +233,13 @@ static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -213,6 +248,13 @@ static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -221,6 +263,13 @@ static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -237,6 +286,13 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -245,6 +301,13 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -253,6 +316,13 @@ static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a2noc_snoc }, }; @@ -337,6 +407,13 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x271000 }, + .prio =3D 1, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -345,6 +422,13 @@ static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x27d000 }, + .prio =3D 3, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -353,6 +437,13 @@ static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x273000 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -370,6 +461,13 @@ static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 4, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 4, + .port_offsets =3D { 0x51000, 0x58000, 0xd1000, 0xd8000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -378,6 +476,13 @@ static struct qcom_icc_node qnm_lpass =3D { .name =3D "qnm_lpass", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x275000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -387,6 +492,13 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x53000, 0xd3000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -395,6 +507,13 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x55000, 0xd5000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -403,6 +522,13 @@ static struct qcom_icc_node qnm_nsp_noc =3D { .name =3D "qnm_nsp_noc", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x57000, 0xd7000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -412,6 +538,13 @@ static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .channels =3D 1, .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x277000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; @@ -420,6 +553,13 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x27b000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -429,6 +569,13 @@ static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x27f000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; @@ -469,6 +616,13 @@ static struct qcom_icc_node qnm_av1_enc =3D { .name =3D "qnm_av1_enc", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2f000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -477,6 +631,13 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x28000, 0x29000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -485,6 +646,13 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -493,6 +661,13 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x2b000, 0x2c000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -501,6 +676,13 @@ static struct qcom_icc_node qnm_eva =3D { .name =3D "qnm_eva", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x33000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -509,6 +691,13 @@ static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x2d000, 0x2e000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -517,6 +706,13 @@ static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x30000, 0x31000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -525,6 +721,13 @@ static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x32000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -533,6 +736,13 @@ static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x34000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_sf }, }; @@ -573,6 +783,13 @@ static struct qcom_icc_node xm_pcie_3 =3D { .name =3D "xm_pcie_3", .channels =3D 1, .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x7000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_north_gem_noc }, }; @@ -581,6 +798,13 @@ static struct qcom_icc_node xm_pcie_4 =3D { .name =3D "xm_pcie_4", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x8000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_north_gem_noc }, }; @@ -589,6 +813,13 @@ static struct qcom_icc_node xm_pcie_5 =3D { .name =3D "xm_pcie_5", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 3, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_north_gem_noc }, }; @@ -597,6 +828,13 @@ static struct qcom_icc_node xm_pcie_0 =3D { .name =3D "xm_pcie_0", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -605,6 +843,13 @@ static struct qcom_icc_node xm_pcie_1 =3D { .name =3D "xm_pcie_1", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -613,6 +858,13 @@ static struct qcom_icc_node xm_pcie_2 =3D { .name =3D "xm_pcie_2", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -621,6 +873,13 @@ static struct qcom_icc_node xm_pcie_6a =3D { .name =3D "xm_pcie_6a", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -629,6 +888,13 @@ static struct qcom_icc_node xm_pcie_6b =3D { .name =3D "xm_pcie_6b", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_south_gem_noc }, }; @@ -653,6 +919,13 @@ static struct qcom_icc_node qnm_gic =3D { .name =3D "qnm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1c000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_gemnoc_sf }, }; @@ -685,6 +958,13 @@ static struct qcom_icc_node xm_usb2_0 =3D { .name =3D "xm_usb2_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x6000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_north_snoc }, }; @@ -693,6 +973,13 @@ static struct qcom_icc_node xm_usb3_mp =3D { .name =3D "xm_usb3_mp", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x7000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_north_snoc }, }; @@ -701,6 +988,13 @@ static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -709,6 +1003,13 @@ static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -717,6 +1018,13 @@ static struct qcom_icc_node xm_usb3_2 =3D { .name =3D "xm_usb3_2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -725,6 +1033,13 @@ static struct qcom_icc_node xm_usb4_0 =3D { .name =3D "xm_usb4_0", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -733,6 +1048,13 @@ static struct qcom_icc_node xm_usb4_1 =3D { .name =3D "xm_usb4_1", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -741,6 +1063,13 @@ static struct qcom_icc_node xm_usb4_2 =3D { .name =3D "xm_usb4_2", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; @@ -1466,11 +1795,21 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, }; =20 +static const struct regmap_config x1e80100_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14400, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_aggre1_noc =3D { + .config =3D &x1e80100_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1488,7 +1827,16 @@ static struct qcom_icc_node * const aggre2_noc_nodes= [] =3D { [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, }; =20 +static const struct regmap_config x1e80100_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c400, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_aggre2_noc =3D { + .config =3D &x1e80100_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1573,7 +1921,16 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[]= =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 +static const struct regmap_config x1e80100_cnoc_cfg_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x6600, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_cnoc_cfg =3D { + .config =3D &x1e80100_cnoc_cfg_regmap_config, .nodes =3D cnoc_cfg_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), .bcms =3D cnoc_cfg_bcms, @@ -1603,7 +1960,16 @@ static struct qcom_icc_node * const cnoc_main_nodes[= ] =3D { [SLAVE_PCIE_6B] =3D &xs_pcie_6b, }; =20 +static const struct regmap_config x1e80100_cnoc_main_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14400, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_cnoc_main =3D { + .config =3D &x1e80100_cnoc_main_regmap_config, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1633,7 +1999,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, }; =20 +static const struct regmap_config x1e80100_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x311200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_gem_noc =3D { + .config =3D &x1e80100_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1648,7 +2023,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nod= es[] =3D { [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, }; =20 +static const struct regmap_config x1e80100_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xe080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_lpass_ag_noc =3D { + .config =3D &x1e80100_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1664,7 +2048,16 @@ static struct qcom_icc_node * const lpass_lpiaon_noc= _nodes[] =3D { [SLAVE_LPIAON_NOC_LPASS_AG_NOC] =3D &qns_lpass_aggnoc, }; =20 +static const struct regmap_config x1e80100_lpass_lpiaon_noc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x19080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc =3D { + .config =3D &x1e80100_lpass_lpiaon_noc_regmap_config, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1679,7 +2072,16 @@ static struct qcom_icc_node * const lpass_lpicx_noc_= nodes[] =3D { [SLAVE_LPICX_NOC_LPIAON_NOC] =3D &qns_lpi_aon_noc, }; =20 +static const struct regmap_config x1e80100_lpass_lpicx_noc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3a200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc =3D { + .config =3D &x1e80100_lpass_lpicx_noc_regmap_config, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms =3D lpass_lpicx_noc_bcms, @@ -1724,7 +2126,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC] =3D &srvc_mnoc, }; =20 +static const struct regmap_config x1e80100_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5b800, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_mmss_noc =3D { + .config =3D &x1e80100_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1740,7 +2151,16 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { [SLAVE_CDSP_MEM_NOC] =3D &qns_nsp_gemnoc, }; =20 +static const struct regmap_config x1e80100_nsp_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xe080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_nsp_noc =3D { + .config =3D &x1e80100_nsp_noc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1757,7 +2177,16 @@ static struct qcom_icc_node * const pcie_center_anoc= _nodes[] =3D { [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, }; =20 +static const struct regmap_config x1e80100_pcie_center_anoc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x7000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_pcie_center_anoc =3D { + .config =3D &x1e80100_pcie_center_anoc_regmap_config, .nodes =3D pcie_center_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_center_anoc_nodes), .bcms =3D pcie_center_anoc_bcms, @@ -1774,7 +2203,16 @@ static struct qcom_icc_node * const pcie_north_anoc_= nodes[] =3D { [SLAVE_PCIE_NORTH] =3D &qns_pcie_north_gem_noc, }; =20 +static const struct regmap_config x1e80100_pcie_north_anoc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_pcie_north_anoc =3D { + .config =3D &x1e80100_pcie_north_anoc_regmap_config, .nodes =3D pcie_north_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_north_anoc_nodes), .bcms =3D pcie_north_anoc_bcms, @@ -1793,7 +2231,16 @@ static struct qcom_icc_node * const pcie_south_anoc_= nodes[] =3D { [SLAVE_PCIE_SOUTH] =3D &qns_pcie_south_gem_noc, }; =20 +static const struct regmap_config x1e80100_pcie_south_anoc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xd080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_pcie_south_anoc =3D { + .config =3D &x1e80100_pcie_south_anoc_regmap_config, .nodes =3D pcie_south_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_south_anoc_nodes), .bcms =3D pcie_south_anoc_bcms, @@ -1815,7 +2262,16 @@ static struct qcom_icc_node * const system_noc_nodes= [] =3D { [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, }; =20 +static const struct regmap_config x1e80100_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_system_noc =3D { + .config =3D &x1e80100_system_noc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, @@ -1831,7 +2287,16 @@ static struct qcom_icc_node * const usb_center_anoc_= nodes[] =3D { [SLAVE_USB_NOC_SNOC] =3D &qns_aggre_usb_snoc, }; =20 +static const struct regmap_config x1e80100_usb_center_anoc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8800, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_usb_center_anoc =3D { + .config =3D &x1e80100_usb_center_anoc_regmap_config, .nodes =3D usb_center_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_center_anoc_nodes), .bcms =3D usb_center_anoc_bcms, @@ -1847,11 +2312,21 @@ static struct qcom_icc_node * const usb_north_anoc_= nodes[] =3D { [SLAVE_AGGRE_USB_NORTH] =3D &qns_aggre_usb_north_snoc, }; =20 +static const struct regmap_config x1e80100_usb_north_anoc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x7080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc x1e80100_usb_north_anoc =3D { + .config =3D &x1e80100_usb_north_anoc_regmap_config, .nodes =3D usb_north_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_north_anoc_nodes), .bcms =3D usb_north_anoc_bcms, .num_bcms =3D ARRAY_SIZE(usb_north_anoc_bcms), + .qos_requires_clocks =3D true, }; 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Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Raviteja Laggyshetty --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index 4ba751a65142..1a2d9b3f7a70 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3132,6 +3132,7 @@ aggre1_noc: interconnect@16e0000 { qcom,bcm-voters =3D <&apps_bcm_voter>; =20 #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; }; =20 aggre2_noc: interconnect@1700000 { @@ -3168,6 +3169,8 @@ usb_north_anoc: interconnect@1760000 { qcom,bcm-voters =3D <&apps_bcm_voter>; =20 #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>; }; =20 usb_south_anoc: interconnect@1770000 { @@ -3177,6 +3180,12 @@ usb_south_anoc: interconnect@1770000 { qcom,bcm-voters =3D <&apps_bcm_voter>; =20 #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_2_AXI_CLK>; }; =20 mmss_noc: interconnect@1780000 { --=20 2.43.0