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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304d4222060sm691653eec.29.2026.05.27.19.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 19:29:23 -0700 (PDT) From: Qiang Yu Date: Wed, 27 May 2026 19:29:12 -0700 Subject: [PATCH v4 1/7] dt-bindings: clock: qcom,sm8550-tcsr: Add QREF/REFGEN supply properties for glymur and mahua Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260527-tcsr_qref_0527-v4-1-ded83866c9d9@oss.qualcomm.com> References: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> In-Reply-To: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu , krishna.chundru@oss.qualcomm.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779935361; l=3605; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=WtpPDP907J8Nn9pP4O+K4wkFHYLpz21QFKFWYhc+jsc=; b=XhrGeWmgpKIsHUWiq4AppbACbHOcVj6K6rxQn7Yws8I79Z7jXYASbFMT0wJ1M8kTF4QI1BKnH g1s1Jktz06JAfPT5/MThSpK7nKf5WI4cypHghocHKhSyDi+jvhLq4/w X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-ORIG-GUID: Q-UhhcBAgBvSe1VwhAbo8yYKMQFDse7E X-Proofpoint-GUID: Q-UhhcBAgBvSe1VwhAbo8yYKMQFDse7E X-Authority-Analysis: v=2.4 cv=E/r9Y6dl c=1 sm=1 tr=0 ts=6a17a885 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=ED1JfwARjmvM9eENDMIA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDAyMSBTYWx0ZWRfXyysA731TfEI1 2s3F63jT/I6agj2sIqk/+PHnO7Ur2zUTx3yXUylj9ku5dIs8OPTPO1t17esU/Yzg9wPNxGXkWj8 HYizvLUcKXBdlLJVe9ah2OYwvoR8K510M7ajIGifz/X5JsKLgSaEagQ7tmrRwcqxo/l6j4T0U3O DJ3Zggz4N6943vwYJDV5gyU1XySIg1/8P3GHAYeARjkl6pXEqAqfSIoasYJuV5nzyz/ntZoya4B h37ei+dj/PdeJWpFX6aL8sUrAihfEEmYX5f+h4s6ciUJy4bzkLIgJSyt8H2Us4areqgB+slrrVf obyLZRqIYPx68QXJYPNzmQH6KHmM2+3vME0hmawTAyRMFUxBSFOJNdN2Ku/06dZ4uuFZ9SDej+N X7QWQNSzKw0tfjcwbwbvWItEjyr6D1OQZvoREy8IhaG7vIXpY2e8TwFPKo/szZGD8zCMECZo7m3 qFMS70if6IwGubWOp/g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-27_05,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280021 The QREF block supplies reference clocks to PCIe PHYs and requires dedicated LDO supplies to operate. The digital control interface for QREF (clkref_en registers) resides in TCSR on glymur and mahua. Since QREF has no dedicated DT node of its own, these supply properties are placed in the TCSR node which acts as the control interface for QREF. Document the supply properties for qcom,glymur-tcsr and qcom,mahua-tcsr. Both SoCs share the same QREF TX/RPT/RX component naming, but differ in topology: Glymur has two independent QREF blocks fed by REFGEN3 and REFGEN4. Mahua has a single QREF block fed by REFGEN3 only. Mark the relevant supplies as required per compatible using allOf/if/then conditionals. Signed-off-by: Qiang Yu --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 66 ++++++++++++++++++= ++++ 1 file changed, 66 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 08824f848973..fd3736ad8c8f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -31,6 +31,7 @@ properties: - qcom,glymur-tcsr - qcom,hawi-tcsrcc - qcom,kaanapali-tcsr + - qcom,mahua-tcsr - qcom,milos-tcsr - qcom,nord-tcsrcc - qcom,sar2130p-tcsr @@ -53,6 +54,71 @@ properties: '#reset-cells': const: 1 =20 + vdda-qrefrpt0-0p9-supply: true + vdda-qrefrpt1-0p9-supply: true + vdda-qrefrpt2-0p9-supply: true + vdda-qrefrpt3-0p9-supply: true + vdda-qrefrpt4-0p9-supply: true + vdda-qrefrpt5-0p9-supply: true + vdda-qrefrx0-0p9-supply: true + vdda-qrefrx1-0p9-supply: true + vdda-qrefrx2-0p9-supply: true + vdda-qrefrx3-0p9-supply: true + vdda-qrefrx4-0p9-supply: true + vdda-qrefrx5-0p9-supply: true + vdda-qreftx0-0p9-supply: true + vdda-qreftx0-1p2-supply: true + vdda-qreftx1-0p9-supply: true + vdda-refgen3-0p9-supply: true + vdda-refgen3-1p2-supply: true + vdda-refgen4-0p9-supply: true + vdda-refgen4-1p2-supply: true + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,glymur-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrx0-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx4-0p9-supply + - vdda-qrefrx5-0p9-supply + - vdda-qreftx0-0p9-supply + - vdda-qreftx0-1p2-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply + - vdda-refgen4-0p9-supply + - vdda-refgen4-1p2-supply + - if: + properties: + compatible: + contains: + const: qcom,mahua-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrpt5-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx3-0p9-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply + required: - compatible - clocks --=20 2.34.1 From nobody Mon Jun 8 16:32:50 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A41972F8E83 for ; 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QREF is powered by dedicated LDO rails, and the clkref_en register controls whether refclk is gated through to the PHY side. These clkref controls are different from typical GCC branch clocks: - only a single enable bit is present, without branch-style config bits - regulators must be voted before enable and unvoted after disable Model this as a dedicated clk_ref clock type with custom clk_ops instead of reusing struct clk_branch semantics. Also provide a common registration/probe API so the same clkref model can be reused regardless of where clkref_en registers are placed, e.g. TCSR on glymur and TLMM on SM8750. Signed-off-by: Qiang Yu --- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ref.c | 205 +++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/clk/qcom.h | 69 +++++++++++++++ 3 files changed, 275 insertions(+) diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e100cfd6a52d..c5b02360861d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -8,6 +8,7 @@ clk-qcom-y +=3D clk-pll.o clk-qcom-y +=3D clk-rcg.o clk-qcom-y +=3D clk-rcg2.o clk-qcom-y +=3D clk-branch.o +clk-qcom-y +=3D clk-ref.o clk-qcom-y +=3D clk-regmap-divider.o clk-qcom-y +=3D clk-regmap-mux.o clk-qcom-y +=3D clk-regmap-mux-div.o diff --git a/drivers/clk/qcom/clk-ref.c b/drivers/clk/qcom/clk-ref.c new file mode 100644 index 000000000000..213c0f58bb36 --- /dev/null +++ b/drivers/clk/qcom/clk-ref.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define QCOM_CLK_REF_EN_MASK BIT(0) + +struct qcom_clk_ref_provider { + struct qcom_clk_ref *refs; + size_t num_refs; +}; + +static inline struct qcom_clk_ref *to_qcom_clk_ref(struct clk_hw *hw) +{ + return container_of(hw, struct qcom_clk_ref, hw); +} + +static const struct clk_parent_data qcom_clk_ref_parent_data =3D { + .index =3D 0, +}; + +static int qcom_clk_ref_prepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + int ret; + + if (!rclk->desc.num_regulators) + return 0; + + ret =3D regulator_bulk_enable(rclk->desc.num_regulators, rclk->regulators= ); + if (ret) + pr_err("Failed to enable regulators for %s: %d\n", + clk_hw_get_name(hw), ret); + + return ret; +} + +static void qcom_clk_ref_unprepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + + if (rclk->desc.num_regulators) + regulator_bulk_disable(rclk->desc.num_regulators, rclk->regulators); +} + +static int qcom_clk_ref_enable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + int ret; + + ret =3D regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_= EN_MASK, + QCOM_CLK_REF_EN_MASK); + if (ret) + return ret; + + udelay(10); + + return 0; +} + +static void qcom_clk_ref_disable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + + regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK,= 0); + udelay(10); +} + +static int qcom_clk_ref_is_enabled(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + u32 val; + int ret; + + ret =3D regmap_read(rclk->regmap, rclk->desc.offset, &val); + if (ret) + return ret; + + return !!(val & QCOM_CLK_REF_EN_MASK); +} + +static const struct clk_ops qcom_clk_ref_ops =3D { + .prepare =3D qcom_clk_ref_prepare, + .unprepare =3D qcom_clk_ref_unprepare, + .enable =3D qcom_clk_ref_enable, + .disable =3D qcom_clk_ref_disable, + .is_enabled =3D qcom_clk_ref_is_enabled, +}; + +static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap, + struct qcom_clk_ref *clk_refs, + const struct qcom_clk_ref_desc *descs, + size_t num_clk_refs) +{ + const struct qcom_clk_ref_desc *desc; + struct qcom_clk_ref *clk_ref; + size_t clk_idx; + unsigned int i; + int ret; + + for (clk_idx =3D 0; clk_idx < num_clk_refs; clk_idx++) { + clk_ref =3D &clk_refs[clk_idx]; + desc =3D &descs[clk_idx]; + + if (!desc->name) + continue; + + clk_ref->regmap =3D regmap; + clk_ref->desc =3D *desc; + + if (clk_ref->desc.num_regulators) { + clk_ref->regulators =3D devm_kcalloc(dev, clk_ref->desc.num_regulators, + sizeof(*clk_ref->regulators), + GFP_KERNEL); + if (!clk_ref->regulators) + return -ENOMEM; + + for (i =3D 0; i < clk_ref->desc.num_regulators; i++) + clk_ref->regulators[i].supply =3D + clk_ref->desc.regulator_names[i]; + + ret =3D devm_regulator_bulk_get(dev, clk_ref->desc.num_regulators, + clk_ref->regulators); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get regulators for %s\n", + clk_ref->desc.name); + } + + clk_ref->init_data.name =3D clk_ref->desc.name; + clk_ref->init_data.parent_data =3D &qcom_clk_ref_parent_data; + clk_ref->init_data.num_parents =3D 1; + clk_ref->init_data.ops =3D &qcom_clk_ref_ops; + clk_ref->hw.init =3D &clk_ref->init_data; + + ret =3D devm_clk_hw_register(dev, &clk_ref->hw); + if (ret) + return ret; + } + + return 0; +} + +static struct clk_hw *qcom_clk_ref_provider_get(struct of_phandle_args *cl= kspec, void *data) +{ + struct qcom_clk_ref_provider *provider =3D data; + unsigned int idx =3D clkspec->args[0]; + + if (idx >=3D provider->num_refs) + return ERR_PTR(-EINVAL); + + if (!provider->refs[idx].regmap) + return ERR_PTR(-ENOENT); + + return &provider->refs[idx].hw; +} + +int qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc *descs, + size_t num_clk_refs) +{ + struct qcom_clk_ref_provider *provider; + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + provider =3D devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + + provider->refs =3D devm_kcalloc(dev, num_clk_refs, sizeof(*provider->refs= ), + GFP_KERNEL); + if (!provider->refs) + return -ENOMEM; + + provider->num_refs =3D num_clk_refs; + + ret =3D qcom_clk_ref_register(dev, regmap, provider->refs, descs, + provider->num_refs); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, qcom_clk_ref_provider_get, provid= er); +} +EXPORT_SYMBOL_GPL(qcom_clk_ref_probe); diff --git a/include/linux/clk/qcom.h b/include/linux/clk/qcom.h new file mode 100644 index 000000000000..09e2e3178cfb --- /dev/null +++ b/include/linux/clk/qcom.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __LINUX_CLK_QCOM_H +#define __LINUX_CLK_QCOM_H + +#include +#include +#include +#include +#include + +struct device; +struct platform_device; +struct regulator_bulk_data; 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This keeps the glymur driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Signed-off-by: Qiang Yu --- drivers/clk/qcom/tcsrcc-glymur.c | 330 ++++++++++-------------------------= ---- 1 file changed, 83 insertions(+), 247 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index 9c0edebcdbb1..e317003398d1 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -4,277 +4,111 @@ */ =20 #include +#include #include #include +#include #include #include =20 #include =20 -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_BI_TCXO_PAD, +static const char * const glymur_tcsr_tx0_rx5_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qrefrx5-0p9", + "vdda-qreftx0-0p9", + "vdda-qreftx0-1p2", }; =20 -static struct clk_branch tcsr_edp_clkref_en =3D { - .halt_reg =3D 0x60, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x60, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_edp_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt01_rx1_regulators[] =3D { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", }; =20 -static struct clk_branch tcsr_pcie_1_clkref_en =3D { - .halt_reg =3D 0x48, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x48, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt012_rx2_regulators[] =3D { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", }; =20 -static struct clk_branch tcsr_pcie_2_clkref_en =3D { - .halt_reg =3D 0x4c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x4c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x94, + .fast_io =3D true, }; =20 -static struct clk_branch tcsr_pcie_3_clkref_en =3D { - .halt_reg =3D 0x54, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x54, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, +static const struct qcom_clk_ref_desc tcsr_cc_glymur_clk_descs[] =3D { + [TCSR_EDP_CLKREF_EN] =3D { + .name =3D "tcsr_edp_clkref_en", + .offset =3D 0x60, }, -}; - -static struct clk_branch tcsr_pcie_4_clkref_en =3D { - .halt_reg =3D 0x58, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x58, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_1_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_1_clkref_en", + .offset =3D 0x48, + .regulator_names =3D glymur_tcsr_tx0_rx5_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators), }, -}; - -static struct clk_branch tcsr_usb2_1_clkref_en =3D { - .halt_reg =3D 0x6c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x6c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_2_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_2_clkref_en", + .offset =3D 0x4c, + .regulator_names =3D glymur_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb2_2_clkref_en =3D { - .halt_reg =3D 0x70, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x70, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_3_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_3_clkref_en", + .offset =3D 0x54, + .regulator_names =3D glymur_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), }, -}; - -static struct clk_branch tcsr_usb2_3_clkref_en =3D { - .halt_reg =3D 0x74, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x74, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_4_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_4_clkref_en", + .offset =3D 0x58, + .regulator_names =3D glymur_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb2_4_clkref_en =3D { - .halt_reg =3D 0x88, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x88, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_1_clkref_en", + .offset =3D 0x6c, }, -}; - -static struct clk_branch tcsr_usb3_0_clkref_en =3D { - .halt_reg =3D 0x64, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x64, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_0_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_2_clkref_en", + .offset =3D 0x70, }, -}; - -static struct clk_branch tcsr_usb3_1_clkref_en =3D { - .halt_reg =3D 0x68, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x68, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_3_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_3_clkref_en", + .offset =3D 0x74, }, -}; - -static struct clk_branch tcsr_usb4_1_clkref_en =3D { - .halt_reg =3D 0x44, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x44, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_4_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_4_clkref_en", + .offset =3D 0x88, }, -}; - -static struct clk_branch tcsr_usb4_2_clkref_en =3D { - .halt_reg =3D 0x5c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x5c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB3_0_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_0_clkref_en", + .offset =3D 0x64, + }, + [TCSR_USB3_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_1_clkref_en", + .offset =3D 0x68, + }, + [TCSR_USB4_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_1_clkref_en", + .offset =3D 0x44, + }, + [TCSR_USB4_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_2_clkref_en", + .offset =3D 0x5c, }, -}; - -static struct clk_regmap *tcsr_cc_glymur_clocks[] =3D { - [TCSR_EDP_CLKREF_EN] =3D &tcsr_edp_clkref_en.clkr, - [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, - [TCSR_PCIE_2_CLKREF_EN] =3D &tcsr_pcie_2_clkref_en.clkr, - [TCSR_PCIE_3_CLKREF_EN] =3D &tcsr_pcie_3_clkref_en.clkr, - [TCSR_PCIE_4_CLKREF_EN] =3D &tcsr_pcie_4_clkref_en.clkr, - [TCSR_USB2_1_CLKREF_EN] =3D &tcsr_usb2_1_clkref_en.clkr, - [TCSR_USB2_2_CLKREF_EN] =3D &tcsr_usb2_2_clkref_en.clkr, - [TCSR_USB2_3_CLKREF_EN] =3D &tcsr_usb2_3_clkref_en.clkr, - [TCSR_USB2_4_CLKREF_EN] =3D &tcsr_usb2_4_clkref_en.clkr, - [TCSR_USB3_0_CLKREF_EN] =3D &tcsr_usb3_0_clkref_en.clkr, - [TCSR_USB3_1_CLKREF_EN] =3D &tcsr_usb3_1_clkref_en.clkr, - [TCSR_USB4_1_CLKREF_EN] =3D &tcsr_usb4_1_clkref_en.clkr, - [TCSR_USB4_2_CLKREF_EN] =3D &tcsr_usb4_2_clkref_en.clkr, -}; - -static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x94, - .fast_io =3D true, -}; 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Add mahua-specific regulator arrays and clk descriptor table, and use match_data to select the correct descriptor table per compatible string at probe time. Signed-off-by: Qiang Yu --- drivers/clk/qcom/tcsrcc-glymur.c | 99 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 96 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index e317003398d1..deca9b8794b4 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -13,6 +13,11 @@ =20 #include =20 +struct tcsrcc_glymur_data { + const struct qcom_clk_ref_desc *descs; + size_t num_descs; +}; + static const char * const glymur_tcsr_tx0_rx5_regulators[] =3D { "vdda-refgen3-0p9", "vdda-refgen3-1p2", @@ -40,6 +45,25 @@ static const char * const glymur_tcsr_tx1_rpt012_rx2_reg= ulators[] =3D { "vdda-qrefrx2-0p9", }; =20 +static const char * const mahua_tcsr_tx1_rpt01_rx1_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", +}; + +static const char * const mahua_tcsr_tx1_rpt012_rx2_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", +}; + static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -111,17 +135,86 @@ static const struct qcom_clk_ref_desc tcsr_cc_glymur_= clk_descs[] =3D { }, }; =20 +static const struct qcom_clk_ref_desc tcsr_cc_mahua_clk_descs[] =3D { + [TCSR_EDP_CLKREF_EN] =3D { + .name =3D "tcsr_edp_clkref_en", + .offset =3D 0x60, + }, + [TCSR_PCIE_2_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_2_clkref_en", + .offset =3D 0x4c, + .regulator_names =3D mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, + [TCSR_PCIE_3_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_3_clkref_en", + .offset =3D 0x54, + .regulator_names =3D mahua_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators), + }, + [TCSR_PCIE_4_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_4_clkref_en", + .offset =3D 0x58, + .regulator_names =3D mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, + [TCSR_USB2_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_1_clkref_en", + .offset =3D 0x6c, + }, + [TCSR_USB2_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_2_clkref_en", + .offset =3D 0x70, + }, + [TCSR_USB2_3_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_3_clkref_en", + .offset =3D 0x74, + }, + [TCSR_USB2_4_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_4_clkref_en", + .offset =3D 0x88, + }, + [TCSR_USB3_0_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_0_clkref_en", + .offset =3D 0x64, + }, + [TCSR_USB3_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_1_clkref_en", + .offset =3D 0x68, + }, + [TCSR_USB4_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_1_clkref_en", + .offset =3D 0x44, + }, + [TCSR_USB4_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_2_clkref_en", + .offset =3D 0x5c, + }, +}; + +static const struct tcsrcc_glymur_data tcsr_cc_glymur_data =3D { + .descs =3D tcsr_cc_glymur_clk_descs, + .num_descs =3D ARRAY_SIZE(tcsr_cc_glymur_clk_descs), +}; + +static const struct tcsrcc_glymur_data tcsr_cc_mahua_data =3D { + .descs =3D tcsr_cc_mahua_clk_descs, + .num_descs =3D ARRAY_SIZE(tcsr_cc_mahua_clk_descs), +}; + static const struct of_device_id tcsr_cc_glymur_match_table[] =3D { - { .compatible =3D "qcom,glymur-tcsr" }, + { .compatible =3D "qcom,glymur-tcsr", .data =3D &tcsr_cc_glymur_data }, + { .compatible =3D "qcom,mahua-tcsr", .data =3D &tcsr_cc_mahua_data }, { } }; MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table); =20 static int tcsr_cc_glymur_probe(struct platform_device *pdev) { + const struct tcsrcc_glymur_data *data =3D device_get_match_data(&pdev->de= v); + return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config, - tcsr_cc_glymur_clk_descs, - ARRAY_SIZE(tcsr_cc_glymur_clk_descs)); + data->descs, data->num_descs); } =20 static struct platform_driver tcsr_cc_glymur_driver =3D { --=20 2.34.1 From nobody Mon Jun 8 16:32:50 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9E792DEA93 for ; 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Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index c98dfb3941fa..be8497ef0da3 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -354,6 +354,26 @@ &usb_1 { status =3D "okay"; }; =20 +&tcsr { + vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx5-0p9-supply =3D <&vreg_l3f_e0_0p72>; + vdda-qreftx0-0p9-supply =3D <&vreg_l3f_e0_0p72>; + vdda-qreftx0-1p2-supply =3D <&vreg_l4h_e0_1p2>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304d4222060sm691653eec.29.2026.05.27.19.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 19:29:29 -0700 (PDT) From: Qiang Yu Date: Wed, 27 May 2026 19:29:17 -0700 Subject: [PATCH v4 6/7] arm64: dts: qcom: mahua: Add QREF regulator supplies to TCSR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260527-tcsr_qref_0527-v4-6-ded83866c9d9@oss.qualcomm.com> References: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> In-Reply-To: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu , krishna.chundru@oss.qualcomm.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779935361; l=1791; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=9FZHk8D4zHs6knN/tvir728/vX0PR2DvuCRo3y6q31w=; b=eYyn85cRgwDDB/YpWyAJfuJjduiRtwbqwZMpnEsTKvCOI3RVwRimdZ0bP1dbxHouGIYQ2qeVZ R/P3sr11VDcBmNvu/Qzj4kCqikqo50jdnj2dEOFvPGXkSYgQ6gxQVAx X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-ORIG-GUID: vag9hPxwFjEZ5xq2EZ5VQXqEXjox1keX X-Proofpoint-GUID: vag9hPxwFjEZ5xq2EZ5VQXqEXjox1keX X-Authority-Analysis: v=2.4 cv=E/r9Y6dl c=1 sm=1 tr=0 ts=6a17a88b cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=J05kOiREooJSWT36y8oA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDAyMSBTYWx0ZWRfXwY5WuMQHvT5J 1CYIfB4qPW6AMdJq5CMzjo26kMejHTzTp3WtOapIY5pwPSuRbY3Ri8//XaCWGW1/FaG0qHvGMF/ d+8hPQrUoBuACu3+OMHyO9n4Ll/HG15Fnwpm+x//yIZTC8veu39haKZsSM4yamdgbZnwReu/0ik mCiHzn7ZpkBOiA6Poulw3/mfslZDlN/MuFEjGHFcv2sE58q5CEJIWucW1SOyEly/4zmYNDuestM 2CaoC2DrQy0okJqhl2g3oPgp9mVrDmT3m7swD0uP4LWnfuBkFEcmyxDjbuwUKdd8/NuL10ADdL7 U09LBc8VV+NLOsQiiVebmVpBaT61zZUxgu6FzQiHP8+nKTqaMF4H+34/Le+MGPwwcW2hPi3A9mR ph53PpQeBWxxLbwPXw68RJtlEHlvG3Yt7OqI1siRpqbBD256x9j70X9BEqMLawsKcIW8tL1Vf+E d7VGNWElBCnkXtHhYSQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-27_05,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280021 Mahua has a different PCIe QREF topology from glymur. Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies for the PCIe clkref paths on the CRD board. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/mahua-crd.dts | 15 +++++++++++++++ arch/arm64/boot/dts/qcom/mahua.dtsi | 4 ++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/q= com/mahua-crd.dts index 9c8244e892dd..8b42f5174b31 100644 --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -19,3 +19,18 @@ / { model =3D "Qualcomm Technologies, Inc. Mahua CRD"; compatible =3D "qcom,mahua-crd", "qcom,mahua"; }; + +&tcsr { + vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrpt5-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx3-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qreftx1-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-refgen3-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-refgen3-1p2-supply =3D <&vreg_l4f_e1_1p08>; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi index 22822b6b2e8b..eb45adc8a0a2 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -286,6 +286,10 @@ gpuss-4-critical { }; }; =20 +&tcsr { + compatible =3D "qcom,mahua-tcsr", "syscon"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304d4222060sm691653eec.29.2026.05.27.19.29.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 19:29:30 -0700 (PDT) From: Qiang Yu Date: Wed, 27 May 2026 19:29:18 -0700 Subject: [PATCH v4 7/7] arm64: dts: qcom: mahua: Switch pcie5_phy ref clock to RPMH_CXO_CLK Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260527-tcsr_qref_0527-v4-7-ded83866c9d9@oss.qualcomm.com> References: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> In-Reply-To: <20260527-tcsr_qref_0527-v4-0-ded83866c9d9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu , krishna.chundru@oss.qualcomm.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779935361; l=993; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=4YeWlIEukC55Yr2J3TwKx6HzkQvNRDSFgt+i8fnXgCE=; b=COh3DLSrUdls4S9gugZcPaAmxGOWG2zHoFNWQeMaQwF0siTs3LgLdHwH7udGTkA7m5AZol4NA NGkgV3i0rAvATSrWtmxtT3wBl0lboI0maZuI9rRecrfHpqUXoUSqsZk X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=VeXH+lp9 c=1 sm=1 tr=0 ts=6a17a88c cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=CR5IuhOMo0Dix3IxAI8A:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI4MDAyMSBTYWx0ZWRfX5NpHiZhNbR/g j48cRUt2mQJYQSd/XgoqsCgVwt+jcK39NFvwwOGXpfcSqRpRpxqFQzpJ1Tkkr0TrsJcONMb6Vxx om1Y3zAHeJLei8+8pFwrCOAfXLm50fOEQLrExLdklQoLgX0Ld9Hp5RPrxtmTeOP8WlC+7o9Qwmu L15an4QrPcv4E+D2s5ys3DNe/TaQS8nrrRqXHIWIOpWDQxREag1tkLu5U0H/mvww4g1g2qDXMEn HMbx5YyIWYnyL+GddiLek5Tp4xSjLUiR6F1fAWUYFSPGyJgN1dxqftm3EWoiuKLA1EjxGkaU3ZV krjXQiqxeZa0GbYKYBLAILYA/3xukWOIqWdbvIxX2qjsFeAbJ++EhJhpfENW2fjdxw7422g4yGS p6hH8j500thNT+bF4/G69JP0iFtCJDEGRyBDKIHUbwmQFF8UD1vpQHZgbAhjXBiyIm2XqGmtYNW Uyou53JXWRv1YXxnJEA== X-Proofpoint-GUID: agS08U8EN_QXpq8GpVBKplDh76MHFHZb X-Proofpoint-ORIG-GUID: agS08U8EN_QXpq8GpVBKplDh76MHFHZb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-27_05,2026-05-26_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605280021 PCIe5 PHY on Mahua gets refclk from CXO0 pad directly, so no QREF clkref_en voting is required. Override the clock list to use RPMH_CXO_CLK directly instead. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/mahua.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi index eb45adc8a0a2..e6c059708912 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -115,6 +115,15 @@ &oobm_ss_noc { compatible =3D "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; }; =20 +&pcie5_phy { + clocks =3D <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; +}; + &pcie_east_anoc { compatible =3D "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; }; --=20 2.34.1