From nobody Mon Jun 8 16:30:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC0D82DAFA9; Thu, 28 May 2026 03:39:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779939572; cv=none; b=PV2k0CkBK/VYmEmg39n6AZ7ngaaOhQP8qXW4IP8WSwagQPuJZLTQWXkYBGpEZHdX4DcxIKk48NLpaMfkoPhHgc8Vu+FfMA/66TD8WDPLQVZNBH9JB/YJtF9uvr4d8KCMXtgPBOPESk/E1rtp78DLm7c+ZWzxeS3VYx7YyJpl/C0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779939572; c=relaxed/simple; bh=0HNKn9uJOrUj5fdAKjFadUhpFBPIo0H4vtoICGI+Ris=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PExukWjh3SfH622kRKMUZx091WwVMNiikctFPWN6xOaJwFa4WCe7r4k7qm8qEvWoOD4yC2papiCYPZ5W9tuphVqjsf4IEgy9ne2u2qAik6g+lTcnS6bcszp7ZrZbib9i8gFEpzBtpVhjewFxTJvUesmcIRV/iDUp+MFR6LG+Vk8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SRQrhWCB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SRQrhWCB" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7AA0FC2BCB4; Thu, 28 May 2026 03:39:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779939570; bh=0HNKn9uJOrUj5fdAKjFadUhpFBPIo0H4vtoICGI+Ris=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SRQrhWCB5i0DZpAw1PMB1w3us7LsL87HiCzxtSmZjRpq8ZxNQQ03HcxjimwdUiQLW pe9Vn8MNegALu7pN47E6vOyshKlCqvvIq27xq/OZnAvmWO8H5ckFAfkTMTOMSMcFVU Ugc1HiEktmkkCBZ1q4UkQrg99O63eHeh7I0vl/BzQDKrXSAJ1HInmHkAdhw3gpy6L4 FOqeVioAydHOzhbukwatvtBYk0UBWtn7YYYT0HYDRhLt74PktiSZz6SLasCI9PBRaP Sq13hbkUDhph6E9WqJSSUgy3aN7TRC9IvR0Y+Uf2+ikTYSsHtspGjFawgOK6w+ea4+ tT2vUoKvABmLg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71C76CD6E43; Thu, 28 May 2026 03:39:30 +0000 (UTC) From: Rudraksha Gupta via B4 Relay Date: Wed, 27 May 2026 20:39:28 -0700 Subject: [PATCH v2 1/3] dt-bindings: opp: Allow optional -vN suffix in opp-microvolt property name Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260527-expressatt_cpufreq-v2-1-b9b7726ccb6d@gmail.com> References: <20260527-expressatt_cpufreq-v2-0-b9b7726ccb6d@gmail.com> In-Reply-To: <20260527-expressatt_cpufreq-v2-0-b9b7726ccb6d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Rudraksha Gupta X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779939570; l=1182; i=guptarud@gmail.com; s=20240916; h=from:subject:message-id; bh=z/WcStOsVzdMFWp8uRFOe40/ecbf/NOss5Qfrb51yd8=; b=jftSPMYmys0+D6DQdiGgQPXjZmjbpCJ43RowmEacOFhKVXHINvYiKqyXVmVPmpdys0oFWSFLG KZ/LWB0W1CoAA7kuvyh7URIahwHeLXLrxfS7i0m1crvJLgfYUv0pfF/ X-Developer-Key: i=guptarud@gmail.com; a=ed25519; pk=ETrudRugWAtOpr0OhRiheQ1lXM4Kk4KGFnBySlKDi2I= X-Endpoint-Received: by B4 Relay for guptarud@gmail.com/20240916 with auth_id=211 X-Original-From: Rudraksha Gupta Reply-To: guptarud@gmail.com From: Rudraksha Gupta The qcom-cpufreq-nvmem driver generates prop_name as "speed%d-pvs%d-v%d" for Krait SoCs, resulting in property names like opp-microvolt-speed0-pvs0-v0. The existing schema regex only allows opp-microvolt-speed[0-9]+-pvs[0-9]+ without the trailing version suffix. Extend the regex to optionally match a -v[0-9]+ suffix so that devicetrees using the full prop_name pass schema validation. Assisted-by: Claude:claude-opus-4.6 Signed-off-by: Rudraksha Gupta --- Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/D= ocumentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index fd04d060c1de..846f49a99484 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -81,7 +81,7 @@ patternProperties: required-opps: true =20 patternProperties: - '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true + '^opp-microvolt-speed[0-9]+-pvs[0-9]+(-v[0-9]+)?$': true =20 required: - opp-hz --=20 2.54.0 From nobody Mon Jun 8 16:30:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8558311C2F; Thu, 28 May 2026 03:39:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779939571; cv=none; b=jFgOggfcdyZ795nnRT7vc0yAs0iZ8roxzt9J7dO+axTBhDlo43PVdKLbRwB41CitSYmaRTkuGlqCfuZZvqdC5A4yVXf2qEEFcW96tVHpx8JLtweG/r6rq1DU2ITXwasOn036kFbuzM/bgB7jVwZkM1g5ZLexQaYtSYQLcgWhZkY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779939571; c=relaxed/simple; bh=o8kNJddvVcrK7IoCVMe+UkaLiQ35HZDprvVYZkVvtAU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jog/+RZZ+XtSob89PJRupCxKZeZgjQFy0wfZth10zcnlqasoVLzwC3oSNwdC5l4cDd91oUrTzXfu7VWCxoeOYPbGfQjFJNSLTPJwtqtUg3leIOkK3os3matCTWni9/WTahURkxnBuvhF1D6POx+eW9Ta1U5szymBxiQqHaWqP6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J7nemYBs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J7nemYBs" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9FB66C4AF0F; Thu, 28 May 2026 03:39:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779939570; bh=o8kNJddvVcrK7IoCVMe+UkaLiQ35HZDprvVYZkVvtAU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=J7nemYBs2SODUE/Zv0LBj0PoWDb+ZxkjfWC8UQMk/HW1QBn4sxisvbgradguMYrDV ipIsyBKwID1OTmI09oDRZs8uQpnLrOO7dgTfkkOFVMmsy1JcbjznM+MmVq8tnfYEeE CTJcShUqiymWrrWDb284H7koyjMI09ebUVRpSGHVlG4xZl13JuNXq2pdklUlWxWibV OCG22QwHSDffNuMsXjdrAlBkRCcA5Nv7vtHWZ1Reazg4h/6+vjZu6DizzpvsLg+Ox+ 7z9z1c9HvD+1JrWWpipYq0XKAqJw6kMFdFzWhfoDDsUj0e1kqTU/InpmCs1YmTDIDq NagLpq69SuI9g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93FC6CD6E45; Thu, 28 May 2026 03:39:30 +0000 (UTC) From: Rudraksha Gupta via B4 Relay Date: Wed, 27 May 2026 20:39:29 -0700 Subject: [PATCH v2 2/3] soc: qcom: spm: Add MSM8960 SAW2 CPU support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260527-expressatt_cpufreq-v2-2-b9b7726ccb6d@gmail.com> References: <20260527-expressatt_cpufreq-v2-0-b9b7726ccb6d@gmail.com> In-Reply-To: <20260527-expressatt_cpufreq-v2-0-b9b7726ccb6d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Rudraksha Gupta X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779939570; l=2263; i=guptarud@gmail.com; s=20240916; h=from:subject:message-id; bh=7s3KzFwEWbUff19gMuQdq9JEmjBwkmq5B8cP8DEG7zQ=; b=+9RKQtGrbedqx6kW4YRBStMd7qCMFDl+Vusc3AVas4VSS/a4yxvKeFbtMhrKxZbhhd3vtBt/f 6s7f9UCjtcICfXCOFnNlbrGLQ4ftSr6RniljOOKDojFv/TEw59Zjt2r X-Developer-Key: i=guptarud@gmail.com; a=ed25519; pk=ETrudRugWAtOpr0OhRiheQ1lXM4Kk4KGFnBySlKDi2I= X-Endpoint-Received: by B4 Relay for guptarud@gmail.com/20240916 with auth_id=211 X-Original-From: Rudraksha Gupta Reply-To: guptarud@gmail.com From: Rudraksha Gupta The MSM8960 uses SAW2 v1.1, the same hardware version as the APQ8064. Add SPM register data so that the SAW2 driver can program the correct SPM sequences and PMIC parameters for MSM8960 CPUs. Link: https://github.com/CyanogenMod/android_kernel_samsung_d2/blob/0dbe2b5= 6847b304d30b809dfd08ba3b4a61d9af8/arch/arm/mach-msm/board-express.c#L3265-L= 3285 Link: https://github.com/CyanogenMod/android_kernel_samsung_d2/blob/0dbe2b5= 6847b304d30b809dfd08ba3b4a61d9af8/arch/arm/mach-msm/board-express.c#L3353-L= 3381 Assisted-by: Claude:claude-opus-4.6 Signed-off-by: Rudraksha Gupta --- drivers/soc/qcom/spm.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index f75659fff287..fb3ec8aa42b0 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -233,7 +233,7 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] =3D { =20 static void smp_set_vdd_v1_1(void *data); =20 -/* SPM register data for 8064 */ +/* SPM register data for 8064, 8960 */ static struct linear_range spm_v1_1_regulator_range =3D REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500); =20 @@ -253,6 +253,22 @@ static const struct spm_reg_data spm_reg_8064_cpu =3D { .ramp_delay =3D 1250, }; =20 +static const struct spm_reg_data spm_reg_8960_cpu =3D { + .reg_offset =3D spm_reg_offset_v1_1, + .spm_cfg =3D 0x1f, + .pmic_dly =3D 0x03020004, + .pmic_data[0] =3D 0x0084009c, + .pmic_data[1] =3D 0x00a4001c, + .seq =3D { 0x03, 0x0f, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01, + 0x10, 0x54, 0x30, 0x0c, 0x24, 0x30, 0x0f }, + .start_index[PM_SLEEP_MODE_STBY] =3D 0, + .start_index[PM_SLEEP_MODE_SPC] =3D 2, + .set_vdd =3D smp_set_vdd_v1_1, + .range =3D &spm_v1_1_regulator_range, + .init_uV =3D 1300000, + .ramp_delay =3D 1250, +}; + static inline void spm_register_write(struct spm_driver_data *drv, enum spm_reg reg, u32 val) { @@ -501,6 +517,8 @@ static const struct of_device_id spm_match_table[] =3D { .data =3D &spm_reg_8974_8084_cpu }, { .compatible =3D "qcom,apq8064-saw2-v1.1-cpu", .data =3D &spm_reg_8064_cpu }, + { .compatible =3D "qcom,msm8960-saw2-cpu", + .data =3D &spm_reg_8960_cpu }, { }, }; MODULE_DEVICE_TABLE(of, spm_match_table); --=20 2.54.0 From nobody Mon Jun 8 16:30:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 877673112AB; Thu, 28 May 2026 03:39:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779939571; cv=none; b=J1b80ggUDVGC+qxlCSl8C2pZapwKegQXcfed0NHQV9JWgRdm1X9X9f635K72en+hXKnNPgtIlQA6krgKTKhRG3H/k2EZaz4aUonJxRvy5Mb/EG7Veb+60SNp+a0RJIBhoQB2v6nHPdIAcUgvQm/M+o3jtWmloigBh4H1gAHWUcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779939571; c=relaxed/simple; bh=95CTCcnU8taxi9/mgQTgRaCweFn/W7gXcVo+1QPHOWs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RILD0opwUVpAJheoR1lU3x5O68oQg7PksIhSPjDhJp0dAq067DVk/JjDiOWbu2IrJz6cgQK5kCJ97n4h4B4t1mMAwTuwj1kHMJ0R0tCqDK0K5LnE/hQa31FQyg/MmV3k/TuUGaq7xChXSfqSM7w2ta+K6lXUmCE6yDb2x+RF4jQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PaWe9U4x; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PaWe9U4x" Received: by smtp.kernel.org (Postfix) with ESMTPS id A8B0DC2BCFA; Thu, 28 May 2026 03:39:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779939570; bh=95CTCcnU8taxi9/mgQTgRaCweFn/W7gXcVo+1QPHOWs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PaWe9U4xs8ElwIOz5jiJRxCx3oHTqjT+hxgtggjSrN7hDxw/ASNKmeb5XCxFwh+uf tEzhQiE7DRsWLB2gxDIpYlJ9t1ZaOGacibNo2eq+S5bcSkYZBFT1i+vBxS9M78ckZf OobzDTlWrfC25LnnmFcWNvWIo/po3g3/80Ac3rs8zbWBbX2/33m019Z6K6l/EwRWQ6 XP6uWvi+6cr76VgK7Nz1fFT0ZI34ZOfeH0fAXey0RMEC392LyainWFvx7J0PkMKW/5 mePTXSYumsPYHH6+ZaGIwybwu08XFZk/YB5NXKLQiFp5GmR0CySiF05bkfXR+BHjSm 0dnudb7g5bDxg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1995CD5BD1; Thu, 28 May 2026 03:39:30 +0000 (UTC) From: Rudraksha Gupta via B4 Relay Date: Wed, 27 May 2026 20:39:30 -0700 Subject: [PATCH v2 3/3] ARM: dts: qcom: msm8960: Add CPU frequency scaling support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260527-expressatt_cpufreq-v2-3-b9b7726ccb6d@gmail.com> References: <20260527-expressatt_cpufreq-v2-0-b9b7726ccb6d@gmail.com> In-Reply-To: <20260527-expressatt_cpufreq-v2-0-b9b7726ccb6d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Rudraksha Gupta , Antony Kurniawan Soemardi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779939570; l=5719; i=guptarud@gmail.com; s=20240916; h=from:subject:message-id; bh=WlqrFZxEtlslS92JpD8deBZvwae3glnW+krKqNCk7sI=; b=wIHakbLcgl2Yb+LsQMAyCOtD+o3Er80lkUYw6OeRoWlKaEQjEV9tuRe8Ls9cBuNICtzRzPLFX sM2CzwKqIXgDfCa5j4LQH5TR21RmpbynpFq+e/6ShOOX2uRlzCEfYPi X-Developer-Key: i=guptarud@gmail.com; a=ed25519; pk=ETrudRugWAtOpr0OhRiheQ1lXM4Kk4KGFnBySlKDi2I= X-Endpoint-Received: by B4 Relay for guptarud@gmail.com/20240916 with auth_id=211 X-Original-From: Rudraksha Gupta Reply-To: guptarud@gmail.com From: Rudraksha Gupta Enable Krait DVFS on MSM8960 by adding the required device tree nodes: - OPP table with 12 operating points from 384 MHz to 1.512 GHz, with per-PVS voltages for slow, nominal, and fast silicon bins. - Krait clock controller (krait-cc-v1) driving the CPU muxes from PLL9/PLL10, ACC aux outputs, and PXO. - PVS efuse nvmem cell in qfprom for the cpufreq-nvmem driver to read the speed-bin and process voltage class. - CPU idle state for Standalone Power Collapse (SPC). - operating-points-v2, clocks, cpu-supply, and cpu-idle-states wired into both CPU nodes. Link: https://github.com/CyanogenMod/android_kernel_samsung_d2/blob/0dbe2b5= 6847b304d30b809dfd08ba3b4a61d9af8/arch/arm/mach-msm/acpuclock-8960.c#L120-L= 235 Assisted-by: Claude:claude-opus-4.6 Tested-by: Antony Kurniawan Soemardi Signed-off-by: Rudraksha Gupta --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 129 +++++++++++++++++++++++++++= ++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8960.dtsi index a427f0f41cd1..3bb78a704850 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -54,6 +54,10 @@ cpu@0 { reg =3D <0>; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + clocks =3D <&kraitcc 0>; + cpu-supply =3D <&saw0_vreg>; + cpu-idle-states =3D <&cpu_spc>; next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; @@ -64,6 +68,10 @@ cpu@1 { reg =3D <1>; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; + operating-points-v2 =3D <&cpu_opp_table>; + clocks =3D <&kraitcc 1>; + cpu-supply =3D <&saw1_vreg>; + cpu-idle-states =3D <&cpu_spc>; next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; @@ -74,6 +82,123 @@ l2: l2-cache { cache-level =3D <2>; cache-unified; }; + + idle-states { + cpu_spc: cpu-spc { + compatible =3D "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us =3D <400>; + exit-latency-us =3D <900>; + min-residency-us =3D <3000>; + }; + }; + }; + + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2-krait-cpu"; + nvmem-cells =3D <&pvs_efuse>; + + opp-384000000 { + opp-hz =3D /bits/ 64 <384000000>; + opp-microvolt-speed0-pvs0-v0 =3D <950000>; + opp-microvolt-speed0-pvs1-v0 =3D <900000>; + opp-microvolt-speed0-pvs3-v0 =3D <850000>; + opp-supported-hw =3D <0x1>; + }; + + opp-486000000 { + opp-hz =3D /bits/ 64 <486000000>; + opp-microvolt-speed0-pvs0-v0 =3D <975000>; + opp-microvolt-speed0-pvs1-v0 =3D <925000>; + opp-microvolt-speed0-pvs3-v0 =3D <875000>; + opp-supported-hw =3D <0x1>; + }; + + opp-594000000 { + opp-hz =3D /bits/ 64 <594000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1000000>; + opp-microvolt-speed0-pvs1-v0 =3D <950000>; + opp-microvolt-speed0-pvs3-v0 =3D <900000>; + opp-supported-hw =3D <0x1>; + }; + + opp-702000000 { + opp-hz =3D /bits/ 64 <702000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1025000>; + opp-microvolt-speed0-pvs1-v0 =3D <975000>; + opp-microvolt-speed0-pvs3-v0 =3D <925000>; + opp-supported-hw =3D <0x1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1075000>; + opp-microvolt-speed0-pvs1-v0 =3D <1025000>; + opp-microvolt-speed0-pvs3-v0 =3D <975000>; + opp-supported-hw =3D <0x1>; + }; + + opp-918000000 { + opp-hz =3D /bits/ 64 <918000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1100000>; + opp-microvolt-speed0-pvs1-v0 =3D <1050000>; + opp-microvolt-speed0-pvs3-v0 =3D <1000000>; + opp-supported-hw =3D <0x1>; + }; + + opp-1026000000 { + opp-hz =3D /bits/ 64 <1026000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1125000>; + opp-microvolt-speed0-pvs1-v0 =3D <1075000>; + opp-microvolt-speed0-pvs3-v0 =3D <1025000>; + opp-supported-hw =3D <0x1>; + }; + + opp-1134000000 { + opp-hz =3D /bits/ 64 <1134000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1175000>; + opp-microvolt-speed0-pvs1-v0 =3D <1125000>; + opp-microvolt-speed0-pvs3-v0 =3D <1075000>; + opp-supported-hw =3D <0x1>; + }; + + opp-1242000000 { + opp-hz =3D /bits/ 64 <1242000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1200000>; + opp-microvolt-speed0-pvs1-v0 =3D <1150000>; + opp-microvolt-speed0-pvs3-v0 =3D <1100000>; + opp-supported-hw =3D <0x1>; + }; + + opp-1350000000 { + opp-hz =3D /bits/ 64 <1350000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1225000>; + opp-microvolt-speed0-pvs1-v0 =3D <1175000>; + opp-microvolt-speed0-pvs3-v0 =3D <1125000>; + opp-supported-hw =3D <0x1>; + }; + + opp-1458000000 { + opp-hz =3D /bits/ 64 <1458000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1237500>; + opp-microvolt-speed0-pvs1-v0 =3D <1187500>; + opp-microvolt-speed0-pvs3-v0 =3D <1137500>; + opp-supported-hw =3D <0x1>; + }; + + opp-1512000000 { + opp-hz =3D /bits/ 64 <1512000000>; + opp-microvolt-speed0-pvs0-v0 =3D <1250000>; + opp-microvolt-speed0-pvs1-v0 =3D <1200000>; + opp-microvolt-speed0-pvs3-v0 =3D <1150000>; + opp-supported-hw =3D <0x1>; + }; + }; + + kraitcc: clock-controller { + compatible =3D "qcom,krait-cc-v1"; + clocks =3D <&gcc PLL9>, <&gcc PLL10>, <&acc0>, <&acc1>, <&pxo_board>; + clock-names =3D "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; + #clock-cells =3D <1>; }; =20 memory@80000000 { @@ -112,6 +237,10 @@ qfprom: efuse@700000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 + pvs_efuse: pvs@c0 { + reg =3D <0xc0 0x04>; + }; + tsens_calib: calib@404 { reg =3D <0x404 0x10>; }; --=20 2.54.0