From nobody Mon Jun 8 21:52:27 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4999A224234; Tue, 26 May 2026 12:53:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799983; cv=none; b=hU4vmyjMCrdMkFBLfBDmbY4wGj4E1h+Dn5pYRXb6j8xBUf881j3Vq94rYH6AIIAI7YL9tzmfEeI4U9e6W8+xfoK7aIel3iQrUI6RtfCl9MxwsTne2PRVF7uv/221UWZSsvpHiyCbJf3UdcaLmYBszTraAIR64aJibEHLA/dDTKw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799983; c=relaxed/simple; bh=xf2yltQCPL4KYbVDKfNIsg8mC4dPbeakx6my0quoUbs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZcjSGVpFAp399Y6SSL+vkJJ7RU1oT/Ane/zNP/3ifZkbHQM43OZ2IZuWu72kc794SaUOKN8Z+RKm4tkZdASYos28kw0FOParbKejjywkXYPemthRAQ0ldeljLgqcX8JP0YFxRMrp+6jzb5KWEIiTSzovuBd31TWMairuBmo5vbA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxrOmrlxVqGWgNAA--.36459S3; Tue, 26 May 2026 20:52:59 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxWcGplxVqbZiRAA--.1284S3; Tue, 26 May 2026 20:52:59 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v5 1/6] LoongArch: KVM: Check irq validility in kvm_vcpu_ioctl_interrupt() Date: Tue, 26 May 2026 20:52:50 +0800 Message-Id: <20260526125256.2511876-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526125256.2511876-1-maobibo@loongson.cn> References: <20260526125256.2511876-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxWcGplxVqbZiRAA--.1284S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Function kvm_vcpu_ioctl_interrupt() can be called from userspace, here add irq validility cheking in kvm_vcpu_ioctl_interrupt(). Fixes: f45ad5b8aa93 ("LoongArch: KVM: Implement vcpu interrupt operations") Cc: stable@vger.kernel.org Signed-off-by: Bibo Mao --- arch/loongarch/kvm/vcpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index e28084c49e68..df5be9b265e8 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -1487,6 +1487,11 @@ void kvm_lose_fpu(struct kvm_vcpu *vcpu) int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *= irq) { int intr =3D (int)irq->irq; + unsigned int vector; + + vector =3D abs(intr); + if (vector >=3D EXCCODE_INT_NUM) + return -EINVAL; =20 if (intr > 0) kvm_queue_irq(vcpu, intr); --=20 2.39.3 From nobody Mon Jun 8 21:52:27 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9D58722B594; Tue, 26 May 2026 12:53:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799983; cv=none; b=sCOuOObxzBucV6JtSF+QOtRlnCkf8CzrApJbytwCxDuNzNV4F9ic25HEXcWeM+rBz1vVJNnijJUCr9BZIIQ09BTIhLXQfFnhVXkvH4UPFjg3BPjepBrQ5Ss1HDhvhqsJV8fb1zt7C5QXVSdYDPCofN5o/uWdbQTfARLmnnlM0HE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799983; c=relaxed/simple; bh=YXvPAAq9mWglp8bbJDg6RlfHdjGIxJI5tkxM4tuS3Vk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZSHARRodAW3hXTyu2iWOAI1JHMDwzsF6mmTBx7nnAEIDe1tQZBVfoxNVM5By81DmaIeQPhMaQRwYjAt31nCu8ShjKasfiCmml76kLgAFKf8t0UZa88rXjgVSEBsZg6c/CCyhPA8Ef4DeHJ9K7OTHwlZhkYF5fnMsKmbqkRTeOx8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxncCslxVqHWgNAA--.14407S3; Tue, 26 May 2026 20:53:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxWcGplxVqbZiRAA--.1284S4; Tue, 26 May 2026 20:52:59 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/6] LoongArch: KVM: Check msgint feature in interrupt post Date: Tue, 26 May 2026 20:52:51 +0800 Message-Id: <20260526125256.2511876-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526125256.2511876-1-maobibo@loongson.cn> References: <20260526125256.2511876-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxWcGplxVqbZiRAA--.1284S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Interrupt AVEC is valid only if VM has msgint feature, and this feature is checked in interrupt handling. Since interrupt handling is executing in VM context switch, and it is hot path, here move the feature checking in interrupt post rather than interrupt handling. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 5 ----- arch/loongarch/kvm/vcpu.c | 14 +++++++++----- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index a18c60dffbba..48dd56aa4dc5 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -36,8 +36,6 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigne= d int priority) =20 switch (priority) { case INT_AVEC: - if (!kvm_guest_has_msgint(&vcpu->arch)) - break; dmsintc_inject_irq(vcpu); fallthrough; case INT_TI: @@ -75,9 +73,6 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned = int priority) =20 switch (priority) { case INT_AVEC: - if (!kvm_guest_has_msgint(&vcpu->arch)) - break; - fallthrough; case INT_TI: case INT_IPI: case INT_SWI0: diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index df5be9b265e8..ebd432da3ca4 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -1493,14 +1493,18 @@ int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,= struct kvm_interrupt *irq) if (vector >=3D EXCCODE_INT_NUM) return -EINVAL; =20 - if (intr > 0) + if (!kvm_guest_has_msgint(&vcpu->arch) && (vector =3D=3D INT_AVEC)) + return -EINVAL; + + /* + * Clear irq with INT_SWI0 (which is 0) is missing from SW side + * INT_SWI0 is cleared by guest kernel with the similar instruction + * clear_csr_estat(1 << INT_SWI0) + */ + if (intr >=3D 0) kvm_queue_irq(vcpu, intr); else if (intr < 0) kvm_dequeue_irq(vcpu, -intr); - else { - kvm_err("%s: invalid interrupt ioctl %d\n", __func__, irq->irq); - return -EINVAL; - } =20 kvm_vcpu_kick(vcpu); =20 --=20 2.39.3 From nobody Mon Jun 8 21:52:27 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8505A22759C; Tue, 26 May 2026 12:53:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799983; cv=none; b=asaduHwN78k1kYIKdDTawDkacmsacJD380uQKgxdXZeUWGVufKdfds57CEANEYYckXItcTVNFdrjrEQv3nDAySPdg3FL9vtcQjkSGF0lM8QTi9e1eTCKbvzxkNgY+/23SxzKqkPMmO3g52hTaCqAKNQ7dzeQmiU09r0SbAUl+fA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799983; c=relaxed/simple; bh=5v/YhmDMLJUxGqRTdK6KcWlJJbiOgeKq9doSJA+sBG4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WKX28sOLaiHBfplm9fjJKwZQ+zcKbyYadt+rFkG36ATKbp5IT1S7tmfQH7FtAVGeEFA6NCNBadLCLPfRP4vTF8PVYdIi0WbBU4X/nwtkM9A3v6VLiAxC77Y+naIdvBuYeIT9FsQD77gVmIBP3e6WKWOzYzuiu/ujJQ2gGT32n8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxzsCslxVqIWgNAA--.14660S3; Tue, 26 May 2026 20:53:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxWcGplxVqbZiRAA--.1284S5; Tue, 26 May 2026 20:53:00 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/6] LoongArch: KVM: Use existing macro about interrupt bit mask Date: Tue, 26 May 2026 20:52:52 +0800 Message-Id: <20260526125256.2511876-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526125256.2511876-1-maobibo@loongson.cn> References: <20260526125256.2511876-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxWcGplxVqbZiRAA--.1284S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With interrupt post, register CSR_GINTC and CSR_ESTAT is used, and CSR_ESTAT is used for percpu interrupt injection and CSR_GINTC is for external hardware interrupt injection. Here use existing macro about interrupt bit of register CSR_GINTC and CSR_ESTAT, rather than hard coded constant value. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_vcpu.h | 43 ++++++++++++++++++--------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_vcpu.h b/arch/loongarch/include= /asm/kvm_vcpu.h index 3784ab4ccdb5..efe26b04b35f 100644 --- a/arch/loongarch/include/asm/kvm_vcpu.h +++ b/arch/loongarch/include/asm/kvm_vcpu.h @@ -10,22 +10,37 @@ #include =20 /* Controlled by 0x5 guest estat */ -#define CPU_SIP0 (_ULCAST_(1)) -#define CPU_SIP1 (_ULCAST_(1) << 1) -#define CPU_PMU (_ULCAST_(1) << 10) -#define CPU_TIMER (_ULCAST_(1) << 11) -#define CPU_IPI (_ULCAST_(1) << 12) -#define CPU_AVEC (_ULCAST_(1) << 14) +#define CPU_SIP0 BIT(INT_SWI0) +#define CPU_SIP1 BIT(INT_SWI1) +#define CPU_HWI0 BIT(INT_HWI0) +#define CPU_HWI1 BIT(INT_HWI1) +#define CPU_HWI2 BIT(INT_HWI2) +#define CPU_HWI3 BIT(INT_HWI3) +#define CPU_HWI4 BIT(INT_HWI4) +#define CPU_HWI5 BIT(INT_HWI5) +#define CPU_HWI6 BIT(INT_HWI6) +#define CPU_HWI7 BIT(INT_HWI7) +#define CPU_PMU BIT(INT_PCOV) +#define CPU_TIMER BIT(INT_TI) +#define CPU_IPI BIT(INT_IPI) +#define CPU_AVEC BIT(INT_AVEC) +#define KVM_ESTAT_IRQ_MASK (CPU_SIP0 | CPU_SIP1 | CPU_PMU | CPU_TIMER \ + | CPU_IPI | CPU_AVEC) +#define KVM_ESTAT_HWI_MASK (CPU_HWI0 | CPU_HWI1 | CPU_HWI2 | CPU_HWI3 \ + | CPU_HWI4 | CPU_HWI5 | CPU_HWI6 | CPU_HWI7) =20 /* Controlled by 0x52 guest exception VIP aligned to estat bit 5~12 */ -#define CPU_IP0 (_ULCAST_(1)) -#define CPU_IP1 (_ULCAST_(1) << 1) -#define CPU_IP2 (_ULCAST_(1) << 2) -#define CPU_IP3 (_ULCAST_(1) << 3) -#define CPU_IP4 (_ULCAST_(1) << 4) -#define CPU_IP5 (_ULCAST_(1) << 5) -#define CPU_IP6 (_ULCAST_(1) << 6) -#define CPU_IP7 (_ULCAST_(1) << 7) +#define GINTC_VIP_DELTA (INT_HWI0 - CSR_GINTC_VIP_SHIFT) +#define CPU_IP0 BIT(INT_HWI0 - GINTC_VIP_DELTA) +#define CPU_IP1 BIT(INT_HWI1 - GINTC_VIP_DELTA) +#define CPU_IP2 BIT(INT_HWI2 - GINTC_VIP_DELTA) +#define CPU_IP3 BIT(INT_HWI3 - GINTC_VIP_DELTA) +#define CPU_IP4 BIT(INT_HWI4 - GINTC_VIP_DELTA) +#define CPU_IP5 BIT(INT_HWI5 - GINTC_VIP_DELTA) +#define CPU_IP6 BIT(INT_HWI6 - GINTC_VIP_DELTA) +#define CPU_IP7 BIT(INT_HWI7 - GINTC_VIP_DELTA) +#define KVM_GINTC_IRQ_MASK (CPU_IP0 | CPU_IP1 | CPU_IP2 | CPU_IP3 \ + | CPU_IP4 | CPU_IP5 | CPU_IP6 | CPU_IP7) =20 #define MNSEC_PER_SEC (NSEC_PER_SEC >> 20) =20 --=20 2.39.3 From nobody Mon Jun 8 21:52:27 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6B033248166; Tue, 26 May 2026 12:53:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779800000; cv=none; b=qm4bVNi6J1dCUtiHjQ4wxL6i75RW/7nFz6P+knX8nZbZz3xMIEQT868LOwFmMUaF88i73M8C/OUgefKTMSkLnc4pGuzWivazCgas7r0ypwQL4irW3eV9LUeNRC0v2BJirIX/PSy50RaLTDs1uEDhLjg9pNBTSdnrYZ8mhJEmHiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779800000; c=relaxed/simple; bh=AFs+WNya3mZde7xpB7WAr9WR9Ggo95jUIl2MIL6j13A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=j4/Es1iQqydHObYwoK58ei6tMdInbfckMPZRTDQQq3AcMuI3U2qevyWJPWWGTghkbRIE1kBlN8dpUWEp2y/VuYlS0gZPE28YJzVFrMPkeHLHJQWRda1i+sy2M5PDzmNY5sMZUsy+IUbeNGvQOiJC1CTPBOAsnNZ/ee/c3lFjcW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cxf+uulxVqJ2gNAA--.37968S3; Tue, 26 May 2026 20:53:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpsCulxVqb5iRAA--.44615S2; Tue, 26 May 2026 20:53:02 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/6] LoongArch: KVM: Inject interrupt with batch method Date: Tue, 26 May 2026 20:52:53 +0800 Message-Id: <20260526125256.2511876-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526125256.2511876-1-maobibo@loongson.cn> References: <20260526125256.2511876-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpsCulxVqb5iRAA--.44615S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With bitmask method, interrupt can be injected with batch mode, rather than one by one. Also remove unused array priority_to_irqp[] here. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 95 ++++++++++------------------------ 1 file changed, 28 insertions(+), 67 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index 48dd56aa4dc5..50081484336e 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -9,39 +9,16 @@ #include #include =20 -static unsigned int priority_to_irq[EXCCODE_INT_NUM] =3D { - [INT_TI] =3D CPU_TIMER, - [INT_IPI] =3D CPU_IPI, - [INT_SWI0] =3D CPU_SIP0, - [INT_SWI1] =3D CPU_SIP1, - [INT_HWI0] =3D CPU_IP0, - [INT_HWI1] =3D CPU_IP1, - [INT_HWI2] =3D CPU_IP2, - [INT_HWI3] =3D CPU_IP3, - [INT_HWI4] =3D CPU_IP4, - [INT_HWI5] =3D CPU_IP5, - [INT_HWI6] =3D CPU_IP6, - [INT_HWI7] =3D CPU_IP7, - [INT_AVEC] =3D CPU_AVEC, -}; - -static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority) +static void kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned long mask) { - unsigned int irq =3D 0; + unsigned long irq; unsigned long old, new; =20 - clear_bit(priority, &vcpu->arch.irq_pending); - if (priority < EXCCODE_INT_NUM) - irq =3D priority_to_irq[priority]; - - switch (priority) { - case INT_AVEC: - dmsintc_inject_irq(vcpu); - fallthrough; - case INT_TI: - case INT_IPI: - case INT_SWI0: - case INT_SWI1: + irq =3D mask & KVM_ESTAT_IRQ_MASK; + if (irq) { + if (irq & CPU_AVEC) + dmsintc_inject_irq(vcpu); + old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); set_gcsr_estat(irq); new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); @@ -49,34 +26,20 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsig= ned int priority) /* Inject TI if TVAL inverted */ if (new > old) set_gcsr_estat(CPU_TIMER); - break; - - case INT_HWI0 ... INT_HWI7: - set_csr_gintc(irq); - break; - - default: - break; } =20 - return 1; + irq =3D (mask >> GINTC_VIP_DELTA) & KVM_GINTC_IRQ_MASK; + if (irq) + set_csr_gintc(irq); } =20 -static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority) +static void kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned long mask) { - unsigned int irq =3D 0; + unsigned long irq; unsigned long old, new; =20 - clear_bit(priority, &vcpu->arch.irq_clear); - if (priority < EXCCODE_INT_NUM) - irq =3D priority_to_irq[priority]; - - switch (priority) { - case INT_AVEC: - case INT_TI: - case INT_IPI: - case INT_SWI0: - case INT_SWI1: + irq =3D mask & KVM_ESTAT_IRQ_MASK; + if (irq) { old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); clear_gcsr_estat(irq); new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); @@ -84,30 +47,28 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigne= d int priority) /* Inject TI if TVAL inverted */ if (new > old) set_gcsr_estat(CPU_TIMER); - break; - - case INT_HWI0 ... INT_HWI7: - clear_csr_gintc(irq); - break; - - default: - break; } =20 - return 1; + irq =3D (mask >> GINTC_VIP_DELTA) & KVM_GINTC_IRQ_MASK; + if (irq) + clear_csr_gintc(irq); } =20 void kvm_deliver_intr(struct kvm_vcpu *vcpu) { - unsigned int priority; - unsigned long *pending =3D &vcpu->arch.irq_pending; - unsigned long *pending_clr =3D &vcpu->arch.irq_clear; + unsigned long mask; =20 - for_each_set_bit(priority, pending_clr, EXCCODE_INT_NUM) - kvm_irq_clear(vcpu, priority); + mask =3D READ_ONCE(vcpu->arch.irq_clear); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_clear, 0); + kvm_irq_clear(vcpu, mask); + } =20 - for_each_set_bit(priority, pending, EXCCODE_INT_NUM) - kvm_irq_deliver(vcpu, priority); + mask =3D READ_ONCE(vcpu->arch.irq_pending); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_pending, 0); + kvm_irq_deliver(vcpu, mask); + } } =20 int kvm_pending_timer(struct kvm_vcpu *vcpu) --=20 2.39.3 From nobody Mon Jun 8 21:52:27 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 69E2923909F; Tue, 26 May 2026 12:53:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799997; cv=none; b=a4+lTE08n2Et8JgvOOc/Tu06bjiuuC0LzUpCKLa54GOk8eNhLtbUid3QL6Sn/sRDmkSqEWwxdTSrpm4/L4g9EaTz/Mxgni1wP3YG3Wwsn5TtJkDUu7uNyBfHQy4PJJeUktNVGwHINLAbvebPu+b8bXeq1cU+PxKVjkYvP7w7aRA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799997; c=relaxed/simple; bh=AiEVm5E86Hgwhs2FlN6CBUirFybgc1DvnzdIK6J01do=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fIyLhfWy+ze7GFC4KkU6wueGeMeB8jILnijDs/X9xc0g7H3uX5R30O1V12U4CanuTiwUR3LvO8NhUmnadtK7850FcHs+r2Uluv354CntStvKfe1FPkCohGyGssmWh8NLm42iiETeZBXZZSDZOzfKD9h8svEQGYK2j81XAp07V0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxT+qvlxVqLGgNAA--.37767S3; Tue, 26 May 2026 20:53:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpsCulxVqb5iRAA--.44615S3; Tue, 26 May 2026 20:53:03 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/6] LoongArch: KVM: Add valid bit check when set ESTAT CSR register Date: Tue, 26 May 2026 20:52:54 +0800 Message-Id: <20260526125256.2511876-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526125256.2511876-1-maobibo@loongson.cn> References: <20260526125256.2511876-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpsCulxVqb5iRAA--.44615S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" When set ESTAT CSR register in function _kvm_setcsr(), valid bit check is added here. Also interrupt CPU_AVEC is checked by msgint feature. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/vcpu.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index ebd432da3ca4..3c6726e00531 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -602,7 +602,7 @@ struct kvm_vcpu *kvm_get_vcpu_by_cpuid(struct kvm *kvm,= int cpuid) =20 static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *val) { - unsigned long gintc; + unsigned long gintc, estat; struct loongarch_csrs *csr =3D vcpu->arch.csr; =20 if (get_gcsr_flag(id) & INVALID_GCSR) @@ -621,8 +621,9 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned = int id, u64 *val) preempt_enable(); =20 /* ESTAT IP0~IP7 get from GINTC */ - gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff; - *val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) | (gintc << 2); + gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & KVM_GINTC_IRQ_MAS= K; + estat =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) & ~KVM_ESTAT_HWI_MA= SK; + *val =3D estat | (gintc << GINTC_VIP_DELTA); return 0; } =20 @@ -637,7 +638,8 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned = int id, u64 *val) =20 static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val) { - int ret =3D 0, gintc; + int ret =3D 0; + unsigned long gintc, estat; struct loongarch_csrs *csr =3D vcpu->arch.csr; =20 if (get_gcsr_flag(id) & INVALID_GCSR) @@ -648,11 +650,16 @@ static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigne= d int id, u64 val) =20 if (id =3D=3D LOONGARCH_CSR_ESTAT) { /* ESTAT IP0~IP7 inject through GINTC */ - gintc =3D (val >> 2) & 0xff; - kvm_set_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc); - - gintc =3D val & ~(0xffUL << 2); - kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, gintc); + gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & ~KVM_GINTC_IRQ_MA= SK; + gintc |=3D (val >> GINTC_VIP_DELTA) & KVM_GINTC_IRQ_MASK; + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc); + + /* only set valid ESTAT bits */ + estat =3D val & ~KVM_ESTAT_HWI_MASK; + estat &=3D CSR_ESTAT_IS | CSR_ESTAT_EXC | CSR_ESTAT_ESUBCODE; + if (!kvm_guest_has_msgint(&vcpu->arch)) + estat &=3D ~CPU_AVEC; + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, estat); =20 return ret; } --=20 2.39.3 From nobody Mon Jun 8 21:52:27 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 853AC238C36; Tue, 26 May 2026 12:53:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799993; cv=none; b=FLBR2fE0CqTDJ96pzR8ZqDKVgLWHgb3ytWlDgblsC9TvCyICRJJfxMswXbFc0E1/FPwjacH0yZhIUs7NIpz4sBZF3qajwapd+I/vPBza19o4BTa/EqwSWpONcjF6op62epnQg3Yccgs7Wr6+7kOah0barFxVEms6cjnpWfQ7YYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779799993; c=relaxed/simple; bh=OhZM1n+w+2YwGw6tdwAp/Kdasbom8NQOMvqLT/bxDE0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U8YaHpjo7x+O3uD9EL6jJoKkX0hZ9eEkqzjRXYLqV7I3sVqqxLiIFy0bFG+5XZGCesWcpB8ZQDEzu19pdv4VZkNHIjHoBzVPVV8XeP6upvdYYSXwIQT5mV8NVom3tnFOw2UvGJ3a0GtJc+b2llr9tiBTUJcNq59kSwyamIAciig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxsOqvlxVqL2gNAA--.38294S3; Tue, 26 May 2026 20:53:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpsCulxVqb5iRAA--.44615S4; Tue, 26 May 2026 20:53:03 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/6] LoongArch: KVM: Deliver interrupt after IN_GUEST_MODE is set Date: Tue, 26 May 2026 20:52:55 +0800 Message-Id: <20260526125256.2511876-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526125256.2511876-1-maobibo@loongson.cn> References: <20260526125256.2511876-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpsCulxVqb5iRAA--.44615S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Interrupt delivery should be called after IN_GUEST_MODE is set. Other threads may be posting interrupt however does not send IPI to the vCPU, since the vCPU is not in IN_GUEST_MODE. here move function call with kvm_deliver_intr() after IN_GUEST_MODE is set, and set mode with OUTSIDE_GUEST_MODE with atomic method. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/vcpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index 3c6726e00531..f8ce985dc97b 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -308,10 +308,10 @@ static int kvm_pre_enter_guest(struct kvm_vcpu *vcpu) * check vmid before vcpu enter guest */ local_irq_disable(); - kvm_deliver_intr(vcpu); kvm_deliver_exception(vcpu); /* Make sure the vcpu mode has been written */ smp_store_mb(vcpu->mode, IN_GUEST_MODE); + kvm_deliver_intr(vcpu); kvm_check_vpid(vcpu); =20 /* @@ -348,7 +348,7 @@ static int kvm_handle_exit(struct kvm_run *run, struct = kvm_vcpu *vcpu) u32 intr =3D estat & CSR_ESTAT_IS; u32 ecode =3D (estat & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; =20 - vcpu->mode =3D OUTSIDE_GUEST_MODE; + smp_store_mb(vcpu->mode, OUTSIDE_GUEST_MODE); =20 /* Set a default exit reason */ run->exit_reason =3D KVM_EXIT_UNKNOWN; --=20 2.39.3