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Miller" CC: Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v4 1/3] crypto: ti - Add support for SHA224/256/384/512 in DTHEv2 driver Date: Tue, 26 May 2026 15:13:51 +0530 Message-ID: <20260526094355.555712-2-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260526094355.555712-1-t-pratham@ti.com> References: <20260526094355.555712-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E65:EE_|CY5PR10MB6071:EE_ X-MS-Office365-Filtering-Correlation-Id: aac276ae-cb8d-45de-ca7b-08debb0b73c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|22082099003|18002099003|56012099003|3023799007; X-Microsoft-Antispam-Message-Info: hEDjm7ehbeCIAYmt3ItlvbTCGET2hlQMFNHKi5Hd6eRveD/bt3eUkCmDDHIgEwm/9//00WG/DOyIEiIL7aQANJ+ZB0yf+2GNSJalmdjCWz07GmkcCCejCMYow1g0qume6rXDG+nbmbrSrbfL/KRbJmCZHuj0+VAs082scPlWAoMyVuN6BbS5Py0ImKyq9ILj4eHsDGXn6FR6Ck+Sug4KSkORH4cz91SrhoBfhUZKZIZW/jbqf9mJLhBKAfyB00ipcaL7DL3Po18kuNb7VStEvS5yrmg4iylpT6a0yqjQIV1P6FOkYn71RK3TLEIAemmpf0M7gR2MiA84pFFRqEBsaz3w88nVsLz+cFQPvrdCqA2HxDeuTFmHrz1alCMJEKI0g+otgKKy6QOo+FaAqxUMZAleWEPL0luoPpLs1ncSZTAkLO6dfg3Educr1pGT3SwlcwLA3OD/yGSMGddTCaoIbi2lY4ht+KQ0aGT82JRctbcCLA/i2umXHTOIQMSmNyTZ7eZzN5GuZK6QqV1QtjPhSljT+/K+pM9+5EkKMgvpAvxvFI0eeu1CqSGD9ywIrpPDf5TR3Omn3y5ijfOkE6lt+kSAqj7OtajBTrDryocQsD3NZxgpa6Am++rxm8GEYL/7kSz4wvh9Ddifxj0PIJeoJ7hLFr1BKJ5JJ693ZbHSCAxSzvgQdOSpSjMtLQ6GUdO/ X-Forefront-Antispam-Report: CIP:198.47.23.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet200.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(22082099003)(18002099003)(56012099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rLZ40KMr0L1rFMnTx472kHpvuZwHgUsl6wwlvC9Tzwr2VimH+oGCIvNboeJZh4xN1fOXofXqJTCWXyUgjEQV1OPpzLEBWLFqnZ7CvzEs6WvKit8Ssn0mxEoejxGDjVZM/J7RI8f6ahUmbA46IhlmUhgkqmXBkGkk4bPuLXPJz4lFV4nSlT6QFgf+jkoAYyA1UKQWbmTEcly+gg74sfE3ETF/muldYACmcn6BDw6rjjGMjC34WUjhDO1Yap9GkdahzL83VMZUoNrXBuYUG4rMaiOZOXfN7h/S3Cx7babYjy1tRYExVwPeeR1aYqorUiRU87O5dkoZkgQJ3sfpNpXYe1cRXge4apT4kBzxxUsP6yaFPTSqxbMwKxxjgzjWm/SDmFGOzqVIJvE8P0dInJ1yiw/CI4KBthijqGr8ve6itmG3wCEiNcgO2sT0zcbqwWl+ X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2026 09:44:59.2983 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aac276ae-cb8d-45de-ca7b-08debb0b73c2 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E65.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR10MB6071 Content-Type: text/plain; charset="utf-8" Add support for SHA224, SHA256, SHA384, SHA512 algorithms in the Hashing Engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 2 + drivers/crypto/ti/Makefile | 2 +- drivers/crypto/ti/dthev2-aes.c | 6 +- drivers/crypto/ti/dthev2-common.c | 43 +- drivers/crypto/ti/dthev2-common.h | 47 ++- drivers/crypto/ti/dthev2-hash.c | 631 ++++++++++++++++++++++++++++++ 6 files changed, 717 insertions(+), 14 deletions(-) create mode 100644 drivers/crypto/ti/dthev2-hash.c diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 1a3a571ac8cef..90af2c7cb1c55 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -10,6 +10,8 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_XTS select CRYPTO_GCM select CRYPTO_CCM + select CRYPTO_SHA256 + select CRYPTO_SHA512 select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/Makefile b/drivers/crypto/ti/Makefile index b883078f203d7..a90bc97a52321 100644 --- a/drivers/crypto/ti/Makefile +++ b/drivers/crypto/ti/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_CRYPTO_DEV_TI_DTHEV2) +=3D dthev2.o -dthev2-objs :=3D dthev2-common.o dthev2-aes.o +dthev2-objs :=3D dthev2-common.o dthev2-aes.o dthev2-hash.o diff --git a/drivers/crypto/ti/dthev2-aes.c b/drivers/crypto/ti/dthev2-aes.c index eb5cd902dfb59..164e72c07ee3f 100644 --- a/drivers/crypto/ti/dthev2-aes.c +++ b/drivers/crypto/ti/dthev2-aes.c @@ -512,7 +512,7 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) } =20 local_bh_disable(); - crypto_finalize_skcipher_request(dev_data->engine, req, ret); + crypto_finalize_skcipher_request(engine, req, ret); local_bh_enable(); return 0; } @@ -547,7 +547,7 @@ static int dthe_aes_crypt(struct skcipher_request *req) return 0; } =20 - engine =3D dev_data->engine; + engine =3D dev_data->aes_engine; return crypto_transfer_skcipher_request_to_engine(engine, req); } =20 @@ -1183,7 +1183,7 @@ static int dthe_aead_crypt(struct aead_request *req) (ctx->aes_mode =3D=3D DTHE_AES_CCM && !is_zero_ctr)) return dthe_aead_do_fallback(req); =20 - engine =3D dev_data->engine; + engine =3D dev_data->aes_engine; return crypto_transfer_aead_request_to_engine(engine, req); } =20 diff --git a/drivers/crypto/ti/dthev2-common.c b/drivers/crypto/ti/dthev2-c= ommon.c index a2ad79bec105a..88d0ccd5d0227 100644 --- a/drivers/crypto/ti/dthev2-common.c +++ b/drivers/crypto/ti/dthev2-common.c @@ -96,6 +96,11 @@ static int dthe_dma_init(struct dthe_data *dev_data) goto err_dma_sha_tx; } =20 + /* + * Do AES Rx and Tx channel config here because it is invariant of AES mo= de + * SHA Tx channel config is done before DMA transfer depending on hashing= algorithm + */ + memzero_explicit(&cfg, sizeof(cfg)); =20 cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; @@ -130,11 +135,21 @@ static int dthe_dma_init(struct dthe_data *dev_data) =20 static int dthe_register_algs(void) { - return dthe_register_aes_algs(); + int ret =3D 0; + + ret =3D dthe_register_hash_algs(); + if (ret) + return ret; + ret =3D dthe_register_aes_algs(); + if (ret) + dthe_unregister_hash_algs(); + + return ret; } =20 static void dthe_unregister_algs(void) { + dthe_unregister_hash_algs(); dthe_unregister_aes_algs(); } =20 @@ -163,15 +178,26 @@ static int dthe_probe(struct platform_device *pdev) if (ret) goto probe_dma_err; =20 - dev_data->engine =3D crypto_engine_alloc_init(dev, 1); - if (!dev_data->engine) { + dev_data->aes_engine =3D crypto_engine_alloc_init(dev, 1); + if (!dev_data->aes_engine) { ret =3D -ENOMEM; goto probe_engine_err; } + dev_data->hash_engine =3D crypto_engine_alloc_init(dev, 1); + if (!dev_data->hash_engine) { + ret =3D -ENOMEM; + goto probe_hash_engine_err; + } + + ret =3D crypto_engine_start(dev_data->aes_engine); + if (ret) { + dev_err(dev, "Failed to start crypto engine for AES\n"); + goto probe_engine_start_err; + } =20 - ret =3D crypto_engine_start(dev_data->engine); + ret =3D crypto_engine_start(dev_data->hash_engine); if (ret) { - dev_err(dev, "Failed to start crypto engine\n"); + dev_err(dev, "Failed to start crypto engine for hash\n"); goto probe_engine_start_err; } =20 @@ -184,7 +210,9 @@ static int dthe_probe(struct platform_device *pdev) return 0; =20 probe_engine_start_err: - crypto_engine_exit(dev_data->engine); + crypto_engine_exit(dev_data->hash_engine); +probe_hash_engine_err: + crypto_engine_exit(dev_data->aes_engine); probe_engine_err: dma_release_channel(dev_data->dma_aes_rx); dma_release_channel(dev_data->dma_aes_tx); @@ -207,7 +235,8 @@ static void dthe_remove(struct platform_device *pdev) =20 dthe_unregister_algs(); =20 - crypto_engine_exit(dev_data->engine); + crypto_engine_exit(dev_data->aes_engine); + crypto_engine_exit(dev_data->hash_engine); =20 dma_release_channel(dev_data->dma_aes_rx); dma_release_channel(dev_data->dma_aes_tx); diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index d4a3b9c18bbc1..bfe7f2de4415c 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include #include @@ -33,6 +34,16 @@ */ #define DTHE_MAX_KEYSIZE (AES_MAX_KEY_SIZE * 2) =20 +enum dthe_hash_alg_sel { + DTHE_HASH_MD5 =3D 0, + DTHE_HASH_SHA1 =3D BIT(1), + DTHE_HASH_SHA224 =3D BIT(2), + DTHE_HASH_SHA256 =3D BIT(1) | BIT(2), + DTHE_HASH_SHA384 =3D BIT(0), + DTHE_HASH_SHA512 =3D BIT(0) | BIT(1), + DTHE_HASH_ERR =3D BIT(0) | BIT(1) | BIT(2), +}; + enum dthe_aes_mode { DTHE_AES_ECB =3D 0, DTHE_AES_CBC, @@ -49,7 +60,8 @@ enum dthe_aes_mode { * @dev: Device pointer * @regs: Base address of the register space * @list: list node for dev - * @engine: Crypto engine instance + * @aes_engine: Crypto engine instance for AES Engine + * @hash_engine: Crypto engine instance for Hashing Engine * @dma_aes_rx: AES Rx DMA Channel * @dma_aes_tx: AES Tx DMA Channel * @dma_sha_tx: SHA Tx DMA Channel @@ -58,7 +70,8 @@ struct dthe_data { struct device *dev; void __iomem *regs; struct list_head list; - struct crypto_engine *engine; + struct crypto_engine *aes_engine; + struct crypto_engine *hash_engine; =20 struct dma_chan *dma_aes_rx; struct dma_chan *dma_aes_tx; @@ -83,6 +96,8 @@ struct dthe_list { * @authsize: Authentication size for modes with authentication * @key: AES key * @aes_mode: AES mode + * @hash_mode: Hashing Engine mode + * @phash_size: partial hash size of the hash algorithm selected * @aead_fb: Fallback crypto aead handle * @skcipher_fb: Fallback crypto skcipher handle for AES-XTS mode */ @@ -91,7 +106,11 @@ struct dthe_tfm_ctx { unsigned int keylen; unsigned int authsize; u32 key[DTHE_MAX_KEYSIZE / sizeof(u32)]; - enum dthe_aes_mode aes_mode; + union { + enum dthe_aes_mode aes_mode; + enum dthe_hash_alg_sel hash_mode; + }; + unsigned int phash_size; union { struct crypto_sync_aead *aead_fb; struct crypto_sync_skcipher *skcipher_fb; @@ -110,6 +129,25 @@ struct dthe_aes_req_ctx { struct completion aes_compl; }; =20 +/** + * struct dthe_hash_req_ctx - Hashing engine ctx struct + * @phash: buffer to store a partial hash from a previous operation + * @digestcnt: stores the digest count from a previous operation; currentl= y hardware only provides + * a single 32-bit value even for SHA384/512 + * @phash_available: flag indicating if a partial hash from a previous ope= ration is available + * @flags: flags for internal use + * @padding: padding buffer for handling unaligned data + * @hash_compl: Completion variable for use in manual completion in case o= f DMA callback failure + */ +struct dthe_hash_req_ctx { + u32 phash[SHA512_DIGEST_SIZE / sizeof(u32)]; + u64 digestcnt[2]; + u8 phash_available; + u8 flags; + u8 padding[SHA512_BLOCK_SIZE]; + struct completion hash_compl; +}; + /* Struct definitions end */ =20 struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx); @@ -131,4 +169,7 @@ struct scatterlist *dthe_copy_sg(struct scatterlist *ds= t, int dthe_register_aes_algs(void); void dthe_unregister_aes_algs(void); =20 +int dthe_register_hash_algs(void); +void dthe_unregister_hash_algs(void); + #endif diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c new file mode 100644 index 0000000000000..204637ab72374 --- /dev/null +++ b/drivers/crypto/ti/dthev2-hash.c @@ -0,0 +1,631 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * K3 DTHE V2 crypto accelerator driver + * + * Copyright (C) Texas Instruments 2025 - https://www.ti.com + * Author: T Pratham + */ + +#include +#include +#include +#include + +#include "dthev2-common.h" + +#include +#include +#include +#include +#include + +/* Registers */ + +#define DTHE_P_HASH_BASE 0x5000 +#define DTHE_P_HASH512_IDIGEST_A 0x0240 +#define DTHE_P_HASH512_DIGEST_COUNT 0x0280 +#define DTHE_P_HASH512_MODE 0x0284 +#define DTHE_P_HASH512_LENGTH 0x0288 +#define DTHE_P_HASH512_DATA_IN_START 0x0080 +#define DTHE_P_HASH512_DATA_IN_END 0x00FC + +#define DTHE_P_HASH_SYSCONFIG 0x0110 +#define DTHE_P_HASH_IRQSTATUS 0x0118 +#define DTHE_P_HASH_IRQENABLE 0x011C + +/* Register write values and macros */ +#define DTHE_HASH_SYSCONFIG_INT_EN BIT(2) +#define DTHE_HASH_SYSCONFIG_DMA_EN BIT(3) +#define DTHE_HASH_IRQENABLE_EN_ALL GENMASK(3, 0) +#define DTHE_HASH_IRQSTATUS_OP_READY BIT(0) +#define DTHE_HASH_IRQSTATUS_IP_READY BIT(1) +#define DTHE_HASH_IRQSTATUS_PH_READY BIT(2) +#define DTHE_HASH_IRQSTATUS_CTX_READY BIT(3) + +#define DTHE_HASH_MODE_USE_ALG_CONST BIT(3) +#define DTHE_HASH_MODE_CLOSE_HASH BIT(4) + +enum dthe_hash_op { + DTHE_HASH_OP_UPDATE =3D 0, + DTHE_HASH_OP_FINUP, +}; + +static void dthe_hash_write_zero_message(enum dthe_hash_alg_sel mode, void= *dst) +{ + switch (mode) { + case DTHE_HASH_SHA512: + memcpy(dst, sha512_zero_message_hash, SHA512_DIGEST_SIZE); + break; + case DTHE_HASH_SHA384: + memcpy(dst, sha384_zero_message_hash, SHA384_DIGEST_SIZE); + break; + case DTHE_HASH_SHA256: + memcpy(dst, sha256_zero_message_hash, SHA256_DIGEST_SIZE); + break; + case DTHE_HASH_SHA224: + memcpy(dst, sha224_zero_message_hash, SHA224_DIGEST_SIZE); + break; + default: + break; + } +} + +static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(struct crypto_ahash = *tfm) +{ + unsigned int ds =3D crypto_ahash_digestsize(tfm); + enum dthe_hash_alg_sel hash_mode; + + /* + * Currently, all hash algorithms supported by DTHEv2 have unique digest = sizes. + * So we can do this. Otherwise, we would have to get the algorithm from = the + * alg_name and do a strcmp. + */ + switch (ds) { + case SHA512_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA512; + break; + case SHA384_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA384; + break; + case SHA256_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA256; + break; + case SHA224_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA224; + break; + default: + hash_mode =3D DTHE_HASH_ERR; + break; + } + + return hash_mode; +} + +static unsigned int dthe_hash_get_phash_size(struct dthe_tfm_ctx *ctx) +{ + unsigned int phash_size =3D 0; + + switch (ctx->hash_mode) { + case DTHE_HASH_SHA512: + case DTHE_HASH_SHA384: + phash_size =3D SHA512_DIGEST_SIZE; + break; + case DTHE_HASH_SHA256: + case DTHE_HASH_SHA224: + phash_size =3D SHA256_DIGEST_SIZE; + break; + default: + break; + } + + return phash_size; +} + +static int dthe_hash_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + + if (!dev_data) + return -ENODEV; + + ctx->dev_data =3D dev_data; + + ctx->hash_mode =3D dthe_hash_get_hash_mode(tfm); + if (ctx->hash_mode =3D=3D DTHE_HASH_ERR) + return -EINVAL; + + ctx->phash_size =3D dthe_hash_get_phash_size(ctx); + + return 0; +} + +static int dthe_hash_config_dma_chan(struct dma_chan *chan, struct crypto_= ahash *tfm) +{ + struct dma_slave_config cfg; + int bs =3D crypto_ahash_blocksize(tfm); + + memzero_explicit(&cfg, sizeof(cfg)); + + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_maxburst =3D bs / 4; + + return dmaengine_slave_config(chan, &cfg); +} + +static void dthe_hash_dma_in_callback(void *data) +{ + struct ahash_request *req =3D (struct ahash_request *)data; + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + complete(&rctx->hash_compl); +} + +static int dthe_hash_dma_start(struct ahash_request *req, struct scatterli= st *src, + int src_nents, size_t len) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct device *tx_dev; + struct dma_async_tx_descriptor *desc_out; + int mapped_nents; + enum dma_data_direction src_dir =3D DMA_TO_DEVICE; + u32 hash_mode; + int ds =3D crypto_ahash_digestsize(tfm); + int ret =3D 0; + u32 *dst; + u32 dst_len; + void __iomem *sha_base_reg =3D dev_data->regs + DTHE_P_HASH_BASE; + + u32 hash_sysconfig_val =3D DTHE_HASH_SYSCONFIG_INT_EN | DTHE_HASH_SYSCONF= IG_DMA_EN; + u32 hash_irqenable_val =3D DTHE_HASH_IRQENABLE_EN_ALL; + + writel_relaxed(hash_sysconfig_val, sha_base_reg + DTHE_P_HASH_SYSCONFIG); + writel_relaxed(hash_irqenable_val, sha_base_reg + DTHE_P_HASH_IRQENABLE); + + /* Config SHA DMA channel as per SHA mode */ + ret =3D dthe_hash_config_dma_chan(dev_data->dma_sha_tx, tfm); + if (ret) { + dev_err(dev_data->dev, "Can't configure sha_tx dmaengine slave: %d\n", r= et); + goto hash_err; + } + + tx_dev =3D dmaengine_get_dma_device(dev_data->dma_sha_tx); + if (!tx_dev) { + ret =3D -ENODEV; + goto hash_err; + } + + mapped_nents =3D dma_map_sg(tx_dev, src, src_nents, src_dir); + if (mapped_nents =3D=3D 0) { + ret =3D -EINVAL; + goto hash_err; + } + + desc_out =3D dmaengine_prep_slave_sg(dev_data->dma_sha_tx, src, mapped_ne= nts, + DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc_out) { + dev_err(dev_data->dev, "OUT prep_slave_sg() failed\n"); + ret =3D -EINVAL; + goto hash_prep_err; + } + + desc_out->callback =3D dthe_hash_dma_in_callback; + desc_out->callback_param =3D req; + + init_completion(&rctx->hash_compl); + + hash_mode =3D ctx->hash_mode; + + if (rctx->flags =3D=3D DTHE_HASH_OP_FINUP) + hash_mode |=3D DTHE_HASH_MODE_CLOSE_HASH; + + if (rctx->phash_available) { + for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->phash[i], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + + writel_relaxed(rctx->digestcnt[0], + sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + } else { + hash_mode |=3D DTHE_HASH_MODE_USE_ALG_CONST; + } + + writel_relaxed(hash_mode, sha_base_reg + DTHE_P_HASH512_MODE); + writel_relaxed(len, sha_base_reg + DTHE_P_HASH512_LENGTH); + + dmaengine_submit(desc_out); + + dma_async_issue_pending(dev_data->dma_sha_tx); + + ret =3D wait_for_completion_timeout(&rctx->hash_compl, + msecs_to_jiffies(DTHE_DMA_TIMEOUT_MS)); + if (!ret) { + dmaengine_terminate_sync(dev_data->dma_sha_tx); + ret =3D -ETIMEDOUT; + } else { + ret =3D 0; + } + + if (rctx->flags =3D=3D DTHE_HASH_OP_UPDATE) { + /* If coming from update, we need to read the phash and store it for fut= ure */ + dst =3D rctx->phash; + dst_len =3D ctx->phash_size / sizeof(u32); + } else { + /* If coming from finup or final, we need to read the final digest */ + dst =3D (u32 *)req->result; + dst_len =3D ds / sizeof(u32); + } + + for (int i =3D 0; i < dst_len; ++i) + dst[i] =3D readl_relaxed(sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + + rctx->digestcnt[0] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_DIGEST= _COUNT); + rctx->phash_available =3D 1; + +hash_prep_err: + dma_unmap_sg(tx_dev, src, src_nents, src_dir); +hash_err: + return ret; +} + +static int dthe_hash_run(struct crypto_engine *engine, void *areq) +{ + struct ahash_request *req =3D container_of(areq, struct ahash_request, ba= se); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + struct scatterlist *src, *sg; + int src_nents =3D 0; + unsigned int bs =3D crypto_ahash_blocksize(tfm); + unsigned int tot_len =3D req->nbytes; + unsigned int len_to_process; + unsigned int len_to_buffer; + unsigned int pad_len =3D 0; + u8 *pad_buf =3D rctx->padding; + int ret =3D 0; + + if (rctx->flags =3D=3D DTHE_HASH_OP_UPDATE) { + len_to_process =3D tot_len - (tot_len % bs); + len_to_buffer =3D tot_len % bs; + + if (len_to_process =3D=3D 0) { + ret =3D len_to_buffer; + goto hash_buf_all; + } + } else { + len_to_process =3D tot_len; + len_to_buffer =3D 0; + } + + src_nents =3D sg_nents_for_len(req->src, len_to_process); + + /* + * Certain DMA restrictions forced us to send data in multiples of BLOCK_= SIZE + * bytes. So, add a padding 0s at the end of src scatterlist if data is n= ot a + * multiple of block_size bytes (Can only happen in final or finup). The = extra + * data is ignored by the DTHE hardware. + */ + if (len_to_process % bs) { + pad_len =3D bs - (len_to_process % bs); + src_nents++; + } + + src =3D kcalloc(src_nents, sizeof(*src), GFP_KERNEL); + if (!src) { + ret =3D -ENOMEM; + goto hash_buf_all; + } + + sg_init_table(src, src_nents); + sg =3D dthe_copy_sg(src, req->src, len_to_process); + if (pad_len > 0) { + memset(pad_buf, 0, pad_len); + sg_set_buf(sg, pad_buf, pad_len); + } + + ret =3D dthe_hash_dma_start(req, src, src_nents, len_to_process); + if (!ret) + ret =3D len_to_buffer; + + kfree(src); + +hash_buf_all: + local_bh_disable(); + crypto_finalize_hash_request(engine, req, ret); + local_bh_enable(); + return 0; +} + +static int dthe_hash_init(struct ahash_request *req) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + rctx->phash_available =3D 0; + rctx->digestcnt[0] =3D 0; + rctx->digestcnt[1] =3D 0; + + return 0; +} + +static int dthe_hash_update(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct crypto_engine *engine =3D dev_data->hash_engine; + + if (req->nbytes =3D=3D 0) + return 0; + + rctx->flags =3D DTHE_HASH_OP_UPDATE; + + return crypto_transfer_hash_request_to_engine(engine, req); +} + +static int dthe_hash_final(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct crypto_engine *engine =3D dev_data->hash_engine; + + /** + * We are always buffering data in update, except when nbytes =3D 0. + * So, either we get the buffered data here (nbytes > 0) or + * it is the case that we got zero message to begin with + */ + if (req->nbytes > 0) { + rctx->flags =3D DTHE_HASH_OP_FINUP; + + return crypto_transfer_hash_request_to_engine(engine, req); + } + + dthe_hash_write_zero_message(ctx->hash_mode, req->result); + + return 0; +} + +static int dthe_hash_finup(struct ahash_request *req) +{ + /* With AHASH_ALG_BLOCK_ONLY, final becomes same as finup. */ + return dthe_hash_final(req); +} + +static int dthe_hash_digest(struct ahash_request *req) +{ + dthe_hash_init(req); + return dthe_hash_finup(req); +} + +static const u32 sha224_init_state[SHA256_DIGEST_SIZE / sizeof(u32)] =3D { + SHA224_H0, SHA224_H1, SHA224_H2, SHA224_H3, + SHA224_H4, SHA224_H5, SHA224_H6, SHA224_H7 +}; + +static const u32 sha256_init_state[SHA256_DIGEST_SIZE / sizeof(u32)] =3D { + SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, + SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7 +}; + +static const u64 sha384_init_state[SHA512_DIGEST_SIZE / sizeof(u64)] =3D { + SHA384_H0, SHA384_H1, SHA384_H2, SHA384_H3, + SHA384_H4, SHA384_H5, SHA384_H6, SHA384_H7 +}; + +static const u64 sha512_init_state[SHA512_DIGEST_SIZE / sizeof(u64)] =3D { + SHA512_H0, SHA512_H1, SHA512_H2, SHA512_H3, + SHA512_H4, SHA512_H5, SHA512_H6, SHA512_H7 +}; + +static const void *dthe_hash_get_init_state(struct dthe_tfm_ctx *ctx) +{ + switch (ctx->hash_mode) { + case DTHE_HASH_SHA224: + return sha224_init_state; + case DTHE_HASH_SHA256: + return sha256_init_state; + case DTHE_HASH_SHA384: + return sha384_init_state; + case DTHE_HASH_SHA512: + return sha512_init_state; + default: + return NULL; + } +} + +static int dthe_hash_export(struct ahash_request *req, void *out) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + union { + u8 *u8; + u64 *u64; + } p =3D { .u8 =3D out }; + + if (rctx->phash_available) + memcpy(out, rctx->phash, ctx->phash_size); + else + memcpy(out, dthe_hash_get_init_state(ctx), ctx->phash_size); + + p.u8 +=3D ctx->phash_size; + put_unaligned(rctx->digestcnt[0], p.u64++); + if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) + put_unaligned(rctx->digestcnt[1], p.u64++); + + return 0; +} + +static int dthe_hash_import(struct ahash_request *req, const void *in) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + union { + const u8 *u8; + const u64 *u64; + } p =3D { .u8 =3D in }; + + memcpy(rctx->phash, in, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + rctx->digestcnt[0] =3D get_unaligned(p.u64++); + if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) + rctx->digestcnt[1] =3D get_unaligned(p.u64++); + rctx->phash_available =3D ((rctx->digestcnt[0]) ? 1 : 0); + + return 0; +} + +static struct ahash_engine_alg hash_algs[] =3D { + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA512_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha512", + .cra_driver_name =3D "sha512-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA384_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha384", + .cra_driver_name =3D "sha384-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha256", + .cra_driver_name =3D "sha256-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha224", + .cra_driver_name =3D "sha224-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, +}; 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Miller" CC: Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v4 2/3] crypto: ti - Add support for MD5 in DTHEv2 Hashing Engine driver Date: Tue, 26 May 2026 15:13:52 +0530 Message-ID: <20260526094355.555712-3-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260526094355.555712-1-t-pratham@ti.com> References: <20260526094355.555712-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B075:EE_|SJ5PPF1D755039F:EE_ X-MS-Office365-Filtering-Correlation-Id: f2a58003-f0f3-4694-4ff4-08debb0b7a04 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: VqKeE85WSeGrnOsBP7wGjGQKenJjiaZZ3EWgEy2IErr3LwrglVM08rFp+9e+ZEBZKnSubinoW/xnFZMsdf1OX0G7aIbjsvFyZ4LvTh/D3WM5lNlcGEWZXCvqXaItjhbPKVWhbsYscGPo+VWNVPeXJs5wXvrOqF9dow66SZEwN6Mgg8RQ6ev1grSiyqOYpG9YTfMAuHwywCUhd19P05yNwh9vAvtxKRJ0stkysbYApxtNd8mTCMoNE5GPWlgR5Hlir7fds46a0IiKBhss5BZwpiXQkNenD7PmhPte1gv5cflA5ziRkS1uVXN81e3r9KTL7J2Ajx60wh3Ebz8hQjDTgea7RVfhM0I3uKckqn8n+9A0vpYtpFSMtCDzqxKXO7c8ZKnqEbqmZLX4L7+IVM0Ht+vxJOQw60vm+GeYkz1Mlcx6F/FlV9THNJG42kvvDJBz/EQmxaBF5T1cfKMvVS/f/CCh35tLgmZ4QXz0AmSJ+tLHW5MQW/z1y7tmXT9vB4otlg9Pt5xFarXlMMTDTQ4TM85G/HmsH3MYA/7SbPGflMTd/gBhqSRPkT9loiH7bhIf0I2glcPmrUC89X/1b8vELtCYrWpRFoKJ0yQk92qfcw0m1bYI0vLKcbtS2nPC9TpS/7oYfn0/E22LVhwSm/5ZOIEBvm64YZxdyEag4gmvHirr7u8j+qxkyyMRskez3k7gOSwqbm7Tb5nUvcRbjxCpMPJD25stqq/aFomfe5p3lr4= X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QJoSVpee6XKA4dapSZQ0OXIGsSFM4l9YZg5DyJBULuB7DCVAWi6ehl95VJiJWz1uFPCWEv9mgpdSFT4Yv/O752+JLSOSUX2nLEUHiUOm3zsxYYEZIcsCu3NDJrhP4NuNC1Wol/WwhF+dn6ynx9pxw3bFy5OcCKbEE4+Yl6Y7v5aJ1ayhwdeian7FvwzJxWprbt2ZLBgAQZwA6eGCuIfY8KMKDi6DFYqukDfwBo8ag4iecIU44BstSTRsxYMFUDPt4S+RcBuXKCGv9Ir1pO8OZ9+0AEgVTQc5cKoTQ5wRbT2abyaQlY+9Z2aez5cbQ/iRiSbbpfACrrCnDgo7gy2J8ZHlsEJqosXrtPoDnCamqa5qWKNHAID+q0S9DzQgXMc/CSq2KhYgOBnsgrOE7I3arwLE9MXEDMrMa3pnKwZuS8ffQGGSHD9pCEVaCzGMvfT9 X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2026 09:45:09.7926 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2a58003-f0f3-4694-4ff4-08debb0b7a04 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF1D755039F Content-Type: text/plain; charset="utf-8" Add support for MD5 algorithm in the hashing engine of DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-common.h | 1 + drivers/crypto/ti/dthev2-hash.c | 49 +++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 90af2c7cb1c55..9c2aa50cfbfbe 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -12,6 +12,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_CCM select CRYPTO_SHA256 select CRYPTO_SHA512 + select CRYPTO_MD5 select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index bfe7f2de4415c..24799007ea81f 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #include diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c index 204637ab72374..4b5df4fdcaa5f 100644 --- a/drivers/crypto/ti/dthev2-hash.c +++ b/drivers/crypto/ti/dthev2-hash.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "dthev2-common.h" @@ -65,6 +66,9 @@ static void dthe_hash_write_zero_message(enum dthe_hash_a= lg_sel mode, void *dst) case DTHE_HASH_SHA224: memcpy(dst, sha224_zero_message_hash, SHA224_DIGEST_SIZE); break; + case DTHE_HASH_MD5: + memcpy(dst, md5_zero_message_hash, MD5_DIGEST_SIZE); + break; default: break; } @@ -93,6 +97,9 @@ static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(str= uct crypto_ahash *tfm) case SHA224_DIGEST_SIZE: hash_mode =3D DTHE_HASH_SHA224; break; + case MD5_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_MD5; + break; default: hash_mode =3D DTHE_HASH_ERR; break; @@ -114,6 +121,9 @@ static unsigned int dthe_hash_get_phash_size(struct dth= e_tfm_ctx *ctx) case DTHE_HASH_SHA224: phash_size =3D SHA256_DIGEST_SIZE; break; + case DTHE_HASH_MD5: + phash_size =3D MD5_DIGEST_SIZE; + break; default: break; } @@ -426,6 +436,10 @@ static const u64 sha512_init_state[SHA512_DIGEST_SIZE = / sizeof(u64)] =3D { SHA512_H4, SHA512_H5, SHA512_H6, SHA512_H7 }; =20 +static const u32 md5_init_state[MD5_DIGEST_SIZE / sizeof(u32)] =3D { + MD5_H0, MD5_H1, MD5_H2, MD5_H3 +}; + static const void *dthe_hash_get_init_state(struct dthe_tfm_ctx *ctx) { switch (ctx->hash_mode) { @@ -437,6 +451,8 @@ static const void *dthe_hash_get_init_state(struct dthe= _tfm_ctx *ctx) return sha384_init_state; case DTHE_HASH_SHA512: return sha512_init_state; + case DTHE_HASH_MD5: + return md5_init_state; default: return NULL; } @@ -618,6 +634,39 @@ static struct ahash_engine_alg hash_algs[] =3D { }, .op.do_one_request =3D dthe_hash_run, }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D MD5_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "md5", + .cra_driver_name =3D "md5-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D MD5_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, }; 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Tue, 26 May 2026 04:45:10 -0500 Received: from pratham-Workstation-PC (pratham-workstation-pc.dhcp.ti.com [10.24.69.191]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 64Q9j9G3631424; Tue, 26 May 2026 04:45:09 -0500 From: T Pratham To: T Pratham , Herbert Xu , "David S. Miller" CC: Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v4 3/3] crypto: ti - Add support for HMAC in DTHEv2 Hashing Engine driver Date: Tue, 26 May 2026 15:13:53 +0530 Message-ID: <20260526094355.555712-4-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260526094355.555712-1-t-pratham@ti.com> References: <20260526094355.555712-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE31:EE_|CO1PR10MB4740:EE_ X-MS-Office365-Filtering-Correlation-Id: ab3f4a4a-5302-4b2d-d19d-08debb0b7b21 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: 37V4BAbmtb9Z1ipMoLe4JYNUc2B2RLQwspPKcbwq2XyYcvyUlkcSkBTaRDIGcpo9d2axo/9TVhzTAkHILXs/zX0kUl6OEfiNpt981NBoH9EqsNPUGhGUmk38mjQ6/55LLZfKFaFWd6FA1qQHn1/ZHugZ73QpOWa//KKak0JsdPmzHyhLEI60Gt/XXuzZnVXAJegyD48PH262yvsf9nfXSxpWTaTXuCbASehOCsij0LsPi8BTQ7pCWHIR0dGke8b3eSdK+TI8wwAJNFdNMRKCm5aVzloiGm9tfeheYDkU5wNBsYDzy1MOt+OLvOU1XInKvGPoFP/Tyo2pb0mzTZtVyEgO2FgyuFiWW03+pumQjD2nYWdSa56mNXVGjU6lwqNVAQ355VVDWTyGY9s4/FyaI2mYHPbnpSY920xD4bjGZWCljJhKgI03QdaNgWXm0Fxs5o/L/kbC4l0zUyfT/pZvynDA1ZnmIsP0ym07GtY17NENyU8XlSVLP2WOKpnILUxLg/kl3pAbVSs4qJUmAF7EP2faxyTggh8lZrB1a04Mg6qnbYJbG4C67CiOZUeuwiEscld3fPH+kGQpBSQy7tbVg8nxWxajphRDkLQvT0ihMCvhy3Ljf4VnGDZQiG4rkC2CrqMSOJpAA08RAzrvacqv7bvnYvIpAoKF/HoHMnZw7krZ4JZ6BG9Kjv2biSKYh72uHhMyTEEPUQpG2LrtOaJxhMnURiqQAlsQS/9rKEH0qjs= X-Forefront-Antispam-Report: CIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MdNveIukmVs4Cc4OW9FVPEa+h8yaB5KDBtm+28DLDQr4+fd/fn2HYijFj61CQQq1vdwzGn/7hX2EVg6r36etlUyPm9/Egx2cIvyx7564oTSGmieJ5PTIsVRabXej93wfVXUI5PSCWCiTtDZv+XjPdhciUyNW0BvYpgiEBJ9BIE8+DzwVDqJXVIk/6n6yisWb45ASUyVsVNmj2hKp9Wwqfbpu55LogPvq1+5HUtZSTPkuynQKNIi3gQtk1W7SRMGT+Ld41SNmbCYMl2XKK8P/yWNEW3aDt+MkQ+RybSf5KPg9xbbJ9+a1VwBhQdLn0cYHuCSOKeR099RkeJcwcWJR2jhFFirtamA3R8yucoF4Uc+CEgky/1IFLp0oCtO3KgFmolfihYr3xprpcIvTBsa6pZ8rS/0FsL1Hdli4SbW/DjyPNmw0djhu/+HUZcCBhmW/ X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2026 09:45:11.7205 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab3f4a4a-5302-4b2d-d19d-08debb0b7b21 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR10MB4740 Content-Type: text/plain; charset="utf-8" Add support for HMAC-SHA512/384/256/224 and HMAC-MD5 algorithms in the hashing engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-common.h | 10 +- drivers/crypto/ti/dthev2-hash.c | 346 +++++++++++++++++++++++++++++- 3 files changed, 351 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 9c2aa50cfbfbe..68dccf92f5382 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -13,6 +13,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_SHA256 select CRYPTO_SHA512 select CRYPTO_MD5 + select CRYPTO_HMAC select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index 24799007ea81f..847804ed74736 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -31,9 +31,9 @@ #define DTHE_DMA_TIMEOUT_MS 2000 /* * Size of largest possible key (of all algorithms) to be stored in dthe_t= fm_ctx - * This is currently the keysize of XTS-AES-256 which is 512 bits (64 byte= s) + * This is currently the keysize of HMAC-SHA512 which is 1024 bits (128 by= tes) */ -#define DTHE_MAX_KEYSIZE (AES_MAX_KEY_SIZE * 2) +#define DTHE_MAX_KEYSIZE (SHA512_BLOCK_SIZE) =20 enum dthe_hash_alg_sel { DTHE_HASH_MD5 =3D 0, @@ -93,9 +93,9 @@ struct dthe_list { /** * struct dthe_tfm_ctx - Transform ctx struct containing ctx for all sub-c= omponents of DTHE V2 * @dev_data: Device data struct pointer - * @keylen: AES key length + * @keylen: Key length for algorithms that use a key * @authsize: Authentication size for modes with authentication - * @key: AES key + * @key: Buffer storing the key * @aes_mode: AES mode * @hash_mode: Hashing Engine mode * @phash_size: partial hash size of the hash algorithm selected @@ -135,6 +135,7 @@ struct dthe_aes_req_ctx { * @phash: buffer to store a partial hash from a previous operation * @digestcnt: stores the digest count from a previous operation; currentl= y hardware only provides * a single 32-bit value even for SHA384/512 + * @odigest: buffer to store the outer digest from a previous operation * @phash_available: flag indicating if a partial hash from a previous ope= ration is available * @flags: flags for internal use * @padding: padding buffer for handling unaligned data @@ -143,6 +144,7 @@ struct dthe_aes_req_ctx { struct dthe_hash_req_ctx { u32 phash[SHA512_DIGEST_SIZE / sizeof(u32)]; u64 digestcnt[2]; + u32 odigest[SHA512_DIGEST_SIZE / sizeof(u32)]; u8 phash_available; u8 flags; u8 padding[SHA512_BLOCK_SIZE]; diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c index 4b5df4fdcaa5f..62a42e63c4772 100644 --- a/drivers/crypto/ti/dthev2-hash.c +++ b/drivers/crypto/ti/dthev2-hash.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -23,6 +24,7 @@ /* Registers */ =20 #define DTHE_P_HASH_BASE 0x5000 +#define DTHE_P_HASH512_ODIGEST_A 0x0200 #define DTHE_P_HASH512_IDIGEST_A 0x0240 #define DTHE_P_HASH512_DIGEST_COUNT 0x0280 #define DTHE_P_HASH512_MODE 0x0284 @@ -45,6 +47,13 @@ =20 #define DTHE_HASH_MODE_USE_ALG_CONST BIT(3) #define DTHE_HASH_MODE_CLOSE_HASH BIT(4) +#define DTHE_HASH_MODE_HMAC_KEY_PROCESSING BIT(5) +#define DTHE_HASH_MODE_HMAC_OUTER_HASH BIT(7) + +/* Misc */ +#define DTHE_HMAC_SHA512_MAX_KEYSIZE (SHA512_BLOCK_SIZE) +#define DTHE_HMAC_SHA256_MAX_KEYSIZE (SHA256_BLOCK_SIZE) +#define DTHE_HMAC_MD5_MAX_KEYSIZE (MD5_BLOCK_SIZE) =20 enum dthe_hash_op { DTHE_HASH_OP_UPDATE =3D 0, @@ -74,6 +83,19 @@ static void dthe_hash_write_zero_message(enum dthe_hash_= alg_sel mode, void *dst) } } =20 +static int dthe_hmac_write_zero_message(struct ahash_request *req) +{ + HASH_FBREQ_ON_STACK(fbreq, req); + int ret; + + ahash_request_set_crypt(fbreq, req->src, req->result, + req->nbytes); + + ret =3D crypto_ahash_digest(fbreq); + HASH_REQUEST_ZERO(fbreq); + return ret; +} + static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(struct crypto_ahash = *tfm) { unsigned int ds =3D crypto_ahash_digestsize(tfm); @@ -131,6 +153,18 @@ static unsigned int dthe_hash_get_phash_size(struct dt= he_tfm_ctx *ctx) return phash_size; } =20 +static const char *dthe_hash_get_alg_name(struct dthe_tfm_ctx *ctx) +{ + switch (ctx->hash_mode) { + case DTHE_HASH_SHA224: return "sha224"; + case DTHE_HASH_SHA256: return "sha256"; + case DTHE_HASH_SHA384: return "sha384"; + case DTHE_HASH_SHA512: return "sha512"; + case DTHE_HASH_MD5: return "md5"; + default: return NULL; + } +} + static int dthe_hash_init_tfm(struct crypto_ahash *tfm) { struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); @@ -184,6 +218,7 @@ static int dthe_hash_dma_start(struct ahash_request *re= q, struct scatterlist *sr enum dma_data_direction src_dir =3D DMA_TO_DEVICE; u32 hash_mode; int ds =3D crypto_ahash_digestsize(tfm); + bool is_hmac =3D (ctx->keylen > 0); int ret =3D 0; u32 *dst; u32 dst_len; @@ -229,8 +264,11 @@ static int dthe_hash_dma_start(struct ahash_request *r= eq, struct scatterlist *sr =20 hash_mode =3D ctx->hash_mode; =20 - if (rctx->flags =3D=3D DTHE_HASH_OP_FINUP) + if (rctx->flags =3D=3D DTHE_HASH_OP_FINUP) { hash_mode |=3D DTHE_HASH_MODE_CLOSE_HASH; + if (is_hmac) + hash_mode |=3D DTHE_HASH_MODE_HMAC_OUTER_HASH; + } =20 if (rctx->phash_available) { for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) @@ -238,9 +276,28 @@ static int dthe_hash_dma_start(struct ahash_request *r= eq, struct scatterlist *sr sha_base_reg + DTHE_P_HASH512_IDIGEST_A + (DTHE_REG_SIZE * i)); + if (is_hmac) { + for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->odigest[i], + sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } =20 writel_relaxed(rctx->digestcnt[0], sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + } else if (is_hmac) { + hash_mode |=3D DTHE_HASH_MODE_HMAC_KEY_PROCESSING; + + for (int i =3D 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i], sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + for (int i =3D 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i + (ctx->keylen / 2) / sizeof(u32)], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); } else { hash_mode |=3D DTHE_HASH_MODE_USE_ALG_CONST; } @@ -275,6 +332,12 @@ static int dthe_hash_dma_start(struct ahash_request *r= eq, struct scatterlist *sr dst[i] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_IDIGEST_A + (DTHE_REG_SIZE * i)); + if (is_hmac) { + for (int i =3D 0; i < dst_len; ++i) + rctx->odigest[i] =3D readl_relaxed(sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } =20 rctx->digestcnt[0] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_DIGEST= _COUNT); rctx->phash_available =3D 1; @@ -399,6 +462,10 @@ static int dthe_hash_final(struct ahash_request *req) return crypto_transfer_hash_request_to_engine(engine, req); } =20 + if (ctx->keylen > 0) + /* HMAC with zero-length message */ + return dthe_hmac_write_zero_message(req); + dthe_hash_write_zero_message(ctx->hash_mode, req->result); =20 return 0; @@ -458,6 +525,53 @@ static const void *dthe_hash_get_init_state(struct dth= e_tfm_ctx *ctx) } } =20 +/* + * Compute the HMAC inner or outer pad state (the intermediate hash state = after + * processing one block of key XOR pad_byte) and write it to @out. Only the + * first ctx->phash_size bytes are written, which is always the raw hash s= tate + * at the start of the shash export struct. + */ +static int dthe_hmac_compute_pad_state(struct dthe_tfm_ctx *ctx, u8 pad_by= te, + void *out) +{ + const char *alg_name =3D dthe_hash_get_alg_name(ctx); + struct crypto_shash *ktfm; + u8 data[SHA512_BLOCK_SIZE]; + unsigned int ss; + u8 *state; + int ret; + + ktfm =3D crypto_alloc_shash(alg_name, 0, 0); + if (IS_ERR(ktfm)) + return PTR_ERR(ktfm); + + ss =3D crypto_shash_statesize(ktfm); + state =3D kmalloc(ss, GFP_KERNEL); + if (!state) { + crypto_free_shash(ktfm); + return -ENOMEM; + } + + SHASH_DESC_ON_STACK(desc, ktfm); + + desc->tfm =3D ktfm; + for (int i =3D 0; i < ctx->keylen; i++) + data[i] =3D ((u8 *)ctx->key)[i] ^ pad_byte; + + ret =3D crypto_shash_init(desc) ?: + crypto_shash_update(desc, data, ctx->keylen) ?: + crypto_shash_export(desc, state); + + if (!ret) + memcpy(out, state, ctx->phash_size); + + memzero_explicit(state, ss); + kfree(state); + crypto_free_shash(ktfm); + memzero_explicit(data, sizeof(data)); + return ret; +} + static int dthe_hash_export(struct ahash_request *req, void *out) { struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); @@ -467,9 +581,12 @@ static int dthe_hash_export(struct ahash_request *req,= void *out) u8 *u8; u64 *u64; } p =3D { .u8 =3D out }; + int ret =3D 0; =20 if (rctx->phash_available) memcpy(out, rctx->phash, ctx->phash_size); + else if (ctx->keylen > 0) + ret =3D dthe_hmac_compute_pad_state(ctx, HMAC_IPAD_VALUE, out); else memcpy(out, dthe_hash_get_init_state(ctx), ctx->phash_size); =20 @@ -478,7 +595,12 @@ static int dthe_hash_export(struct ahash_request *req,= void *out) if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) put_unaligned(rctx->digestcnt[1], p.u64++); =20 - return 0; + if (ctx->keylen > 0) { + memcpy(p.u8, rctx->odigest, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + } + + return ret; } =20 static int dthe_hash_import(struct ahash_request *req, const void *in) @@ -498,9 +620,59 @@ static int dthe_hash_import(struct ahash_request *req,= const void *in) rctx->digestcnt[1] =3D get_unaligned(p.u64++); rctx->phash_available =3D ((rctx->digestcnt[0]) ? 1 : 0); =20 + if (ctx->keylen > 0) { + memcpy(rctx->odigest, p.u8, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + } + return 0; } =20 +static int dthe_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct crypto_ahash *fb =3D crypto_ahash_fb(tfm); + const char *hash_alg_name =3D dthe_hash_get_alg_name(ctx); + unsigned int max_keysize; + + memzero_explicit(ctx->key, sizeof(ctx->key)); + + switch (ctx->hash_mode) { + case DTHE_HASH_SHA512: + case DTHE_HASH_SHA384: + max_keysize =3D DTHE_HMAC_SHA512_MAX_KEYSIZE; + break; + case DTHE_HASH_SHA256: + case DTHE_HASH_SHA224: + max_keysize =3D DTHE_HMAC_SHA256_MAX_KEYSIZE; + break; + case DTHE_HASH_MD5: + max_keysize =3D DTHE_HMAC_MD5_MAX_KEYSIZE; + break; + default: + return -EINVAL; + } + + if (keylen > max_keysize) { + struct crypto_shash *ktfm =3D crypto_alloc_shash(hash_alg_name, 0, 0); + SHASH_DESC_ON_STACK(desc, ktfm); + int err; + + desc->tfm =3D ktfm; + err =3D crypto_shash_digest(desc, key, keylen, (u8 *)ctx->key); + crypto_free_shash(ktfm); + if (err) + return err; + } else { + memcpy(ctx->key, key, keylen); + } + + ctx->keylen =3D max_keysize; + + return crypto_ahash_setkey(fb, key, keylen); +} + static struct ahash_engine_alg hash_algs[] =3D { { .base.init_tfm =3D dthe_hash_init_tfm, @@ -667,6 +839,176 @@ static struct ahash_engine_alg hash_algs[] =3D { }, .op.do_one_request =3D dthe_hash_run, }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA512_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha512)", + .cra_driver_name =3D "hmac-sha512-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA384_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha384)", + .cra_driver_name =3D "hmac-sha384-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha256)", + .cra_driver_name =3D "hmac-sha256-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha224)", + .cra_driver_name =3D "hmac-sha224-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D MD5_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(md5)", + .cra_driver_name =3D "hmac-md5-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D MD5_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, }; =20 int dthe_register_hash_algs(void) --=20 2.34.1