From nobody Mon Jun 8 22:55:25 2026 Received: from dggsgout12.his.huawei.com (dggsgout12.his.huawei.com [45.249.212.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A98892BE7DC; Tue, 26 May 2026 01:57:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779760658; cv=none; b=VIWFYl+9ByLGrSefzf1im8OTN2bLvNe8HRAfUQ7qOoGMJBo6L1aIXTrCo5BtG/FHkeI9Yztwyl+RnkhxqQZleXftMv91reV/uvYy1VnE7dAJPQUMIA9phaB8F8dZp0d81V0XD9fOrod1U4UxslXaNWgB1xONyDd2XiZHazsT00M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779760658; c=relaxed/simple; bh=uPQquMxSL+C/uYnX7SEJgLYiEzvz7kSuIPsa2gcnG4A=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=R7jsfOr8viahGI++DYml8DoRNtLtxHcQdyzvQdnE6hpF/PxuIMnfSS2Mlb+GRqEc/Vld2l67ek+CYodTElnyUbXGop4z+ukrW449VTZzTn5Gq3nDvxE3KsG9wvUCihRPsSTzkZZ/bFegUNA7Uc7CfKWF4TPUikCuVbRwOvBRH80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com; spf=pass smtp.mailfrom=huaweicloud.com; arc=none smtp.client-ip=45.249.212.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=huaweicloud.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huaweicloud.com Received: from mail.maildlp.com (unknown [172.19.163.170]) by dggsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4gPbV90JkxzKHMRq; Tue, 26 May 2026 09:57:21 +0800 (CST) Received: from mail02.huawei.com (unknown [10.116.40.128]) by mail.maildlp.com (Postfix) with ESMTP id 5DB364056B; Tue, 26 May 2026 09:57:33 +0800 (CST) Received: from huaweicloud.com (unknown [10.50.87.109]) by APP4 (Coremail) with SMTP id gCh0CgCXX1sD_hRqw9GdDg--.18849S4; Tue, 26 May 2026 09:57:33 +0800 (CST) From: Zeng Heng To: corbet@lwn.net, kuninori.morimoto.gx@renesas.com, maz@kernel.org, oupton@kernel.org, catalin.marinas@arm.com, lucaswei@google.com, yeoreum.yun@arm.com, skhan@linuxfoundation.org, james.clark@linaro.org, broonie@kernel.org, mark.rutland@arm.com, lpieralisi@kernel.org, ryan.roberts@arm.com, will@kernel.org, tongtiangen@huawei.com, kevin.brodsky@arm.com, yangyicong@hisilicon.com, miko.lenczewski@arm.com Cc: linux-doc@vger.kernel.org, wangkefeng.wang@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: kernel: Disable CNP on HiSilicon HIP09 Date: Tue, 26 May 2026 09:57:20 +0800 Message-ID: <20260526015720.206854-1-zengheng@huaweicloud.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: gCh0CgCXX1sD_hRqw9GdDg--.18849S4 X-Coremail-Antispam: 1UD129KBjvJXoWxJw47Jr13CF1UGr1UAr1xuFg_yoWrZr1fpw 4fAr1xJF1DWF13J34UJw17Xr45Can3Gwn8XF1Ut340qr13Z34UZF18Xw1xJFWjqrykWw48 uF1q9FyUtF17ArUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUv2b4IE77IF4wAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6r1S6rWUM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x 0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG 6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFV Cjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4IIrI8v6xkF7I0E8cxan2IY04v7MxkF7I0E n4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I 0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8 ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAF wI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa 7IU0s2-5UUUUU== X-CM-SenderInfo: p2hqwxhhqjqx5xdzvxpfor3voofrz/ Content-Type: text/plain; charset="utf-8" From: Tong Tiangen HiSilicon HIP09 implements TLB entry matching behavior that deviates from the ARM architecture specification when the CNP (Common not Private) bit is set in TTBRx_ELx. When TTBRx.CNP=3D1, TLB entries may be incorrectly shared between CPU cores, leading to TLB conflicts and stale mappings. This affects coherency and can result in incorrect translations. Add the hardware erratum workaround (Hisilicon erratum 162100125) to disable CNP on affected HIP09 cores. Signed-off-by: Tong Tiangen Signed-off-by: Zeng Heng --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 15 +++++++++++++++ arch/arm64/kernel/cpu_errata.c | 7 +++++++ arch/arm64/kernel/cpufeature.c | 3 ++- arch/arm64/tools/cpucaps | 1 + 5 files changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 211119ce7adc..cd50059edb85 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -284,6 +284,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | Hisilicon | Hip09 | #162100801 | HISILICON_ERRATUM_1= 62100801 | +----------------+-----------------+-----------------+--------------------= ---------+ +| Hisilicon | Hip09 | #162100125 | HISILICON_ERRATUM_1= 62100125 | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM= _1003 | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fe60738e5943..ed6207c75b54 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1273,6 +1273,21 @@ config HISILICON_ERRATUM_162100801 =20 If unsure, say Y. =20 +config HISILICON_ERRATUM_162100125 + bool "Hisilicon erratum 162100125" + default y + help + On HiSilicon HIP09, TLB entry matching behavior when CNP + (TTBRx.CNP=3D1) is enabled differs from the ARM architecture + specification. + + TLB entries may be incorrectly shared between CPUs, potentially + causing TLB conflicts and stale mappings. + + Disable CNP support for affected HiSilicon HIP09 cores. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 5377e4c2eba2..26d9677a20fc 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -968,6 +968,13 @@ const struct arm64_cpu_capabilities arm64_errata[] =3D= { .matches =3D has_impdef_pmuv3, .cpu_enable =3D cpu_enable_impdef_pmuv3_traps, }, +#ifdef CONFIG_HISILICON_ERRATUM_162100125 + { + .desc =3D "Hisilicon erratum 162100125", + .capability =3D ARM64_WORKAROUND_HISILICON_ERRATUM_162100125, + ERRATA_MIDR_ALL_VERSIONS(MIDR_HISI_HIP09), + }, +#endif { } }; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6d53bb15cf7b..c4b0db77a58a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1785,7 +1785,8 @@ has_useable_cnp(const struct arm64_cpu_capabilities *= entry, int scope) if (is_kdump_kernel()) return false; =20 - if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) + if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP) || + cpus_have_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100125)) return false; =20 return has_cpuid_feature(entry, scope); diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 811c2479e82d..b797d4893adc 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -128,3 +128,4 @@ WORKAROUND_REPEAT_TLBI WORKAROUND_SPECULATIVE_AT WORKAROUND_SPECULATIVE_SSBS WORKAROUND_SPECULATIVE_UNPRIV_LOAD +WORKAROUND_HISILICON_ERRATUM_162100125 --=20 2.43.0