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Tue, 26 May 2026 22:53:00 -0700 (PDT) From: Yong-Xuan Wang Date: Tue, 26 May 2026 22:52:38 -0700 Subject: [PATCH v2 1/3] KVM: RISC-V: SBI FWFT: Fix stale feature exposure after runtime extension changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260526-kvm-get_reg_list-v2-v2-1-7940a401454a@sifive.com> References: <20260526-kvm-get_reg_list-v2-v2-0-7940a401454a@sifive.com> In-Reply-To: <20260526-kvm-get_reg_list-v2-v2-0-7940a401454a@sifive.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, zong.li@sifive.com, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Yong-Xuan Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779861178; l=4044; i=yongxuan.wang@sifive.com; s=20260424; h=from:subject:message-id; bh=8rCDNvc2TJDmq0o9jKD+SWttG8Vm4gJbAUgSdeBhahw=; b=AfhaUDr6EDvzRR8AckzFU4mLJnayFuZt//mAddpv5TFe16Wy03F28lBbX2zJK5NPIj/ZCUBLU sDKiVJUb++NDY3CurknxqrlxIaH+V8PPFsplhKxsEtPX1j0d3+NfVcx X-Developer-Key: i=yongxuan.wang@sifive.com; a=ed25519; pk=+8NCHB1ZJvZthQAmZspOAaqjo+/snaW8mFSiDx45HxY= Fix a bug where FWFT features could be incorrectly exposed to guests after userspace disables their dependent ISA extensions at runtime. The 'supported' field in kvm_sbi_fwft_config was set once during vCPU initialization based on the initial hardware/extension availability. However, when userspace subsequently disables ISA extensions via the KVM ONE_REG interface, the 'supported' field was not updated. This caused the following issues: 1. FWFT features would remain visible and accessible to guests even after their prerequisite ISA extensions were disabled 2. Guests could configure FWFT features that depend on disabled extensions, leading to undefined behavior 3. The static 'supported' flag and the dynamic supported() callback could disagree about feature availability Remove the redundant static 'supported' field from kvm_sbi_fwft_config and replace all conf->supported checks with feature->supported(vcpu) calls that check the current vCPU ISA extension state. This can ensure the feature availability is always determined at runtime based on the current configuration, not initialization-time snapshots. Fixes: 6b72fd170592 ("RISC-V: KVM: add support for FWFT SBI extension") Signed-off-by: Yong-Xuan Wang --- arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 1 - arch/riscv/kvm/vcpu_sbi_fwft.c | 17 ++++++++--------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/includ= e/asm/kvm_vcpu_sbi_fwft.h index 5604cec79902..837431867c6f 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h @@ -15,7 +15,6 @@ struct kvm_sbi_fwft_feature; =20 struct kvm_sbi_fwft_config { const struct kvm_sbi_fwft_feature *feature; - bool supported; bool enabled; unsigned long flags; }; diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 2eab15339694..d3be059c3822 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -279,8 +279,8 @@ static int kvm_fwft_get_feature(struct kvm_vcpu *vcpu, = u32 feature, return SBI_ERR_DENIED; } =20 - if (!tconf->supported || !tconf->enabled) - return SBI_ERR_NOT_SUPPORTED; + if (!tconf->feature->supported(vcpu)) + return SBI_ERR_NOT_SUPPORTED; =20 *conf =3D tconf; =20 @@ -361,11 +361,10 @@ static int kvm_sbi_ext_fwft_init(struct kvm_vcpu *vcp= u) feature =3D &features[i]; conf =3D &fwft->configs[i]; if (feature->supported) - conf->supported =3D feature->supported(vcpu); + conf->enabled =3D feature->supported(vcpu); else - conf->supported =3D true; + conf->enabled =3D true; =20 - conf->enabled =3D conf->supported; conf->feature =3D feature; } =20 @@ -406,7 +405,7 @@ static unsigned long kvm_sbi_ext_fwft_get_reg_count(str= uct kvm_vcpu *vcpu) continue; =20 conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); - if (!conf || !conf->supported) + if (!conf || !feature->supported(vcpu)) continue; =20 ret++; @@ -428,7 +427,7 @@ static int kvm_sbi_ext_fwft_get_reg_id(struct kvm_vcpu = *vcpu, int index, u64 *re continue; =20 conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); - if (!conf || !conf->supported) + if (!conf || !feature->supported(vcpu)) continue; =20 if (index =3D=3D idx) { @@ -463,7 +462,7 @@ static int kvm_sbi_ext_fwft_get_reg(struct kvm_vcpu *vc= pu, unsigned long reg_num return -ENOENT; =20 conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); - if (!conf || !conf->supported) + if (!conf || !feature->supported(vcpu)) return -ENOENT; =20 switch (reg_num - feature->first_reg_num) { @@ -500,7 +499,7 @@ static int kvm_sbi_ext_fwft_set_reg(struct kvm_vcpu *vc= pu, unsigned long reg_num return -ENOENT; =20 conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); - if (!conf || !conf->supported) + if (!conf || !feature->supported(vcpu)) return -ENOENT; =20 switch (reg_num - feature->first_reg_num) { --=20 2.43.7 From nobody Mon Jun 8 19:57:17 2026 Received: from mail-dy1-f173.google.com (mail-dy1-f173.google.com [74.125.82.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B8532D9797 for ; Wed, 27 May 2026 05:53:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 26 May 2026 22:53:03 -0700 (PDT) Received: from sw07.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304be0851c9sm613202eec.23.2026.05.26.22.53.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2026 22:53:02 -0700 (PDT) From: Yong-Xuan Wang Date: Tue, 26 May 2026 22:52:39 -0700 Subject: [PATCH v2 2/3] KVM: riscv: selftests: Refactor ISA and SBI extension sublist macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260526-kvm-get_reg_list-v2-v2-2-7940a401454a@sifive.com> References: <20260526-kvm-get_reg_list-v2-v2-0-7940a401454a@sifive.com> In-Reply-To: <20260526-kvm-get_reg_list-v2-v2-0-7940a401454a@sifive.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, zong.li@sifive.com, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Yong-Xuan Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779861178; l=6156; i=yongxuan.wang@sifive.com; s=20260424; h=from:subject:message-id; bh=4DPizMp5c9ZYd5J6eYtnzgZrFa5iDZWYGDJjDrKQguI=; b=S7fRaOZsRn89YBqQxmsVvW+ybsBc4X5m6GfdOSpXsQoaqsaJjtbEtjGTpoBsIwuapMZzGmgK0 kWhQZBuxDB7CX0+PG8/0CblcxP79ieiSW4fKv7xcyp6H4A2PQSrsCTB X-Developer-Key: i=yongxuan.wang@sifive.com; a=ed25519; pk=+8NCHB1ZJvZthQAmZspOAaqjo+/snaW8mFSiDx45HxY= Refactor the get-reg-list test to use unified sublist macros for ISA and SBI extensions, eliminating code duplication and improving maintainability. Previously, each extension had its own hand-coded sublist definition (e.g., SUBLIST_ZICBOM, SUBLIST_AIA, etc.) and the config structures repeated the same pattern. This made the code verbose and error-prone. Signed-off-by: Yong-Xuan Wang --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 80 +++++++++-----------= ---- 1 file changed, 29 insertions(+), 51 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 8d6fdb5d38b8..cb16c638ce1a 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -1057,37 +1057,17 @@ static __u64 vector_regs[] =3D { #define SUBLIST_BASE \ {"base", .regs =3D base_regs, .regs_n =3D ARRAY_SIZE(base_regs), \ .skips_set =3D base_skips_set, .skips_set_n =3D ARRAY_SIZE(base_skips_se= t),} -#define SUBLIST_SBI_BASE \ - {"sbi-base", .feature_type =3D VCPU_FEATURE_SBI_EXT, .feature =3D KVM_RIS= CV_SBI_EXT_V01, \ - .regs =3D sbi_base_regs, .regs_n =3D ARRAY_SIZE(sbi_base_regs),} -#define SUBLIST_SBI_STA \ - {"sbi-sta", .feature_type =3D VCPU_FEATURE_SBI_EXT, .feature =3D KVM_RISC= V_SBI_EXT_STA, \ - .regs =3D sbi_sta_regs, .regs_n =3D ARRAY_SIZE(sbi_sta_regs),} -#define SUBLIST_SBI_FWFT \ - {"sbi-fwft", .feature_type =3D VCPU_FEATURE_SBI_EXT, .feature =3D KVM_RIS= CV_SBI_EXT_FWFT, \ - .regs =3D sbi_fwft_regs, .regs_n =3D ARRAY_SIZE(sbi_fwft_regs),} -#define SUBLIST_ZICBOM \ - {"zicbom", .feature =3D KVM_RISCV_ISA_EXT_ZICBOM, .regs =3D zicbom_regs, = .regs_n =3D ARRAY_SIZE(zicbom_regs),} -#define SUBLIST_ZICBOP \ - {"zicbop", .feature =3D KVM_RISCV_ISA_EXT_ZICBOP, .regs =3D zicbop_regs, = .regs_n =3D ARRAY_SIZE(zicbop_regs),} -#define SUBLIST_ZICBOZ \ - {"zicboz", .feature =3D KVM_RISCV_ISA_EXT_ZICBOZ, .regs =3D zicboz_regs, = .regs_n =3D ARRAY_SIZE(zicboz_regs),} -#define SUBLIST_AIA \ - {"aia", .feature =3D KVM_RISCV_ISA_EXT_SSAIA, .regs =3D aia_regs, .regs_n= =3D ARRAY_SIZE(aia_regs),} -#define SUBLIST_SMSTATEEN \ - {"smstateen", .feature =3D KVM_RISCV_ISA_EXT_SMSTATEEN, .regs =3D smstate= en_regs, .regs_n =3D ARRAY_SIZE(smstateen_regs),} -#define SUBLIST_FP_F \ - {"fp_f", .feature =3D KVM_RISCV_ISA_EXT_F, .regs =3D fp_f_regs, \ - .regs_n =3D ARRAY_SIZE(fp_f_regs),} -#define SUBLIST_FP_D \ - {"fp_d", .feature =3D KVM_RISCV_ISA_EXT_D, .regs =3D fp_d_regs, \ - .regs_n =3D ARRAY_SIZE(fp_d_regs),} - -#define SUBLIST_V \ - {"v", .feature =3D KVM_RISCV_ISA_EXT_V, .regs =3D vector_regs, .regs_n = =3D ARRAY_SIZE(vector_regs),} + +#define SUBLIST_ISA(ext, extu) \ + { \ + .name =3D #ext, \ + .feature =3D KVM_RISCV_ISA_EXT_##extu, \ + .regs =3D ext##_regs, \ + .regs_n =3D ARRAY_SIZE(ext##_regs), \ + } =20 #define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \ -static __u64 regs_##ext[] =3D { \ +static __u64 ext##_regs[] =3D { \ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | \ KVM_RISCV_ISA_EXT_##extu, \ @@ -1095,18 +1075,22 @@ static __u64 regs_##ext[] =3D { \ static struct vcpu_reg_list config_##ext =3D { \ .sublists =3D { \ SUBLIST_BASE, \ - { \ - .name =3D #ext, \ - .feature =3D KVM_RISCV_ISA_EXT_##extu, \ - .regs =3D regs_##ext, \ - .regs_n =3D ARRAY_SIZE(regs_##ext), \ - }, \ + SUBLIST_ISA(ext, extu), \ {0}, \ }, \ } \ =20 +#define SUBLIST_SBI(ext, extu) \ + { \ + .name =3D "sbi-"#ext, \ + .feature_type =3D VCPU_FEATURE_SBI_EXT, \ + .feature =3D KVM_RISCV_SBI_EXT_##extu, \ + .regs =3D sbi_##ext##_regs, \ + .regs_n =3D ARRAY_SIZE(sbi_##ext##_regs), \ + } + #define KVM_SBI_EXT_SIMPLE_CONFIG(ext, extu) \ -static __u64 regs_sbi_##ext[] =3D { \ +static __u64 sbi_##ext##_regs[] =3D { \ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | \ KVM_RISCV_SBI_EXT_##extu, \ @@ -1114,13 +1098,7 @@ static __u64 regs_sbi_##ext[] =3D { \ static struct vcpu_reg_list config_sbi_##ext =3D { \ .sublists =3D { \ SUBLIST_BASE, \ - { \ - .name =3D "sbi-"#ext, \ - .feature_type =3D VCPU_FEATURE_SBI_EXT, \ - .feature =3D KVM_RISCV_SBI_EXT_##extu, \ - .regs =3D regs_sbi_##ext, \ - .regs_n =3D ARRAY_SIZE(regs_sbi_##ext), \ - }, \ + SUBLIST_SBI(ext, extu), \ {0}, \ }, \ } \ @@ -1129,7 +1107,7 @@ static struct vcpu_reg_list config_sbi_##ext =3D { \ static struct vcpu_reg_list config_##ext =3D { \ .sublists =3D { \ SUBLIST_BASE, \ - SUBLIST_##extu, \ + SUBLIST_ISA(ext, extu), \ {0}, \ }, \ } \ @@ -1138,14 +1116,14 @@ static struct vcpu_reg_list config_##ext =3D { \ static struct vcpu_reg_list config_sbi_##ext =3D { \ .sublists =3D { \ SUBLIST_BASE, \ - SUBLIST_SBI_##extu, \ + SUBLIST_SBI(ext, extu), \ {0}, \ }, \ } \ =20 /* Note: The below list is alphabetically sorted. */ =20 -KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE); +KVM_SBI_EXT_SUBLIST_CONFIG(base, V01); KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA); KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU); KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN); @@ -1153,10 +1131,10 @@ KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP); KVM_SBI_EXT_SIMPLE_CONFIG(mpxy, MPXY); KVM_SBI_EXT_SUBLIST_CONFIG(fwft, FWFT); =20 -KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA); -KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F); -KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D); -KVM_ISA_EXT_SUBLIST_CONFIG(v, V); +KVM_ISA_EXT_SUBLIST_CONFIG(aia, SSAIA); +KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, F); +KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, D); +KVM_ISA_EXT_SUBLIST_CONFIG(vector, V); KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SIMPLE_CONFIG(smnpm, SMNPM); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); @@ -1240,7 +1218,7 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_fp_f, &config_fp_d, &config_h, - &config_v, + &config_vector, &config_smnpm, &config_smstateen, &config_sscofpmf, --=20 2.43.7 From nobody Mon Jun 8 19:57:17 2026 Received: from mail-dy1-f181.google.com (mail-dy1-f181.google.com [74.125.82.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 330CC2857C7 for ; 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a=ed25519-sha256; t=1779861178; l=7898; i=yongxuan.wang@sifive.com; s=20260424; h=from:subject:message-id; bh=PU3MvdV8tam4q1KMdiajihMJ3i8qhlgrfETzPE8HD/Y=; b=Rf/Bxb/Y6dVq19o6khyGvrIhnmWe6YPFVdkxBIChoeXeDEbJ5eD7cToZTzm/Vs3esy/8MC97k 1y2/g4v/RwICUXDg73dHFNGlE0YaXfV2hGe0iNJyWyk9lFzoRaXUW+j X-Developer-Key: i=yongxuan.wang@sifive.com; a=ed25519; pk=+8NCHB1ZJvZthQAmZspOAaqjo+/snaW8mFSiDx45HxY= Divide the monolithic SBI FWFT (Firmware Features) register list into separate sublists, each testing a specific FWFT feature independently with proper dependency checking. Previously, all FWFT features were tested together in a single sublist. This caused issues because: 1. Not all FWFT features are available on all platforms 2. Some features depend on specific ISA extensions (e.g., pointer_masking requires Smnpm) 3. Tests would fail if any single feature was unavailable Add the feature-specific SBI FWFT sublists with the following improvements: - Add check_supported_reg() function to validate register availability based on required ISA extensions - Add check_fwft_feature() helper to verify FWFT feature availability at runtime - Update filter_reg() to handle per-feature FWFT register filtering Signed-off-by: Yong-Xuan Wang --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 92 ++++++++++++++++++++= +--- 1 file changed, 82 insertions(+), 10 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index cb16c638ce1a..6a34320be78c 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -26,7 +26,21 @@ enum { KVM_RISC_V_REG_OFFSET_MAX, }; =20 -static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX]; +static bool isa_ext_enabled[KVM_RISCV_ISA_EXT_MAX]; + +bool check_supported_reg(struct kvm_vcpu *vcpu, __u64 reg) +{ + switch (reg & ~REG_MASK) { + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(pointer_masking.enable): + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(pointer_masking.flags): + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(pointer_masking.value): + return isa_ext_enabled[KVM_RISCV_ISA_EXT_SMNPM]; + default: + break; + } + + return true; +} =20 bool filter_reg(__u64 reg) { @@ -148,7 +162,12 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_RE= G(siph): case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_RE= G(iprio1h): case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_RE= G(iprio2h): - return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA]; + return isa_ext_enabled[KVM_RISCV_ISA_EXT_SSAIA]; + /* KVM misaligned delegation registers are always visible when the host s= upports it */ + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(misaligned_deleg.enable): + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(misaligned_deleg.flags): + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(misaligned_deleg.value): + return true; default: break; } @@ -193,15 +212,39 @@ static int override_vector_reg_size(struct kvm_vcpu *= vcpu, struct vcpu_reg_subli return 0; } =20 +void check_fwft_feature(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s,= u64 feature) +{ + unsigned long value; + int rc; + + /* Enable SBI FWFT extension so that we can check the supported register = */ + rc =3D __vcpu_set_reg(vcpu, feature, 1); + if (rc) + return; + + for (int i =3D 0; i < s->regs_n; i++) { + if ((s->regs[i] & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_SBI_STAT= E) { + rc =3D __vcpu_get_reg(vcpu, s->regs[i], &value); + __TEST_REQUIRE(!rc, "%s not available, skipping tests", s->name); + } + } + + /* We should assert if disabling failed here while enabling succeeded bef= ore */ + vcpu_set_reg(vcpu, feature, 0); +} + void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) { - unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] =3D { 0 }; + unsigned long isa_ext_state; struct vcpu_reg_sublist *s; u64 feature; int rc; =20 - for (int i =3D 0; i < KVM_RISCV_ISA_EXT_MAX; i++) - __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]); + for (int i =3D 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { + rc =3D __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state); + if (!rc) + isa_ext_enabled[i] =3D !!isa_ext_state; + } =20 /* * Disable all extensions which were enabled by default @@ -209,8 +252,10 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_= reg_list *c) */ for (int i =3D 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { rc =3D __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0); - if (rc && isa_ext_state[i]) - isa_ext_cant_disable[i] =3D true; + if (rc && isa_ext_enabled[i]) + isa_ext_enabled[i] =3D true; + else + isa_ext_enabled[i] =3D false; } =20 for (int i =3D 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { @@ -229,9 +274,15 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_= reg_list *c) goto skip; } =20 + if (s->feature =3D=3D KVM_RISCV_SBI_EXT_FWFT) { + feature =3D RISCV_SBI_EXT_REG(KVM_RISCV_SBI_EXT_FWFT); + check_fwft_feature(vcpu, s, feature); + } + switch (s->feature_type) { case VCPU_FEATURE_ISA_EXT: feature =3D RISCV_ISA_EXT_REG(s->feature); + isa_ext_enabled[s->feature] =3D true; break; case VCPU_FEATURE_SBI_EXT: feature =3D RISCV_SBI_EXT_REG(s->feature); @@ -897,11 +948,15 @@ static __u64 sbi_sta_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi), }; =20 -static __u64 sbi_fwft_regs[] =3D { +static __u64 sbi_fwft_misaligned_deleg_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISC= V_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value), +}; + +static __u64 sbi_fwft_pointer_masking_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISC= V_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), @@ -1129,7 +1184,6 @@ KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU); KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN); KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP); KVM_SBI_EXT_SIMPLE_CONFIG(mpxy, MPXY); -KVM_SBI_EXT_SUBLIST_CONFIG(fwft, FWFT); =20 KVM_ISA_EXT_SUBLIST_CONFIG(aia, SSAIA); KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, F); @@ -1206,6 +1260,23 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED); KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH); KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT); =20 +static struct vcpu_reg_list config_sbi_fwft_misaligned_deleg =3D { + .sublists =3D { + SUBLIST_BASE, + SUBLIST_SBI(fwft_misaligned_deleg, FWFT), + {0}, + }, +}; + +static struct vcpu_reg_list config_sbi_fwft_pointer_masking =3D { + .sublists =3D { + SUBLIST_BASE, + SUBLIST_ISA(smnpm, SMNPM), + SUBLIST_SBI(fwft_pointer_masking, FWFT), + {0}, + }, +}; + struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_base, &config_sbi_sta, @@ -1213,7 +1284,8 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_dbcn, &config_sbi_susp, &config_sbi_mpxy, - &config_sbi_fwft, + &config_sbi_fwft_misaligned_deleg, + &config_sbi_fwft_pointer_masking, &config_aia, &config_fp_f, &config_fp_d, --=20 2.43.7