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These registers are organized in H/W as below on various SoCs. +---------------------------------------------------------------+ | SM8350, SM8450 | SM8550, Hamoa | SM8650, SM8750 | |---------------------------------------------------------------| | v2.7 | v3.0 | v3.2 | |---------------------------------------------------------------| | IRQ_ENABLE_BANK | IRQ_ENABLE_BANK | NA | |---------------------------------------------------------------| | IRQ_CFG | IRQ_CFG | IRQ_CFG | | | | | | | | [31:6] Unused | | | [31:5] Unused | [5] GPIO_STATUS | | | [4] GPIO_STATUS| [4] GPIO_MASK | | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE | | [0:2] Type | [0:2] Type | [0:2] Type | +---------------------------------------------------------------| All SoCs PDC irqchip supports "pass through mode" in which all interrupts are forwarded to the GIC without any latching at PDC H/W. So far irqchip did not utilize GPIO_STATUS and GPIO_MASK from IRQ_CFG register for v3.0 and v3.2 since they are only needed to be configured when PDC runs in specific mode named "second level interrupt controller" where it can latch the GPIO interrupts in GPIO_STATUS and forward GPIO interrupts to GIC as LEVEL_HIGH type SPI interrupt. All the SoCs defaulted to pass through mode with the exception of some x1e. x1e PDC may be set to secondary controller mode for builds on CRD boards whereas it may be set to pass through mode for IoT-EVK boards. Restructure in preparation to add the second level interrupt controller mode utilizing GPIO_STATUS and GPIO_MASK bits which changed the bit positions between v3.0 and v3.2. No functional impact with the change. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 193 +++++++++++++++++++++++++++++++++++------= ---- 1 file changed, 150 insertions(+), 43 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 638b5d89a141..c5b64649b2a9 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -21,18 +21,10 @@ #include #include =20 -#define PDC_MAX_GPIO_IRQS 256 -#define PDC_DRV_SIZE 0x10000 - -/* Valid only on HW version < 3.2 */ -#define IRQ_ENABLE_BANK 0x10 -#define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_= IRQS)) -#define IRQ_i_CFG 0x110 +#define PDC_MAX_IRQS 256 +#define IRQ_ENABLE_BANK_MAX BITS_TO_BYTES(PDC_MAX_IRQS) =20 -/* Valid only on HW version >=3D 3.2 */ -#define IRQ_i_CFG_IRQ_ENABLE 3 - -#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0) +#define PDC_DRV_SIZE 0x10000 =20 #define PDC_VERSION_REG 0x1000 #define PDC_VERSION_MAJOR GENMASK(23, 16) @@ -45,6 +37,98 @@ =20 /* Notable PDC versions */ #define PDC_VERSION_3_2 PDC_VERSION(3, 2, 0) +#define PDC_VERSION_3_0 PDC_VERSION(3, 0, 0) +#define PDC_VERSION_2_7 PDC_VERSION(2, 7, 0) + +/* + * PDC H/W registers layout per version: + * + * IRQ_ENABLE_BANK[b], b =3D 0....BITS_TO_BYTES(PDC_MAX_IRQS) + * IRQ_CFG[n], n =3D 0....PDC_MAX_IRQS + * + * +---------------------------------------------------------------+ + * | v2.7 | v3.0 | v3.2 | + * |---------------------------------------------------------------| + * | BASE | BASE | BASE | + * |---------------------------------------------------------------| + * | | + * | IRQ_ENABLE_BANK | IRQ_ENABLE_BANK | NA | + * |---------------------------------------------------------------| + * | IRQ_CFG | IRQ_CFG | IRQ_CFG | + * | | | | + * | | | [31:6] Unused | + * | | [31:5] Unused | [5] GPIO_STATUS | + * | | [4] GPIO_STATUS| [4] GPIO_MASK | + * | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE | + * | [0:2] Type | [0:2] Type | [0:2] Type | + * +---------------------------------------------------------------+ + */ + +/** + * struct pdc_regs: PDC registers location + * + * @irq_en_reg: IRQ_ENABLE_BANK register location + * @irq_cfg_reg: IRQ_CFG register location + */ +struct pdc_regs { + u32 irq_en_reg; + u32 irq_cfg_reg; +}; + +/** + * struct pdc_cfg: bit fields for PDC IRQ_CFG register + * + * @irq_enable: bit mask for IRQ_ENABLE + * @irq_type: bit mask for IRQ_TYPE + */ +struct pdc_cfg { + u32 irq_enable; + u32 irq_type; +}; + +/** + * struct pdc_desc: PDC driver state + * + * @base: PDC base register for DRV2 / HLOS + * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. + * @version: PDC version + * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG) + * @cfg: bit masks within for IRQ_CFG reg + */ +struct pdc_desc { + void __iomem *base; + void __iomem *prev_base; + u32 version; + const struct pdc_regs *regs; + const struct pdc_cfg *cfg; +}; + +static const struct pdc_regs pdc_v3_2 =3D { + .irq_cfg_reg =3D 0x110, +}; + +static const struct pdc_cfg pdc_cfg_v3_2 =3D { + .irq_enable =3D GENMASK(3, 3), + .irq_type =3D GENMASK(2, 0), +}; + +static const struct pdc_regs pdc_v3_0 =3D { + .irq_en_reg =3D 0x10, + .irq_cfg_reg =3D 0x110, +}; + +static const struct pdc_cfg pdc_cfg_v3_0 =3D { + .irq_type =3D GENMASK(2, 0), +}; + +static const struct pdc_regs pdc_v2_7 =3D { + .irq_en_reg =3D 0x10, + .irq_cfg_reg =3D 0x110, +}; + +static const struct pdc_cfg pdc_cfg_v2_7 =3D { + .irq_type =3D GENMASK(2, 0), +}; =20 struct pdc_pin_region { u32 pin_base; @@ -55,12 +139,11 @@ struct pdc_pin_region { #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) =20 static DEFINE_RAW_SPINLOCK(pdc_lock); -static void __iomem *pdc_base; -static void __iomem *pdc_prev_base; static struct pdc_pin_region *pdc_region; static int pdc_region_cnt; static void (*__pdc_enable_intr)(int pin_out, bool on); static bool pdc_x1e_quirk; +static struct pdc_desc *pdc; =20 static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val) { @@ -69,12 +152,12 @@ static void pdc_base_reg_write(void __iomem *base, int= reg, u32 i, u32 val) =20 static void pdc_reg_write(int reg, u32 i, u32 val) { - pdc_base_reg_write(pdc_base, reg, i, val); + pdc_base_reg_write(pdc->base, reg, i, val); } =20 static u32 pdc_reg_read(int reg, u32 i) { - return readl_relaxed(pdc_base + reg + i * sizeof(u32)); + return readl_relaxed(pdc->base + reg + i * sizeof(u32)); } =20 static void pdc_x1e_irq_enable_write(u32 bank, u32 enable) @@ -85,24 +168,24 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 ena= ble) switch (bank) { case 0 ... 1: /* Use previous DRV (client) region and shift to bank 3-4 */ - base =3D pdc_prev_base; + base =3D pdc->prev_base; bank +=3D 3; break; case 2 ... 4: /* Use our own region and shift to bank 0-2 */ - base =3D pdc_base; + base =3D pdc->base; bank -=3D 2; break; case 5: /* No fixup required for bank 5 */ - base =3D pdc_base; + base =3D pdc->base; break; default: WARN_ON(1); return; } =20 - pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable); + pdc_base_reg_write(base, pdc->regs->irq_en_reg, bank, enable); } =20 static void pdc_enable_intr_bank(int pin_out, bool on) @@ -113,22 +196,25 @@ static void pdc_enable_intr_bank(int pin_out, bool on) index =3D FIELD_GET(GENMASK(31, 5), pin_out); mask =3D FIELD_GET(GENMASK(4, 0), pin_out); =20 - enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); + enable =3D pdc_reg_read(pdc->regs->irq_en_reg, index); __assign_bit(mask, &enable, on); =20 if (pdc_x1e_quirk) pdc_x1e_irq_enable_write(index, enable); else - pdc_reg_write(IRQ_ENABLE_BANK, index, enable); + pdc_reg_write(pdc->regs->irq_en_reg, index, enable); } =20 static void pdc_enable_intr_cfg(int pin_out, bool on) { unsigned long enable; =20 - enable =3D pdc_reg_read(IRQ_i_CFG, pin_out); - __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); - pdc_reg_write(IRQ_i_CFG, pin_out, enable); + enable =3D pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); + if (on) + enable |=3D pdc->cfg->irq_enable; + else + enable &=3D ~pdc->cfg->irq_enable; + pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable); } =20 static void pdc_enable_intr(struct irq_data *d, bool on) @@ -216,9 +302,9 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, un= signed int type) return -EINVAL; } =20 - old_pdc_type =3D pdc_reg_read(IRQ_i_CFG, d->hwirq); - pdc_type |=3D (old_pdc_type & ~IRQ_i_CFG_TYPE_MASK); - pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); + old_pdc_type =3D pdc_reg_read(pdc->regs->irq_cfg_reg, d->hwirq); + pdc_type |=3D (old_pdc_type & ~pdc->cfg->irq_type); + pdc_reg_write(pdc->regs->irq_cfg_reg, d->hwirq, pdc_type); =20 ret =3D irq_chip_set_type_parent(d, type); if (ret) @@ -375,6 +461,34 @@ static int qcom_pdc_probe(struct platform_device *pdev= , struct device_node *pare if (res_size > resource_size(&res)) pr_warn("%pOF: invalid reg size, please fix DT\n", node); =20 + pdc =3D kzalloc_objs(*pdc, GFP_KERNEL); + if (!pdc) + return -ENOMEM; + + pdc->base =3D ioremap(res.start, res_size); + if (!pdc->base) { + pr_err("%pOF: unable to map PDC registers\n", node); + ret =3D -ENXIO; + goto fail; + } + + pdc->version =3D pdc_reg_read(PDC_VERSION_REG, 0); + + if (pdc->version >=3D PDC_VERSION_3_2) { + pdc->cfg =3D &pdc_cfg_v3_2; + pdc->regs =3D &pdc_v3_2; + __pdc_enable_intr =3D pdc_enable_intr_cfg; + } else if (pdc->version < PDC_VERSION_3_2 && + pdc->version >=3D PDC_VERSION_3_0) { + pdc->cfg =3D &pdc_cfg_v3_0; + pdc->regs =3D &pdc_v3_0; + __pdc_enable_intr =3D pdc_enable_intr_bank; + } else { + pdc->cfg =3D &pdc_cfg_v2_7; + pdc->regs =3D &pdc_v2_7; + __pdc_enable_intr =3D pdc_enable_intr_bank; + } + /* * PDC has multiple DRV regions, each one provides the same set of * registers for a particular client in the system. Due to a hardware @@ -384,25 +498,17 @@ static int qcom_pdc_probe(struct platform_device *pde= v, struct device_node *pare * region with the expected offset to preserve support for old DTs. */ if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) { - pdc_prev_base =3D ioremap(res.start - PDC_DRV_SIZE, IRQ_ENABLE_BANK_MAX); - if (!pdc_prev_base) { + pdc->prev_base =3D ioremap(res.start - PDC_DRV_SIZE, + pdc->regs->irq_en_reg + IRQ_ENABLE_BANK_MAX); + if (!pdc->prev_base) { pr_err("%pOF: unable to map previous PDC DRV region\n", node); - return -ENXIO; + ret =3D -ENXIO; + goto fail; } =20 pdc_x1e_quirk =3D true; } =20 - pdc_base =3D ioremap(res.start, res_size); - if (!pdc_base) { - pr_err("%pOF: unable to map PDC registers\n", node); - ret =3D -ENXIO; - goto fail; - } - - __pdc_enable_intr =3D (pdc_reg_read(PDC_VERSION_REG, 0) < PDC_VERSION_3_2= ) ? - pdc_enable_intr_bank : pdc_enable_intr_cfg; - parent_domain =3D irq_find_host(parent); if (!parent_domain) { pr_err("%pOF: unable to find PDC's parent domain\n", node); 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Move all to struct pdc_desc to better align with versioning support. Document them. No functional impact. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 68 +++++++++++++++++++++++++++---------------= ---- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index c5b64649b2a9..8f7802139e4e 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -92,15 +92,30 @@ struct pdc_cfg { * @base: PDC base register for DRV2 / HLOS * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. * @version: PDC version + * @region: PDC interrupt continuous range + * @region_cnt: Total PDC ranges + * @x1e_quirk: x1e H/W Bug handling + * @lock: lock for IRQ_ENABLE_BANK protection * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG) * @cfg: bit masks within for IRQ_CFG reg + * @enable_intr: pointer to enable function based on PDC version */ struct pdc_desc { void __iomem *base; void __iomem *prev_base; u32 version; + + struct pdc_pin_region *region; + int region_cnt; + + bool x1e_quirk; + + raw_spinlock_t lock; + const struct pdc_regs *regs; const struct pdc_cfg *cfg; + + void (*enable_intr)(int pin_out, bool on); }; =20 static const struct pdc_regs pdc_v3_2 =3D { @@ -138,11 +153,6 @@ struct pdc_pin_region { =20 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) =20 -static DEFINE_RAW_SPINLOCK(pdc_lock); -static struct pdc_pin_region *pdc_region; -static int pdc_region_cnt; -static void (*__pdc_enable_intr)(int pin_out, bool on); -static bool pdc_x1e_quirk; static struct pdc_desc *pdc; =20 static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val) @@ -199,7 +209,7 @@ static void pdc_enable_intr_bank(int pin_out, bool on) enable =3D pdc_reg_read(pdc->regs->irq_en_reg, index); __assign_bit(mask, &enable, on); =20 - if (pdc_x1e_quirk) + if (pdc->x1e_quirk) pdc_x1e_irq_enable_write(index, enable); else pdc_reg_write(pdc->regs->irq_en_reg, index, enable); @@ -221,9 +231,9 @@ static void pdc_enable_intr(struct irq_data *d, bool on) { unsigned long flags; =20 - raw_spin_lock_irqsave(&pdc_lock, flags); - __pdc_enable_intr(d->hwirq, on); - raw_spin_unlock_irqrestore(&pdc_lock, flags); + raw_spin_lock_irqsave(&pdc->lock, flags); + pdc->enable_intr(d->hwirq, on); + raw_spin_unlock_irqrestore(&pdc->lock, flags); } =20 static void qcom_pdc_gic_disable(struct irq_data *d) @@ -348,10 +358,10 @@ static struct pdc_pin_region *get_pin_region(int pin) { int i; =20 - for (i =3D 0; i < pdc_region_cnt; i++) { - if (pin >=3D pdc_region[i].pin_base && - pin < pdc_region[i].pin_base + pdc_region[i].cnt) - return &pdc_region[i]; + for (i =3D 0; i < pdc->region_cnt; i++) { + if (pin >=3D pdc->region[i].pin_base && + pin < pdc->region[i].pin_base + pdc->region[i].cnt) + return &pdc->region[i]; } =20 return NULL; @@ -413,32 +423,32 @@ static int pdc_setup_pin_mapping(struct device_node *= np) if (n <=3D 0 || n % 3) return -EINVAL; =20 - pdc_region_cnt =3D n / 3; - pdc_region =3D kzalloc_objs(*pdc_region, pdc_region_cnt); - if (!pdc_region) { - pdc_region_cnt =3D 0; + pdc->region_cnt =3D n / 3; + pdc->region =3D kzalloc_objs(*pdc->region, pdc->region_cnt); + if (!pdc->region) { + pdc->region_cnt =3D 0; return -ENOMEM; } =20 - for (n =3D 0; n < pdc_region_cnt; n++) { + for (n =3D 0; n < pdc->region_cnt; n++) { ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 0, - &pdc_region[n].pin_base); + &pdc->region[n].pin_base); if (ret) return ret; ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 1, - &pdc_region[n].parent_base); + &pdc->region[n].parent_base); if (ret) return ret; ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 2, - &pdc_region[n].cnt); + &pdc->region[n].cnt); if (ret) return ret; =20 - for (i =3D 0; i < pdc_region[n].cnt; i++) - __pdc_enable_intr(i + pdc_region[n].pin_base, 0); + for (i =3D 0; i < pdc->region[n].cnt; i++) + pdc->enable_intr(i + pdc->region[n].pin_base, 0); } =20 return 0; @@ -477,16 +487,16 @@ static int qcom_pdc_probe(struct platform_device *pde= v, struct device_node *pare if (pdc->version >=3D PDC_VERSION_3_2) { pdc->cfg =3D &pdc_cfg_v3_2; pdc->regs =3D &pdc_v3_2; - __pdc_enable_intr =3D pdc_enable_intr_cfg; + pdc->enable_intr =3D pdc_enable_intr_cfg; } else if (pdc->version < PDC_VERSION_3_2 && pdc->version >=3D PDC_VERSION_3_0) { pdc->cfg =3D &pdc_cfg_v3_0; pdc->regs =3D &pdc_v3_0; - __pdc_enable_intr =3D pdc_enable_intr_bank; + pdc->enable_intr =3D pdc_enable_intr_bank; } else { pdc->cfg =3D &pdc_cfg_v2_7; pdc->regs =3D &pdc_v2_7; - __pdc_enable_intr =3D pdc_enable_intr_bank; + pdc->enable_intr =3D pdc_enable_intr_bank; } =20 /* @@ -506,7 +516,7 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare goto fail; } =20 - pdc_x1e_quirk =3D true; + pdc->x1e_quirk =3D true; } =20 parent_domain =3D irq_find_host(parent); @@ -522,6 +532,8 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare goto fail; } =20 + raw_spin_lock_init(&pdc->lock); + pdc_domain =3D irq_domain_create_hierarchy(parent_domain, IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, PDC_MAX_IRQS, @@ -538,7 +550,7 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare return 0; 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Remove the wrapper and invoke pdc->enable_intr() from caller. Locking in pdc_enable_intr() applies lock to all pdc->enable_intr() however its only required for pdc_enable_intr_bank() which uses a shared bank across all interrupts. pdc_enable_intr_cfg() do not required locking as IRQ_CFG registers are one per interrupt. Move locking accordingly. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 8f7802139e4e..db76737646e1 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -201,11 +201,14 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 en= able) static void pdc_enable_intr_bank(int pin_out, bool on) { unsigned long enable; + unsigned long flags; u32 index, mask; =20 index =3D FIELD_GET(GENMASK(31, 5), pin_out); mask =3D FIELD_GET(GENMASK(4, 0), pin_out); =20 + raw_spin_lock_irqsave(&pdc->lock, flags); + enable =3D pdc_reg_read(pdc->regs->irq_en_reg, index); __assign_bit(mask, &enable, on); =20 @@ -213,6 +216,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on) pdc_x1e_irq_enable_write(index, enable); else pdc_reg_write(pdc->regs->irq_en_reg, index, enable); + + raw_spin_unlock_irqrestore(&pdc->lock, flags); } =20 static void pdc_enable_intr_cfg(int pin_out, bool on) @@ -227,24 +232,15 @@ static void pdc_enable_intr_cfg(int pin_out, bool on) pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable); 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Separate domains can be useful in case irqchip want to differentiate both of them. Since commit unified both the domains there is no way to differentiate. In preparation to add the second level interrupt controller support where GPIO interrupts get lateched at PDC (but not direct SPIs) there is a need to differentiate between SPIs and GPIOs as SPIs. Reverting above commit do not seem a good option either which leads to waste of resources. PDC HW have the IRQ_PARAM register telling number of direct SPIs and number of GPIOs as SPIs. Further PDC allocates direct SPIs at the beginning and all GPIOs as SPIs are allocated at the end. This information can be used in driver to differentiate them. Add the support to read this register and keep this information in struct pdc_desc. Later change utilizes same. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index db76737646e1..86379dddc5be 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -61,6 +61,11 @@ * | | [4] GPIO_STATUS| [4] GPIO_MASK | * | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE | * | [0:2] Type | [0:2] Type | [0:2] Type | + * |---------------------------------------------------------------| + * | IRQ_PARAM | IRQ_PARAM | IRQ_PARAM | + * | | | + * | [15:8] NUM_GPIO | [15:8] NUM_GPIO | [15:8] NUM_GPIO | + * | [7:0] NUM_SPI | [7:0] NUM_SPI | [7:0] NUM_SPI | * +---------------------------------------------------------------+ */ =20 @@ -69,10 +74,12 @@ * * @irq_en_reg: IRQ_ENABLE_BANK register location * @irq_cfg_reg: IRQ_CFG register location + * @irq_param_reg: IRQ_PARAM register location */ struct pdc_regs { u32 irq_en_reg; u32 irq_cfg_reg; + u32 irq_param_reg; }; =20 /** @@ -92,6 +99,8 @@ struct pdc_cfg { * @base: PDC base register for DRV2 / HLOS * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. * @version: PDC version + * @num_spis: Total number of direct SPI interrupts + * @num_gpios: Total number of GPIOs forwarded as SPI interrupts * @region: PDC interrupt continuous range * @region_cnt: Total PDC ranges * @x1e_quirk: x1e H/W Bug handling @@ -104,6 +113,8 @@ struct pdc_desc { void __iomem *base; void __iomem *prev_base; u32 version; + u32 num_spis; + u32 num_gpios; =20 struct pdc_pin_region *region; int region_cnt; @@ -120,6 +131,7 @@ struct pdc_desc { =20 static const struct pdc_regs pdc_v3_2 =3D { .irq_cfg_reg =3D 0x110, + .irq_param_reg =3D 0x100c, }; =20 static const struct pdc_cfg pdc_cfg_v3_2 =3D { @@ -130,6 +142,7 @@ static const struct pdc_cfg pdc_cfg_v3_2 =3D { static const struct pdc_regs pdc_v3_0 =3D { .irq_en_reg =3D 0x10, .irq_cfg_reg =3D 0x110, + .irq_param_reg =3D 0x100c, }; =20 static const struct pdc_cfg pdc_cfg_v3_0 =3D { @@ -139,6 +152,7 @@ static const struct pdc_cfg pdc_cfg_v3_0 =3D { static const struct pdc_regs pdc_v2_7 =3D { .irq_en_reg =3D 0x10, .irq_cfg_reg =3D 0x110, + .irq_param_reg =3D 0x100c, }; =20 static const struct pdc_cfg pdc_cfg_v2_7 =3D { @@ -457,6 +471,7 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare struct device_node *node =3D pdev->dev.of_node; resource_size_t res_size; struct resource res; + u32 irq_param; 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Newer PDCs (v3.0 onwards) also support additional secondary controller mode where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs still works same as pass through mode without latching at PDC even in secondary controller mode. All the SoCs so far default uses pass through mode with the exception of x1e. x1e PDC may be set to secondary controller mode for builds on CRD boards whereas it may be set to pass through mode for IoT-EVK boards. The mode configuration is done in firmware and initially shipped windows firmware did not have SCM interface to read or modify the PDC mode. Later only write access is opened up for non secure world. Using the write access available add changes to modify the PDC mode to pass through mode via SCM write. When the write fails (on older firmware) assume to work in secondary mode. Co-developed-by: Sneh Mankad Signed-off-by: Sneh Mankad Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 109 +++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 106 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 86379dddc5be..69ddd7d89a83 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -20,12 +20,18 @@ #include #include #include +#include =20 #define PDC_MAX_IRQS 256 #define IRQ_ENABLE_BANK_MAX BITS_TO_BYTES(PDC_MAX_IRQS) =20 #define PDC_DRV_SIZE 0x10000 =20 +/* Secure DRV register to configure the PDC mode via qcom_scm_io_writel() = */ +#define PDC_GPIO_INT_CTL_ENABLE 0xb2045e8 +#define PDC_PASS_THROUGH_MODE 0x0 +#define PDC_SECONDARY_MODE 0x1 + #define PDC_VERSION_REG 0x1000 #define PDC_VERSION_MAJOR GENMASK(23, 16) #define PDC_VERSION_MINOR GENMASK(15, 8) @@ -85,10 +91,14 @@ struct pdc_regs { /** * struct pdc_cfg: bit fields for PDC IRQ_CFG register * + * @gpio_irq_sts: bit mask for GPIO_STATUS + * @gpio_irq_mask: bit mask for GPIO_MASK * @irq_enable: bit mask for IRQ_ENABLE * @irq_type: bit mask for IRQ_TYPE */ struct pdc_cfg { + u32 gpio_irq_sts; + u32 gpio_irq_mask; u32 irq_enable; u32 irq_type; }; @@ -103,11 +113,14 @@ struct pdc_cfg { * @num_gpios: Total number of GPIOs forwarded as SPI interrupts * @region: PDC interrupt continuous range * @region_cnt: Total PDC ranges + * @mode: PDC_PASS_THROUGH_MODE or PDC_SECONDARY_MODE * @x1e_quirk: x1e H/W Bug handling * @lock: lock for IRQ_ENABLE_BANK protection * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG) * @cfg: bit masks within for IRQ_CFG reg * @enable_intr: pointer to enable function based on PDC version + * @unmask_gpio: pointer to GPIO irq unmask function + * @clear_gpio: pointer to GPIO irq clear function */ struct pdc_desc { void __iomem *base; @@ -119,6 +132,7 @@ struct pdc_desc { struct pdc_pin_region *region; int region_cnt; =20 + u8 mode; bool x1e_quirk; =20 raw_spinlock_t lock; @@ -127,6 +141,8 @@ struct pdc_desc { const struct pdc_cfg *cfg; =20 void (*enable_intr)(int pin_out, bool on); + void (*unmask_gpio)(int pin_out, bool on); + void (*clear_gpio)(int pin_out); }; =20 static const struct pdc_regs pdc_v3_2 =3D { @@ -135,6 +151,8 @@ static const struct pdc_regs pdc_v3_2 =3D { }; =20 static const struct pdc_cfg pdc_cfg_v3_2 =3D { + .gpio_irq_sts =3D GENMASK(5, 5), + .gpio_irq_mask =3D GENMASK(4, 4), .irq_enable =3D GENMASK(3, 3), .irq_type =3D GENMASK(2, 0), }; @@ -146,6 +164,8 @@ static const struct pdc_regs pdc_v3_0 =3D { }; =20 static const struct pdc_cfg pdc_cfg_v3_0 =3D { + .gpio_irq_sts =3D GENMASK(4, 4), + .gpio_irq_mask =3D GENMASK(3, 3), .irq_type =3D GENMASK(2, 0), }; =20 @@ -184,6 +204,14 @@ static u32 pdc_reg_read(int reg, u32 i) return readl_relaxed(pdc->base + reg + i * sizeof(u32)); } =20 +static inline bool pdc_pin_uses_seconary_mode(int pin_out) +{ + if (pdc->mode =3D=3D PDC_SECONDARY_MODE && pin_out >=3D pdc->num_spis) + return true; + + return false; +} + static void pdc_x1e_irq_enable_write(u32 bank, u32 enable) { void __iomem *base; @@ -232,6 +260,36 @@ static void pdc_enable_intr_bank(int pin_out, bool on) pdc_reg_write(pdc->regs->irq_en_reg, index, enable); =20 raw_spin_unlock_irqrestore(&pdc->lock, flags); + + if (pdc_pin_uses_seconary_mode(pin_out)) + pdc->unmask_gpio(pin_out, on); +} + +static void pdc_clear_gpio_cfg(int pin_out) +{ + unsigned long gpio_sts; + + if (pdc->version < PDC_VERSION_3_0) + return; + + gpio_sts =3D pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); + gpio_sts &=3D ~pdc->cfg->gpio_irq_sts; + pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_sts); +} + +static void pdc_unmask_gpio_cfg(int pin_out, bool unmask) +{ + unsigned long gpio_mask; + + if (pdc->version < PDC_VERSION_3_0) + return; + + gpio_mask =3D pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); + if (unmask) + gpio_mask &=3D ~pdc->cfg->gpio_irq_mask; + else + gpio_mask |=3D pdc->cfg->gpio_irq_mask; + pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_mask); } =20 static void pdc_enable_intr_cfg(int pin_out, bool on) @@ -244,6 +302,9 @@ static void pdc_enable_intr_cfg(int pin_out, bool on) else enable &=3D ~pdc->cfg->irq_enable; pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable); + + if (pdc_pin_uses_seconary_mode(pin_out)) + pdc->unmask_gpio(pin_out, on); } =20 static void qcom_pdc_gic_disable(struct irq_data *d) @@ -258,6 +319,20 @@ static void qcom_pdc_gic_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static void qcom_pdc_ack(struct irq_data *d) +{ + if (pdc_pin_uses_seconary_mode(d->hwirq) && !irqd_is_level_type(d)) + pdc->clear_gpio(d->hwirq); +} + +static void qcom_pdc_gic_eoi(struct irq_data *d) +{ + if (pdc_pin_uses_seconary_mode(d->hwirq) && irqd_is_level_type(d)) + pdc->clear_gpio(d->hwirq); + + irq_chip_eoi_parent(d); +} + /* * GIC does not handle falling edge or active low. To allow falling edge a= nd * active low interrupts to be handled at GIC, PDC has an inverter that in= verts @@ -291,6 +366,8 @@ enum pdc_irq_config_bits { * takes care of converting falling edge to rising edge signal * If @type is level, then forward that as level high as PDC * takes care of converting falling edge to rising edge signal + * If interrupt is GPIO and PDC is in secondary mode forward that + * as level high as PDC takes care of coverting all types to level high */ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) { @@ -326,6 +403,16 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, u= nsigned int type) pdc_type |=3D (old_pdc_type & ~pdc->cfg->irq_type); pdc_reg_write(pdc->regs->irq_cfg_reg, d->hwirq, pdc_type); =20 + if (pdc_pin_uses_seconary_mode(d->hwirq)) { + /* + * PDC forwards GPIOs as level high to GIC in secondary + * mode. Update the type and clear any previously latched + * phantom interrupt at PDC. + */ + type =3D IRQ_TYPE_LEVEL_HIGH; + pdc->clear_gpio(d->hwirq); + } + ret =3D irq_chip_set_type_parent(d, type); if (ret) return ret; @@ -347,7 +434,8 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, un= signed int type) =20 static struct irq_chip qcom_pdc_gic_chip =3D { .name =3D "PDC", - .irq_eoi =3D irq_chip_eoi_parent, + .irq_ack =3D qcom_pdc_ack, + .irq_eoi =3D qcom_pdc_gic_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D qcom_pdc_gic_disable, @@ -457,8 +545,10 @@ static int pdc_setup_pin_mapping(struct device_node *n= p) if (ret) return ret; =20 - for (i =3D 0; i < pdc->region[n].cnt; i++) - pdc->enable_intr(i + pdc->region[n].pin_base, 0); + for (i =3D 0; i < pdc->region[n].cnt; i++) { + pdc->clear_gpio(i + pdc->region[n].pin_base); + pdc->enable_intr(i + pdc->region[n].pin_base, false); + } } =20 return 0; @@ -510,6 +600,10 @@ static int qcom_pdc_probe(struct platform_device *pdev= , struct device_node *pare pdc->enable_intr =3D pdc_enable_intr_bank; } =20 + pdc->unmask_gpio =3D pdc_unmask_gpio_cfg; + pdc->clear_gpio =3D pdc_clear_gpio_cfg; + pdc->mode =3D PDC_PASS_THROUGH_MODE; + /* * PDC has multiple DRV regions, each one provides the same set of * registers for a particular client in the system. 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For level-triggered IRQs this happens automatically in irq_eoi() but for edge-triggered IRQs this needs to happen as early as possible in the IRQ handler. Implement this by using handle_fasteoi_ack_irq() as IRQ handler in this situation and forward the irq_ack() callback to the parent IRQ chip. Signed-off-by: Stephan Gerhold Signed-off-by: Maulik Shah --- drivers/pinctrl/qcom/pinctrl-msm.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinc= trl-msm.c index 45b3a2763eb8..c2938494c6bb 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -995,6 +995,16 @@ static void msm_gpio_irq_ack(struct irq_data *d) if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) msm_gpio_update_dual_edge_parent(d); + + /* + * During early initialization of the IRQ hierarchy, + * irq_ack() is called by __irq_set_handler() before + * the parent IRQ chip has been set up. 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PDC interrupts no more break GPIOs PDC irqchip is updated to work for pass through or secondary mode. Update nwakeirq_map to reflect the GPIO to PDC irq map size. Signed-off-by: Maulik Shah --- drivers/pinctrl/qcom/pinctrl-x1e80100.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom= /pinctrl-x1e80100.c index 8d2b8246170b..e4c0abcd95b9 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1836,9 +1836,7 @@ static const struct msm_pinctrl_soc_data x1e80100_pin= ctrl =3D { .ngroups =3D ARRAY_SIZE(x1e80100_groups), .ngpios =3D 239, .wakeirq_map =3D x1e80100_pdc_map, - /* TODO: Enabling PDC currently breaks GPIO interrupts */ - .nwakeirq_map =3D 0, - /* .nwakeirq_map =3D ARRAY_SIZE(x1e80100_pdc_map), */ + .nwakeirq_map =3D ARRAY_SIZE(x1e80100_pdc_map), .egpio_func =3D 9, }; =20 --=20 2.43.0 From nobody Mon Jun 8 22:01:35 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AEDA3DFC79 for ; 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Signed-off-by: Maulik Shah --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index b5516655db8c..5a1b041ea768 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -302,6 +302,14 @@ cluster_cl5: cluster-sleep-1 { exit-latency-us =3D <4000>; min-residency-us =3D <7000>; }; + + domain_ss3: domain-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x0200c354>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <9000>; + }; }; }; =20 @@ -460,7 +468,7 @@ cluster_pd2: power-domain-cpu-cluster2 { =20 system_pd: power-domain-system { #power-domain-cells =3D <0>; - /* TODO: system-wide idle states */ + domain-idle-states =3D <&domain_ss3>; }; }; =20 --=20 2.43.0