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Mon, 25 May 2026 22:30:00 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb56b7920sm114088995ad.21.2026.05.25.22.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 22:30:00 -0700 (PDT) From: Taniya Das Date: Tue, 26 May 2026 10:59:44 +0530 Subject: [PATCH 1/4] clk: qcom: gcc-glymur: Move EVA clocks to critical clock list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260526-evacc_glymur-v1-1-b61c7755c403@oss.qualcomm.com> References: <20260526-evacc_glymur-v1-0-b61c7755c403@oss.qualcomm.com> In-Reply-To: <20260526-evacc_glymur-v1-0-b61c7755c403@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDA0NSBTYWx0ZWRfX+I/oXysGspCJ a4FofTJ5RoK02twPP6bDpu0QBdo0qDeVmeGgB5KQhJIkGUKpM1db7gWUR94vFCPifW1ItBFDHiF UI2XKo+dt6bIZSyBIKdGKmJVLoc9q0B3uAyMv5lIXeXY3Cdt7Q/5t77uGTWqvaC/rbOF/pKMa+b D7rlkKOpzlr9IAegjUDzx87UKgNPwe7iPjohgB8SpcuY1qgqSHSKWvdPZoUP2CLN6VVPS4eYZCR pjXgmeahjhhMzJ1QdAvDqIQ7mLyw69GR/u+SRWFeTU3ZjcqHtbtIU6vFZ6n5yTvUl++R7kF4LmI 0LzB2d5AHu9Jgh9QHGIhW6vXrJmD1TBVPiM05CyI74NdQJ0yV6O+PswIcYYpeZkqFoUPfCPYWhk fs0Mdm7b1khwyBl9xTeAqWoYxZM/pc8AfwJAfnn8eB4jH2fZwH+F7tClhfPcVC01rMSg9O2MkQB bl88H0HWfxoFYffmhjQ== X-Proofpoint-GUID: TjhZLIq2Lx8TUZCKLiezX73NLTEIBAH1 X-Proofpoint-ORIG-GUID: TjhZLIq2Lx8TUZCKLiezX73NLTEIBAH1 X-Authority-Analysis: v=2.4 cv=XqTK/1F9 c=1 sm=1 tr=0 ts=6a152fd9 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=6SqLyIFWvb7f5ISMJ2QA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-26_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605260045 The gcc_eva_ahb_clk and gcc_eva_xo_clk branch clocks should not be registered as standalone GCC branch clocks. Drop these clocks from the GCC clock list and instead add their CBCR registers to the GCC critical clocks list to ensure they remain enabled during early boot. Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controll= er") Signed-off-by: Taniya Das --- drivers/clk/qcom/gcc-glymur.c | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gcc-glymur.c b/drivers/clk/qcom/gcc-glymur.c index 2736465efdea9b3cf9ec945107d4b002e123b59f..32d23bdc819b7a62472f2a1ad23= c9c8a66cfd0d1 100644 --- a/drivers/clk/qcom/gcc-glymur.c +++ b/drivers/clk/qcom/gcc-glymur.c @@ -3669,21 +3669,6 @@ static struct clk_branch gcc_disp_hf_axi_clk =3D { }, }; =20 -static struct clk_branch gcc_eva_ahb_clk =3D { - .halt_reg =3D 0x9b004, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x9b004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x9b004, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "gcc_eva_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_eva_axi0_clk =3D { .halt_reg =3D 0x9b008, .halt_check =3D BRANCH_HALT_SKIP, @@ -3714,19 +3699,6 @@ static struct clk_branch gcc_eva_axi0c_clk =3D { }, }; =20 -static struct clk_branch gcc_eva_xo_clk =3D { - .halt_reg =3D 0x9b024, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x9b024, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "gcc_eva_xo_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk =3D { .halt_reg =3D 0x64000, .halt_check =3D BRANCH_HALT, @@ -7993,10 +7965,8 @@ static struct clk_regmap *gcc_glymur_clocks[] =3D { [GCC_CFG_NOC_USB_ANOC_AHB_CLK] =3D &gcc_cfg_noc_usb_anoc_ahb_clk.clkr, [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] =3D &gcc_cfg_noc_usb_anoc_south_ahb_= clk.clkr, [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, - [GCC_EVA_AHB_CLK] =3D &gcc_eva_ahb_clk.clkr, [GCC_EVA_AXI0_CLK] =3D &gcc_eva_axi0_clk.clkr, [GCC_EVA_AXI0C_CLK] =3D &gcc_eva_axi0c_clk.clkr, - [GCC_EVA_XO_CLK] =3D &gcc_eva_xo_clk.clkr, [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, @@ -8545,6 +8515,8 @@ static const u32 gcc_glymur_critical_cbcrs[] =3D { 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 0x32004, /* GCC_VIDEO_AHB_CLK */ 0x32058, /* GCC_VIDEO_XO_CLK */ + 0x9b004, /* GCC_EVA_AHB_CLK */ + 0x9b024, /* GCC_EVA_XO_CLK */ }; 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Mon, 25 May 2026 22:30:05 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb56b7920sm114088995ad.21.2026.05.25.22.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 22:30:05 -0700 (PDT) From: Taniya Das Date: Tue, 26 May 2026 10:59:45 +0530 Subject: [PATCH 2/4] dt-bindings: clock: qcom: Add EVA clock and reset controller for Glymur SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260526-evacc_glymur-v1-2-b61c7755c403@oss.qualcomm.com> References: <20260526-evacc_glymur-v1-0-b61c7755c403@oss.qualcomm.com> In-Reply-To: <20260526-evacc_glymur-v1-0-b61c7755c403@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDA0NSBTYWx0ZWRfX4Zbl5bl9FKDC j75/YYVxRUpTqisexWD+Bl/5qgg9HtvHdorGYZq1JXUHBDji9/9mL/L8sL8OFD9UfD4FVHYroWF 6czTblXMqygDLVjEBLHbCrlHkkUawjHLhQZnLMwRQjEVnh+UXOKly8BqsMM4ioYKP4KQGddkn7c FCJaMAAK0u+Q8Ux9tpVG/6DiaBQsoVJuUUS2Fpvp/4HzR17jUHCmMK6d5TSU+7va9q+++beJE1s qQw+S74A58L+fGJn/miTe9gpfPowi4DEzOe17C6OZSXm7QftzwvTkHzX0A9O83y8wu4KjE1pgt2 fHWKzskXPkafnUdvOizXhG1Ax+qds9Gx8CwScxJSHV+O9f/ONa0hyhlFtBEDS05y9NU9NW5/wGz vH8lnPrrrp+1QreKYMl6Ax2RNBw48DlqDs9FqhkRztMkMgPLskWY3GOu3lP30+PKC3B+K9aIbf8 X2OaXJLwc9oO6ToDfrQ== X-Proofpoint-GUID: HO1OPRIfr9DjiFVNmmOVcvXn2gzW-Pyx X-Proofpoint-ORIG-GUID: HO1OPRIfr9DjiFVNmmOVcvXn2gzW-Pyx X-Authority-Analysis: v=2.4 cv=XqTK/1F9 c=1 sm=1 tr=0 ts=6a152fdf cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=QUVFY6MdtzYYwQCb-hMA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-26_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605260045 Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Signed-off-by: Taniya Das Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/qcom,glymur-evacc.yaml | 76 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,glymur-evacc.h | 38 +++++++++++ 2 files changed, 114 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml= b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8315e3ce82ecfefb5413ce1c428= 43adb0bce50d7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-evacc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm EVA Clock & Reset Controller on Glymur SoC + +maintainers: + - Taniya Das + +description: | + Qualcomm EVA clock control module which supports the clocks, resets and + power domains for the EVA instances on Glymur SoC. + + See also: + - include/dt-bindings/clock/qcom,glymur-evacc.h + +properties: + compatible: + const: qcom,glymur-evacc + + clocks: + items: + - description: Interface clock from GCC + - description: Board XO source + - description: Board XO_A source + - description: Sleep clock source + + power-domains: + description: + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain + + required-opps: + description: + Required OPP nodes for the MMCX and MXC power domains. + items: + - description: MMCX performance point + - description: MXC performance point + +required: + - compatible + - clocks + - power-domains + - required-opps + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ab00000 { + compatible =3D "qcom,glymur-evacc"; + reg =3D <0x0ab00000 0x10000>; + clocks =3D <&gcc GCC_EVA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,glymur-evacc.h b/include/dt-bin= dings/clock/qcom,glymur-evacc.h new file mode 100644 index 0000000000000000000000000000000000000000..35a7b4550351661bdb1f7bdfbee= c625fafdfcef7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-evacc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H + +/* EVA_CC clocks */ +#define EVA_CC_AHB_CLK 0 +#define EVA_CC_AHB_CLK_SRC 1 +#define EVA_CC_MVS0_CLK 2 +#define EVA_CC_MVS0_CLK_SRC 3 +#define EVA_CC_MVS0_DIV_CLK_SRC 4 +#define EVA_CC_MVS0_FREERUN_CLK 5 +#define EVA_CC_MVS0_SHIFT_CLK 6 +#define EVA_CC_MVS0C_CLK 7 +#define EVA_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define EVA_CC_MVS0C_FREERUN_CLK 9 +#define EVA_CC_MVS0C_SHIFT_CLK 10 +#define EVA_CC_PLL0 11 +#define EVA_CC_SLEEP_CLK 12 +#define EVA_CC_SLEEP_CLK_SRC 13 +#define EVA_CC_XO_CLK 14 +#define EVA_CC_XO_CLK_SRC 15 + +/* EVA_CC power domains */ +#define EVA_CC_MVS0_GDSC 0 +#define EVA_CC_MVS0C_GDSC 1 + +/* EVA_CC resets */ +#define EVA_CC_INTERFACE_BCR 0 +#define EVA_CC_MVS0_BCR 1 +#define EVA_CC_MVS0C_CLK_ARES 2 +#define EVA_CC_MVS0C_BCR 3 +#define EVA_CC_MVS0C_FREERUN_CLK_ARES 4 + +#endif /* _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H */ --=20 2.34.1 From nobody Mon Jun 8 22:54:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19D583BF699 for ; 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Mon, 25 May 2026 22:30:11 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb56b7920sm114088995ad.21.2026.05.25.22.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 22:30:10 -0700 (PDT) From: Taniya Das Date: Tue, 26 May 2026 10:59:46 +0530 Subject: [PATCH 3/4] clk: qcom: Add EVA clock controller driver for Glymur SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260526-evacc_glymur-v1-3-b61c7755c403@oss.qualcomm.com> References: <20260526-evacc_glymur-v1-0-b61c7755c403@oss.qualcomm.com> In-Reply-To: <20260526-evacc_glymur-v1-0-b61c7755c403@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=Vd3H+lp9 c=1 sm=1 tr=0 ts=6a152fe6 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=mU7vPRoAUwN6OPuHNRcA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: aUICKdkqRrmTto-mx4wN7L4qsiM73b0o X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDA0NSBTYWx0ZWRfX8+mYtfU1pH6Q zSgbxrZdAj9uAl4nursV63ADlasOEPV9VwwuUMkGEzoCedPzTPswhfA+wtNgqWY8Z8mWf51RJMV VYtRZkZX0uivHfbIxhdP9PJefqsNs1DVCAISek+9Ag+dMdwuxeSERW+xmJcGlnAqKQRUDw9YCXB 1IKewuGxoVZPO0Bjew2r8ZPh0ESrh8A+e+51PIpHGMak4ne5FBFd67XCFdCJm0LYGPRrNH3RQ8R kRFZ970gMSTTSFTquNuzpVOlxM4UDWPG/8WqtYBRk+tviyRuPhyyVwchYgcjpEtEPgW+bu+3+pO 0HstXONWZly893uoNyvB8C30Wsi1t6eaWA9NTiJFsEGLakIHi/d1ACwc2dj1Tg8tZ55RPY8Dl8/ 7rdaDgiaByHVv1Svw3003eg95zJGw+Tw6BRFnrz9X0G3oa3c37P9c21HeWXyb1J4f6+cqIvpmTj fvuH0nPJazSFJdXbQ/g== X-Proofpoint-ORIG-GUID: aUICKdkqRrmTto-mx4wN7L4qsiM73b0o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-26_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 adultscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605260045 Add the Enhanced Video Analytics (EVA) clock controller driver for the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs and resets for the EVA subsystem which handles vision processing workloads. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/evacc-glymur.c | 453 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 465 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d9cff5b0281d8cc373b8ab14683370cb9b7f8bf3..94378d435162799aa866689377e= 4a9f1e96ab138 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,6 +55,17 @@ config CLK_GLYMUR_DISPCC Say Y if you want to support display devices and functionality such as splash screen. =20 +config CLK_GLYMUR_EVACC + tristate "Glymur EVA Clock Controller" + depends on ARM64 || COMPILE_TEST + default m if ARCH_QCOM + select CLK_GLYMUR_GCC + help + Support for the Enhanced Video Analytics (EVA) clock controller on + Qualcomm Technologies, Inc. Glymur devices. + Say Y if you want to support EVA devices and functionality such as + vision processing. + config CLK_GLYMUR_GCC tristate "Glymur Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e100cfd6a52de9f88f11720d9c2043db5e553618..74761f2c767d9ce5988fedf539d= 80dc1393b4617 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o obj-$(CONFIG_CLK_ELIZA_TCSRCC) +=3D tcsrcc-eliza.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o +obj-$(CONFIG_CLK_GLYMUR_EVACC) +=3D evacc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GPUCC) +=3D gpucc-glymur.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o diff --git a/drivers/clk/qcom/evacc-glymur.c b/drivers/clk/qcom/evacc-glymu= r.c new file mode 100644 index 0000000000000000000000000000000000000000..eab43ba922f37067d75645c860e= ce0ccfb9193b5 --- /dev/null +++ b/drivers/clk/qcom/evacc-glymur.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_AHB_CLK, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_EVA_CC_PLL0_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco taycan_eko_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 840.0 MHz Configuration */ +static const struct alpha_pll_config eva_cc_pll0_config =3D { + .l =3D 0x2b, + .alpha =3D 0xc000, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll eva_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &eva_cc_pll0_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct parent_map eva_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data eva_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map eva_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_EVA_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data eva_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &eva_cc_pll0.clkr.hw }, +}; + +static const struct parent_map eva_cc_parent_map_2[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data eva_cc_parent_data_2[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_eva_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 eva_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D eva_cc_parent_map_0, + .freq_tbl =3D ftbl_eva_cc_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_ahb_clk_src", + .parent_data =3D eva_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(eva_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_eva_cc_mvs0_clk_src[] =3D { + F(840000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1050000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1350000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1500000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1650000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 eva_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D eva_cc_parent_map_1, + .freq_tbl =3D ftbl_eva_cc_mvs0_clk_src, + .hw_clk_ctrl =3D true, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0_clk_src", + .parent_data =3D eva_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(eva_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_eva_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 eva_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x80e0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D eva_cc_parent_map_2, + .freq_tbl =3D ftbl_eva_cc_sleep_clk_src, + .hw_clk_ctrl =3D true, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_sleep_clk_src", + .parent_data =3D eva_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(eva_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_rcg2 eva_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x80bc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D eva_cc_parent_map_0, + .freq_tbl =3D ftbl_eva_cc_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_xo_clk_src", + .parent_data =3D eva_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(eva_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, + }, +}; + +static struct clk_regmap_div eva_cc_mvs0_div_clk_src =3D { + .reg =3D 0x809c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &eva_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div eva_cc_mvs0c_div2_div_clk_src =3D { + .reg =3D 0x8060, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &eva_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch eva_cc_mvs0_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x807c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &eva_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0_freerun_clk =3D { + .halt_reg =3D 0x808c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x808c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &eva_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x80d8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &eva_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0c_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &eva_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0c_freerun_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0c_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &eva_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch eva_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x80dc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80dc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "eva_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &eva_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc eva_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x8034, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "eva_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc eva_cc_mvs0_gdsc =3D { + .gdscr =3D 0x8068, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "eva_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &eva_cc_mvs0c_gdsc.pd, +}; + +static struct clk_regmap *eva_cc_glymur_clocks[] =3D { + [EVA_CC_AHB_CLK_SRC] =3D &eva_cc_ahb_clk_src.clkr, + [EVA_CC_MVS0_CLK] =3D &eva_cc_mvs0_clk.clkr, + [EVA_CC_MVS0_CLK_SRC] =3D &eva_cc_mvs0_clk_src.clkr, + [EVA_CC_MVS0_DIV_CLK_SRC] =3D &eva_cc_mvs0_div_clk_src.clkr, + [EVA_CC_MVS0_FREERUN_CLK] =3D &eva_cc_mvs0_freerun_clk.clkr, + [EVA_CC_MVS0_SHIFT_CLK] =3D &eva_cc_mvs0_shift_clk.clkr, + [EVA_CC_MVS0C_CLK] =3D &eva_cc_mvs0c_clk.clkr, + [EVA_CC_MVS0C_DIV2_DIV_CLK_SRC] =3D &eva_cc_mvs0c_div2_div_clk_src.clkr, + [EVA_CC_MVS0C_FREERUN_CLK] =3D &eva_cc_mvs0c_freerun_clk.clkr, + [EVA_CC_MVS0C_SHIFT_CLK] =3D &eva_cc_mvs0c_shift_clk.clkr, + [EVA_CC_PLL0] =3D &eva_cc_pll0.clkr, + [EVA_CC_SLEEP_CLK_SRC] =3D &eva_cc_sleep_clk_src.clkr, + [EVA_CC_XO_CLK_SRC] =3D &eva_cc_xo_clk_src.clkr, +}; + +static struct gdsc *eva_cc_glymur_gdscs[] =3D { + [EVA_CC_MVS0_GDSC] =3D &eva_cc_mvs0_gdsc, + [EVA_CC_MVS0C_GDSC] =3D &eva_cc_mvs0c_gdsc, +}; + +static const struct qcom_reset_map eva_cc_glymur_resets[] =3D { + [EVA_CC_INTERFACE_BCR] =3D { 0x80a0 }, + [EVA_CC_MVS0_BCR] =3D { 0x8064 }, + [EVA_CC_MVS0C_CLK_ARES] =3D { 0x804c, 2 }, + [EVA_CC_MVS0C_BCR] =3D { 0x8030 }, + [EVA_CC_MVS0C_FREERUN_CLK_ARES] =3D { 0x805c, 2 }, +}; + +static struct clk_alpha_pll *eva_cc_glymur_plls[] =3D { + &eva_cc_pll0, +}; + +static const u32 eva_cc_glymur_critical_cbcrs[] =3D { + 0x80a4, /* EVA_CC_AHB_CLK */ + 0x80f8, /* EVA_CC_SLEEP_CLK */ + 0x80d4, /* EVA_CC_XO_CLK */ +}; + +static const struct regmap_config eva_cc_glymur_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9f50, + .fast_io =3D true, +}; + +static void clk_glymur_regs_configure(struct device *dev, struct regmap *r= egmap) +{ + /* Update CTRL_IN register */ + regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0)); +} + +static const struct qcom_cc_driver_data eva_cc_glymur_driver_data =3D { + .alpha_plls =3D eva_cc_glymur_plls, + .num_alpha_plls =3D ARRAY_SIZE(eva_cc_glymur_plls), + .clk_cbcrs =3D eva_cc_glymur_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(eva_cc_glymur_critical_cbcrs), + .clk_regs_configure =3D clk_glymur_regs_configure, +}; + +static const struct qcom_cc_desc eva_cc_glymur_desc =3D { + .config =3D &eva_cc_glymur_regmap_config, + .clks =3D eva_cc_glymur_clocks, + .num_clks =3D ARRAY_SIZE(eva_cc_glymur_clocks), + .resets =3D eva_cc_glymur_resets, + .num_resets =3D ARRAY_SIZE(eva_cc_glymur_resets), + .gdscs =3D eva_cc_glymur_gdscs, + .num_gdscs =3D ARRAY_SIZE(eva_cc_glymur_gdscs), + .use_rpm =3D true, + .driver_data =3D &eva_cc_glymur_driver_data, +}; + +static const struct of_device_id eva_cc_glymur_match_table[] =3D { + { .compatible =3D "qcom,glymur-evacc" }, + { } +}; +MODULE_DEVICE_TABLE(of, eva_cc_glymur_match_table); + +static int eva_cc_glymur_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &eva_cc_glymur_desc); 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Mon, 25 May 2026 22:30:17 -0700 (PDT) X-Received: by 2002:a17:902:e548:b0:2bd:4d97:b5bb with SMTP id d9443c01a7336-2beb0385f86mr195646035ad.12.1779773416724; Mon, 25 May 2026 22:30:16 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb56b7920sm114088995ad.21.2026.05.25.22.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 22:30:16 -0700 (PDT) From: Taniya Das Date: Tue, 26 May 2026 10:59:47 +0530 Subject: [PATCH 4/4] arm64: dts: qcom: glymur: Add EVA clock controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260526-evacc_glymur-v1-4-b61c7755c403@oss.qualcomm.com> References: <20260526-evacc_glymur-v1-0-b61c7755c403@oss.qualcomm.com> In-Reply-To: <20260526-evacc_glymur-v1-0-b61c7755c403@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Konrad Dybcio , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=dtfrzVg4 c=1 sm=1 tr=0 ts=6a152fe9 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=Juf6bUmjuD87IqhQNpkA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: fQkPZSr91Lt0eu8f5ZkZ0OKvmbcbGJsm X-Proofpoint-ORIG-GUID: fQkPZSr91Lt0eu8f5ZkZ0OKvmbcbGJsm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDA0NSBTYWx0ZWRfX4qAk4kwihkDV IkrPXl4LOU6fJxHJTdUi01hr543jyFgInASKyvY34rCYDRnqbr0ya7TjEAaAxKP8j7ZlvwYGbw8 +F8ew8oN3sG9i7DQJGoChe1Ay5HXXaVY+/0CJn5W93xWJxJRnwX/d5Z/hvQuoZqzkTcO3Zrxz9R Ghe6a3stzYtCpV25UNCDa+obd65Kb//9wXxu8VV41fJB85qNRZ1QDfDV8vvlkYg73pRJXk+wrMz +Xqcrff9nJjt5v543vhrD0r4NE6UWU3P7dOH/RT5wv/OT1OZvdtP152IhA7xpQLLbw8Xq1SzgTx 5dBXgmulI9bK4A4t/LYpDVt5jSDqmbDXQCZm5LMSqHUuRzaHusX0UuIs/rnJ/bGEzPqJ8ZleXI5 sLycfilWN8RZzjetMNHUJXEyWB6iw2rvVhL6ibVH2McECdpOyHhH8KRbsFlKRaQtUP9aL/+ORxd FFqleo+R98SIIih3TxA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-26_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605260045 Add the device node for the EVA clock controller (evacc) for Qualcomm Glymur SoC. The EVACC provides clocks and resets to the EVA hardware block. Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/glymur.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index 20b49af7298e9549d126aa50a0dc7a90943a3249..66948808d197bd17ffe65190b47= 2bb845cba0eb8 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -4804,6 +4805,24 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + evacc: clock-controller@abf0000 { + compatible =3D "qcom,glymur-evacc"; + reg =3D <0x0 0x0abf0000 0x0 0x10000>; + clocks =3D <&gcc GCC_EVA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,glymur-dispcc"; reg =3D <0x0 0x0af00000 0x0 0x20000>; --=20 2.34.1