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Mon, 25 May 2026 15:04:57 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d:7285:c2ff:fe45:8a32]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84164b0963asm10065750b3a.25.2026.05.25.15.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 15:04:57 -0700 (PDT) From: Rosen Penev To: linux-mtd@lists.infradead.org Cc: Manivannan Sadhasivam , linusw@kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-arm-msm@vger.kernel.org (open list:QUALCOMM NAND CONTROLLER DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH] mtd: rawnand: qcom: embed nand_controller into qcom_nand_controller Date: Mon, 25 May 2026 15:04:40 -0700 Message-ID: <20260525220440.94639-1-rosenp@gmail.com> X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The qcom_nand_controller had a struct nand_controller *controller pointer that was assigned to (struct nand_controller *)&nandc[1], with the allocation oversized by sizeof(*controller) to make room. get_qcom_nand_controller() then walked backwards from chip->controller using sizeof()-based arithmetic to recover the enclosing nandc. Embed the nand_controller directly into qcom_nand_controller and use container_of() in get_qcom_nand_controller(). The header now needs the full rawnand.h definition rather than a forward declaration. Assisted-by: Claude:Opus-4.7 Signed-off-by: Rosen Penev --- drivers/mtd/nand/raw/qcom_nandc.c | 16 ++++++---------- include/linux/mtd/nand-qpic-common.h | 4 +++- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_= nandc.c index b7e79b76654d..4b80ce084d9a 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -128,8 +128,8 @@ static struct qcom_nand_host *to_qcom_nand_host(struct = nand_chip *chip) static struct qcom_nand_controller * get_qcom_nand_controller(struct nand_chip *chip) { - return (struct qcom_nand_controller *) - ((u8 *)chip->controller - sizeof(struct qcom_nand_controller)); + return container_of(chip->controller, struct qcom_nand_controller, + controller); } =20 static u32 nandc_read(struct qcom_nand_controller *nandc, int offset) @@ -2034,8 +2034,8 @@ static int qcom_nandc_setup(struct qcom_nand_controll= er *nandc) { u32 nand_ctrl; =20 - nand_controller_init(nandc->controller); - nandc->controller->ops =3D &qcom_nandc_ops; + nand_controller_init(&nandc->controller); + nandc->controller.ops =3D &qcom_nandc_ops; =20 /* kill onenand */ if (!nandc->props->nandc_part_of_qpic) @@ -2175,7 +2175,7 @@ static int qcom_nand_host_init_and_register(struct qc= om_nand_controller *nandc, chip->legacy.block_bad =3D qcom_nandc_block_bad; chip->legacy.block_markbad =3D qcom_nandc_block_markbad; =20 - chip->controller =3D nandc->controller; + chip->controller =3D &nandc->controller; chip->options |=3D NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA | NAND_SKIP_BBTSCAN; =20 @@ -2256,21 +2256,17 @@ static int qcom_nandc_parse_dt(struct platform_devi= ce *pdev) static int qcom_nandc_probe(struct platform_device *pdev) { struct qcom_nand_controller *nandc; - struct nand_controller *controller; const void *dev_data; struct device *dev =3D &pdev->dev; struct resource *res; int ret; =20 - nandc =3D devm_kzalloc(&pdev->dev, sizeof(*nandc) + sizeof(*controller), - GFP_KERNEL); + nandc =3D devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); if (!nandc) return -ENOMEM; - controller =3D (struct nand_controller *)&nandc[1]; =20 platform_set_drvdata(pdev, nandc); nandc->dev =3D dev; - nandc->controller =3D controller; =20 dev_data =3D of_device_get_match_data(dev); if (!dev_data) { diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-= qpic-common.h index e8201d1b7cf9..006ca8c978a9 100644 --- a/include/linux/mtd/nand-qpic-common.h +++ b/include/linux/mtd/nand-qpic-common.h @@ -9,6 +9,8 @@ #ifndef __MTD_NAND_QPIC_COMMON_H__ #define __MTD_NAND_QPIC_COMMON_H__ =20 +#include + /* NANDc reg offsets */ #define NAND_FLASH_CMD 0x00 #define NAND_ADDR0 0x04 @@ -394,7 +396,7 @@ struct qcom_nand_controller { =20 const struct qcom_nandc_props *props; =20 - struct nand_controller *controller; + struct nand_controller controller; struct qpic_spi_nand *qspi; struct list_head host_list; =20 --=20 2.54.0