From nobody Mon Jun 8 22:52:28 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEA303793D0 for ; Mon, 25 May 2026 18:43:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779734635; cv=none; b=Ewaz7A+Vo5dXPvZJJjZsbBtIow9zp2XnLjf1tR9CO7xK77rAzBoECPD7MqxtTjzpOvEZ6IsZ0YBalF+Lqt3Jo3rQcJpkENtyhcQ88lagkShorQKvERfUWeDJ5XzUiDM9lsj0gPm5KRWxTdWKtUO2bqouOXyhCH2kzeAH0KnLvBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779734635; c=relaxed/simple; bh=4rSy3o0s1t2X0KnAOSHjI7mBWu/hrM5yp05yahxxfi4=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=tdy582oQKHCYUhKIT82mYnOdnuoO6YS0ZXIg3Hw4msO1zHCqN5KaKdBGNs0PkXYAwIg1RFjzIZjfYrikSU6jEAWGUirXlWDhlLrBe8bbmZzne9mJYbyijanfBL7u6Jw0Eb4MA3hIWAk+A2UZ7Rb1pFT2tq1oOgfedElnkztleiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--praan.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=kL2y/zDJ; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--praan.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="kL2y/zDJ" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-367f715cbd0so9690276a91.0 for ; Mon, 25 May 2026 11:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1779734633; x=1780339433; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=U//oE56krJ8X0dzRdJlpBkAz8D7rzP/0SvFlnQu6n1U=; b=kL2y/zDJ6ZW2nmn2JEOd7oOVt/ya/6HQJ68z/THwPCNwIxD51nV1o1ojV4aTxJBVdP wFykh8gGhMlBM3z1T4Mnc/Pyh7gYxkKyjzf7jX3RLYHFUcvGz06AZaUZEJ5/23ndK8uI 4ADWxJZeSKvDGlnTct8EotKOm9n+WNHNMFgMA0auN4E2nPgg5F72maakOihLtRN6bXVR X5tIAQlgqw/AnREGYz0jD70u/zTpwFrrRauvQLepi2q/sL5NfWSfJ2PcRGehQ6LevWF+ KNiLc0n+/IZ3isnRXAbSsNWrgOerHH4TFYZk9Yi6FVYJl8rj6qhp3qPfQQ2B4NbMfmEV yiAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779734633; x=1780339433; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=U//oE56krJ8X0dzRdJlpBkAz8D7rzP/0SvFlnQu6n1U=; b=YfdMCq3SoDtdNDe3hI26qnfdDwkYJrfQ9CsluK2vS4X87y0anPCR/iT+VI8CtrEcmc c3kXQ2R8u2WSsCOd8W1TfbY1y+uH1kfshxzga7uczjLZGWghouT2zF9WPSW6PcQAgpnf ImFoR8QeU8w4hh1DOhnm90sTWuuM1GCaJDgCcx6z28tKqEmrkE+JKg+tomZCp/JHFP1S zntBXbKjKHDwdW7vu1AHw9M5hxpBMlntvykFLDqfuKJXQjcFGJ7ZGCWtqWqv9sT4wnUg RJzenXM5TevphcTb80mm8GJ9PPOfdEMwVRB0kSEJ1T3A1GY7FeMWPeg+cfEvb0kuIwSo sqhg== X-Forwarded-Encrypted: i=1; AFNElJ+MEBoxVY8X9WSmC5cY/I6gMT1JkAfIgKHQpg1blRIm9C3q0zNjTYAIMrwrPKgSmK6YrgPo6Q8O9UAovSk=@vger.kernel.org X-Gm-Message-State: AOJu0YzmmKBE2e4nrXj1l6QjNbE5TvnExUJcLpZMh/4/e05TtZiGVZO0 NnG34gDivCnxYX0F8xCDqVwQslLQ+TS467EcOaA18NoI08ST7czCaJH1wM49vaL77z6kGlLEiEQ DVg== X-Received: from pjob1.prod.google.com ([2002:a17:90a:8c81:b0:369:c5f0:e8f6]) (user=praan job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:57c8:b0:36a:f612:e695 with SMTP id 98e67ed59e1d1-36af612e947mr2150738a91.17.1779734632985; Mon, 25 May 2026 11:43:52 -0700 (PDT) Date: Mon, 25 May 2026 18:43:43 +0000 In-Reply-To: <20260525184347.4059549-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260525184347.4059549-1-praan@google.com> X-Mailer: git-send-email 2.54.0.746.g67dd491aae-goog Message-ID: <20260525184347.4059549-2-praan@google.com> Subject: [PATCH v4 1/5] PCI/ATS: Ensure pci_ats_supported() is PF-aware for VFs From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Bjorn Helgaas , David Woodhouse , Lu Baolu , Robin Murphy , Suravee Suthikulpanit , Jason Gunthorpe , Nicolin Chen , David Matlack , Samiullah Khawaja , Daniel Mentz , Pasha Tatashin , Mostafa Saleh , Pranjal Shrivastava , Jason Gunthorpe Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update pci_ats_supported() to additionally check the associated PF's status when called on a VF. This ensures that PF-level quirks and untrusted status are correctly propagated to VFs, providing a robust support check that aligns with the kernel's PF-centric ATS configuration model and is immune to the timing of VF-specific fixups. Reviewed-by: Jason Gunthorpe Reviewed-by: Samiullah Khawaja Signed-off-by: Pranjal Shrivastava Reviewed-by: Nicolin Chen --- drivers/pci/ats.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index ec6c8dbdc5e9..a5fa7745bce8 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -40,10 +40,13 @@ void pci_ats_init(struct pci_dev *dev) */ bool pci_ats_supported(struct pci_dev *dev) { - if (!dev->ats_cap) + if (!dev->ats_cap || dev->untrusted) return false; =20 - return (dev->untrusted =3D=3D 0); + if (dev->is_virtfn) + return pci_ats_supported(pci_physfn(dev)); + + return true; } EXPORT_SYMBOL_GPL(pci_ats_supported); =20 --=20 2.54.0.746.g67dd491aae-goog From nobody Mon Jun 8 22:52:28 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 835C537C0FA for ; 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Mon, 25 May 2026 11:43:55 -0700 (PDT) Date: Mon, 25 May 2026 18:43:44 +0000 In-Reply-To: <20260525184347.4059549-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260525184347.4059549-1-praan@google.com> X-Mailer: git-send-email 2.54.0.746.g67dd491aae-goog Message-ID: <20260525184347.4059549-3-praan@google.com> Subject: [PATCH v4 2/5] PCI/ATS: Validate STU for VFs in pci_prepare_ats() From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Bjorn Helgaas , David Woodhouse , Lu Baolu , Robin Murphy , Suravee Suthikulpanit , Jason Gunthorpe , Nicolin Chen , David Matlack , Samiullah Khawaja , Daniel Mentz , Pasha Tatashin , Mostafa Saleh , Pranjal Shrivastava , Jason Gunthorpe Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While every PCI Function that implements ATS has an independent ATS Extended Capability structure with a Read/Write Smallest Translation Unit (STU) field, the kernel manages SR-IOV ATS by requiring the IOMMU driver to configure the STU on the Physical Function (PF) before any any Virtual Functions (VFs) are created. Currently, pci_prepare_ats() bails out early for VFs, assuming that the PF has already been correctly prepared. However, this creates a potential mismatch if a VF is subsequently prepared with a different page shift. Update pci_prepare_ats() to validate that the requested page shift (ps) matches the STU already configured in the associated PF. This ensures early detection of incompatible configurations and maintains the kernel's policy of consistent STU sizing across all functions associated with a given SMMU. Reviewed-by: Jason Gunthorpe Reviewed-by: Samiullah Khawaja Signed-off-by: Pranjal Shrivastava Reviewed-by: Nicolin Chen --- drivers/pci/ats.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index a5fa7745bce8..54319854bfd8 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -73,8 +73,13 @@ int pci_prepare_ats(struct pci_dev *dev, int ps) if (ps < PCI_ATS_MIN_STU) return -EINVAL; =20 - if (dev->is_virtfn) + if (dev->is_virtfn) { + struct pci_dev *pdev =3D pci_physfn(dev); + + if (pdev->ats_stu !=3D ps) + return -EINVAL; return 0; + } =20 dev->ats_stu =3D ps; ctrl =3D PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); --=20 2.54.0.746.g67dd491aae-goog From nobody Mon Jun 8 22:52:28 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1E53379C3B for ; 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Mon, 25 May 2026 11:43:57 -0700 (PDT) Date: Mon, 25 May 2026 18:43:45 +0000 In-Reply-To: <20260525184347.4059549-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260525184347.4059549-1-praan@google.com> X-Mailer: git-send-email 2.54.0.746.g67dd491aae-goog Message-ID: <20260525184347.4059549-4-praan@google.com> Subject: [PATCH v4 3/5] iommu/arm-smmu-v3: Fix ATS state tracking From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Bjorn Helgaas , David Woodhouse , Lu Baolu , Robin Murphy , Suravee Suthikulpanit , Jason Gunthorpe , Nicolin Chen , David Matlack , Samiullah Khawaja , Daniel Mentz , Pasha Tatashin , Mostafa Saleh , Pranjal Shrivastava Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SMMUv3 driver currently has a two-phase commit in its ATS enablement flow. During arm_smmu_attach_prepare(), it predicts whether ATS will be enabled using arm_smmu_ats_supported() and accordingly increments nr_ats_masters and merges ATS invalidations into the domain's invs array. However, the actual hardware enablement via pci_enable_ats() happens later in arm_smmu_attach_commit(). If this call to pci_enable_ats fails, the SMMU driver's ATS state tracking remains polluted, i.e., the driver tracks ATS enabled on a master that is not actually using ATS. This leads to an incorrect nr_ats_masters and triggers a warning in the PCI core during detach: [ 127.925080] ------------[ cut here ]------------ [ 127.925084] WARNING: drivers/pci/ats.c:132 at pci_disable_ats+0x94/0xa8,= CPU#42: iova_stress/12240 [ 127.949761] Modules linked in: vfat fat dummy bridge stp llc cdc_ncm cdc= _eem cdc_ether usbnet mii xhci_pci xhci_hcd ehci_pci ehci_hcd [ 127.961760] CPU: 42 UID: 0 PID: 12240 Comm: iova_stress Not tainted 7.1.= 0-smp-DEV #4 PREEMPTLAZY [ 127.970619] Hardware name: [ 127.977655] pstate: 61400009 (nZCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE= =3D--) [ 127.984603] pc : pci_disable_ats+0x94/0xa8 [ 127.988687] lr : arm_smmu_attach_prepare+0x104/0x310 ... [ 128.068169] Call trace: [ 128.070603] pci_disable_ats+0x94/0xa8 (P) [ 128.074688] arm_smmu_attach_prepare+0x104/0x310 [ 128.079292] arm_smmu_attach_dev_ste+0x128/0x1e0 [ 128.083899] arm_smmu_attach_dev_blocked+0x50/0x88 [ 128.088677] __iommu_attach_device+0x30/0x138 [ 128.093026] __iommu_group_set_domain_internal+0xdc/0x228 [ 128.098412] __iommu_take_dma_ownership+0x118/0x150 [ 128.103278] iommu_group_claim_dma_owner+0x48/0x80 [ 128.108056] vfio_container_attach_group+0xc8/0x1b0 [ 128.112927] vfio_group_fops_unl_ioctl+0x578/0x968 [ 128.117706] __arm64_sys_ioctl+0x90/0xe8 The issue was exposed under heavy load when running a VFIO-based DMA map stress test (iova_stress). Fix this by ensuring that all failable ATS configuration happens early during device discovery. Update arm_smmu_probe_device() to call pci_prepare_ats() only if ATS is supported and fail the probe if pci_prepare_ats() returns an error, ensuring that any master that reaches the attach phase is guaranteed to have a valid ATS configuration. Additionally, update arm_smmu_enable_ats() to use the WARN() macro. Since earlier checks now preclude configuration-related failures, any failure during hardware enablement is a noisy kernel bug or fatal hardware error that should be reported with a backtrace while allowing the driver to continue in a balanced software state. Fixes: 7497f4211f4f ("iommu/arm-smmu-v3: Make changing domains be hitless f= or ATS") Signed-off-by: Pranjal Shrivastava --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index e8d7dbe495f0..1d96064d314b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3065,8 +3065,14 @@ static void arm_smmu_enable_ats(struct arm_smmu_mast= er *master) * ATC invalidation of PASID 0 causes the entire ATC to be flushed. */ arm_smmu_atc_inv_master(master, IOMMU_NO_PASID); - if (pci_enable_ats(pdev, stu)) - dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); + + /* + * Any failure at this point is a kernel bug. pci_ats_supported() + * and pci_prepare_ats() have already verified the hardware capability + * and programmed the STU. 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Mon, 25 May 2026 11:44:00 -0700 (PDT) Date: Mon, 25 May 2026 18:43:46 +0000 In-Reply-To: <20260525184347.4059549-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260525184347.4059549-1-praan@google.com> X-Mailer: git-send-email 2.54.0.746.g67dd491aae-goog Message-ID: <20260525184347.4059549-5-praan@google.com> Subject: [PATCH v4 4/5] iommu/vt-d: Fail probe on ATS configuration failure From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Bjorn Helgaas , David Woodhouse , Lu Baolu , Robin Murphy , Suravee Suthikulpanit , Jason Gunthorpe , Nicolin Chen , David Matlack , Samiullah Khawaja , Daniel Mentz , Pasha Tatashin , Mostafa Saleh , Pranjal Shrivastava Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the Intel VT-d driver to handle ATS configuration and enablement more strictly. Specifically, update the device probe to fail if pci_prepare_ats() returns an error. This ensures that any ATS-capable master reaching the attach phase is guaranteed to have a valid config. Additionally, update iommu_enable_pci_ats() to WARN() if pci_enable_ats fails. Since earlier checks in the probe phase preclude config-related failures, any failure during hardware enablement is considered a kernel bug. Signed-off-by: Pranjal Shrivastava --- drivers/iommu/intel/iommu.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 4d0e65bc131d..22308e4911e1 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -873,8 +873,14 @@ static void iommu_enable_pci_ats(struct device_domain_= info *info) if (!pci_ats_page_aligned(pdev)) return; =20 - if (!pci_enable_ats(pdev, VTD_PAGE_SHIFT)) - info->ats_enabled =3D 1; + /* + * pci_enable_ats() should not fail here because earlier checks + * have already verified support and configuration. + */ + if (WARN_ON(pci_enable_ats(pdev, VTD_PAGE_SHIFT))) + return; + + info->ats_enabled =3D 1; } =20 static void iommu_disable_pci_ats(struct device_domain_info *info) @@ -3288,7 +3294,10 @@ static struct iommu_device *intel_iommu_probe_device= (struct device *dev) =20 dev_iommu_priv_set(dev, info); if (pdev && pci_ats_supported(pdev)) { - pci_prepare_ats(pdev, VTD_PAGE_SHIFT); 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charset="utf-8" Update the AMD IOMMU driver to handle ATS configuration and enablement more strictly. Specifically, update the device probe to fail if pci_prepare_ats() returns an error. This ensures that any ATS-capable master reaching the attach phase is guaranteed to have a valid config. Additionally, update pdev_enable_cap_ats() to WARN_ON() if pci_enable_ats fails. Since earlier checks in the probe phase preclude config-related failures, any failure during hardware enablement is considered a kernel bug. Signed-off-by: Pranjal Shrivastava --- drivers/iommu/amd/iommu.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 84cad43dc188..1dddb08e7b22 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -570,10 +570,16 @@ static inline int pdev_enable_cap_ats(struct pci_dev = *pdev) if (amd_iommu_iotlb_sup && (dev_data->flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP)) { ret =3D pci_enable_ats(pdev, PAGE_SHIFT); - if (!ret) { - dev_data->ats_enabled =3D 1; - dev_data->ats_qdep =3D pci_ats_queue_depth(pdev); - } + /* + * pci_enable_ats() should not fail here because earlier checks + * have already verified support and configuration. + */ + if (WARN_ON(ret)) + return ret; + + dev_data->ats_enabled =3D 1; + dev_data->ats_qdep =3D pci_ats_queue_depth(pdev); + ret =3D 0; } =20 return ret; @@ -2502,8 +2508,17 @@ static struct iommu_device *amd_iommu_probe_device(s= truct device *dev) else dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_512; =20 - if (dev_is_pci(dev)) - pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT); + if (dev_is_pci(dev)) { + struct pci_dev *pdev =3D to_pci_dev(dev); + + if (pci_ats_supported(pdev)) { + ret =3D pci_prepare_ats(pdev, PAGE_SHIFT); + if (ret) { + iommu_dev =3D ERR_PTR(ret); + goto out_err; + } + } + } =20 out_err: return iommu_dev; --=20 2.54.0.746.g67dd491aae-goog