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charset="utf-8" Some peripherals on RZ/G3E SoCs (SSIU, SPDIF, SCU/SRC, DVC) require explicit ACK signal routing through the ICU via the ICU_DMACKSELk registers for level-based DMA handshaking. Add rzv2h_icu_register_dma_ack() to configure ICU_DMACKSELk, routing a DMAC channel's ACK signal to the specified peripheral. Signed-off-by: John Madieu Acked-by: Thomas Gleixner --- Changes: v4: No changes v3: No changes v2: No changes drivers/irqchip/irq-renesas-rzv2h.c | 40 +++++++++++++++++++++++ include/linux/irqchip/irq-renesas-rzv2h.h | 5 +++ 2 files changed, 45 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 31c543c876b1..971ac83eee90 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -151,6 +151,12 @@ struct rzv2h_hw_info { #define ICU_DMAC_PREP_DMAREQ(sel, up) (FIELD_PREP(ICU_DMAC_DkRQ_SEL_MASK,= (sel)) \ << ICU_DMAC_DMAREQ_SHIFT(up)) =20 +/* DMAC ACK routing - 4 x 7-bit fields per 32-bit register, 8-bit spacing = */ +#define ICU_DMAC_DACK_SEL_MASK GENMASK(6, 0) +#define ICU_DMAC_DACK_SHIFT(n) ((n) * 8) +#define ICU_DMAC_DACK_FIELD_MASK(n) (ICU_DMAC_DACK_SEL_MASK << ICU_DMAC_D= ACK_SHIFT(n)) +#define ICU_DMAC_PREP_DACK(val, n) (((val) & ICU_DMAC_DACK_SEL_MASK) << I= CU_DMAC_DACK_SHIFT(n)) + /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data = structure. * @base: Controller's base address @@ -188,6 +194,40 @@ void rzv2h_icu_register_dma_req(struct platform_device= *icu_dev, u8 dmac_index, } EXPORT_SYMBOL_GPL(rzv2h_icu_register_dma_req); =20 +/** + * rzv2h_icu_register_dma_ack - Configure DMA ACK signal routing + * @icu_dev: ICU platform device + * @dmac_index: DMAC instance index (0-4) + * @dmac_channel: DMAC channel number (0-15), or RZV2H_ICU_DMAC_ACK_NO_DEF= AULT + * to disconnect routing for a given ack_no + * @ack_no: Peripheral ACK number (0-88) per RZ/G3E manual Table 4.6= -28, + * used as index into ICU_DMACKSELk + * + * Routes the ACK signal of the peripheral identified by @ack_no to DMAC + * channel @dmac_channel of instance @dmac_index. When @dmac_channel is + * RZV2H_ICU_DMAC_ACK_NO_DEFAULT the field is reset, disconnecting any + * previously configured routing for that peripheral. + */ +void rzv2h_icu_register_dma_ack(struct platform_device *icu_dev, u8 dmac_i= ndex, + u8 dmac_channel, u16 ack_no) +{ + struct rzv2h_icu_priv *priv =3D platform_get_drvdata(icu_dev); + u8 reg_idx =3D ack_no / 4; + u8 field_idx =3D ack_no & 0x3; + u8 dmac_ack_src =3D (dmac_channel =3D=3D RZV2H_ICU_DMAC_ACK_NO_DEFAULT) ? + RZV2H_ICU_DMAC_ACK_NO_DEFAULT : + (dmac_index * 16 + dmac_channel); + u32 val; + + guard(raw_spinlock_irqsave)(&priv->lock); + + val =3D readl(priv->base + ICU_DMACKSELk(reg_idx)); + val &=3D ~ICU_DMAC_DACK_FIELD_MASK(field_idx); + val |=3D ICU_DMAC_PREP_DACK(dmac_ack_src, field_idx); + writel(val, priv->base + ICU_DMACKSELk(reg_idx)); +} +EXPORT_SYMBOL_GPL(rzv2h_icu_register_dma_ack); + static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *dat= a) { return data->domain->host_data; diff --git a/include/linux/irqchip/irq-renesas-rzv2h.h b/include/linux/irqc= hip/irq-renesas-rzv2h.h index 618a60d2eac0..4ffa898eaaf2 100644 --- a/include/linux/irqchip/irq-renesas-rzv2h.h +++ b/include/linux/irqchip/irq-renesas-rzv2h.h @@ -11,13 +11,18 @@ #include =20 #define RZV2H_ICU_DMAC_REQ_NO_DEFAULT 0x3ff +#define RZV2H_ICU_DMAC_ACK_NO_DEFAULT 0x7f =20 #ifdef CONFIG_RENESAS_RZV2H_ICU void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_i= ndex, u8 dmac_channel, u16 req_no); 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Mon, 25 May 2026 11:08:56 +0000 From: John Madieu To: vkoul@kernel.org, tglx@kernel.org Cc: Frank.Li@kernel.org, claudiu.beznea.uj@bp.renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, cosmin-gabriel.tanislav.xa@renesas.com, john.madieu.xa@bp.renesas.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, john.madieu@gmail.com Subject: [PATCH v4 2/2] dma: sh: rz-dmac: Add DMA ACK signal routing support Date: Mon, 25 May 2026 11:07:50 +0000 Message-Id: <20260525110750.4020112-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260525110750.4020112-1-john.madieu.xa@bp.renesas.com> References: <20260525110750.4020112-1-john.madieu.xa@bp.renesas.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: PR1P264CA0152.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:346::10) To TY6PR01MB17377.jpnprd01.prod.outlook.com (2603:1096:405:35b::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY6PR01MB17377:EE_|OSZPR01MB8484:EE_ X-MS-Office365-Filtering-Correlation-Id: 5fdaec68-7c90-4d56-3433-08deba4e03c0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|52116014|11063799006|5023799004|56012099003|18002099003|22082099003|38350700014; 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charset="utf-8" Some peripherals on RZ/G3E SoCs (SSIU, SPDIF, SCU/SRC, DVC, PFC) require explicit ACK signal routing through the ICU for level-based DMA handshaking. Rather than extending the DT binding with an optional second #dma-cells (which would require all DMA consumers to supply two cells even when ACK routing is not needed), derive the ACK signal number directly from the MID/RID request number using the linear mapping defined in RZ/G3E hardware manual Table 4.6-28: PFC external DMA pins (DREQ0..DREQ4): req_no 0x000-0x004 -> ACK No. 84-88 SSIU BUSIFs (ssip00..ssip93): req_no 0x161-0x198 -> ACK No. 28-83 SPDIF (CH0..CH2) + SCU SRC (sr0..sr9) + DVC (cmd0..cmd1): req_no 0x199-0x1b4 -> ACK No. 0-27 ACK routing is programmed when a channel is prepared for transfer and cleared when the channel is released or the transfer times out, following the same pattern as MID/RID request routing. Signed-off-by: John Madieu --- Changes: v4: - Rebased on top of Claudiu Beznea's updated rz-dmac series. The rebased base reworks rz_dmac_resume() and now re-programs the DMA request routing itself (rz_dmac_set_dma_req_no()), so this patch no longer needs to add that call there. The patch still adds the rz_dmac_set_dma_ack_no() call in rz_dmac_resume(); resume() thus continues to restore both the request and the ACK routing, the request call now coming from the dependency. No other code changes. v3: No changes v2: - Drop DMA ACK second cell from DT specifier - Derive ACK signal number in-driver from MID/RID using arithmetic formulas per ICU Table 4.6-28 (3 linear peripheral groups) drivers/dma/sh/rz-dmac.c | 69 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 19095a5492bc..f6346f31096c 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -93,6 +93,7 @@ struct rz_dmac_chan { u32 chcfg; u32 chctrl; int mid_rid; + int dmac_ack; =20 struct { u32 nxla; @@ -118,6 +119,9 @@ struct rz_dmac_icu { struct rz_dmac_info { void (*icu_register_dma_req)(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel, u16 req_no); + void (*icu_register_dma_ack)(struct platform_device *icu_dev, + u8 dmac_index, u8 dmac_channel, u16 ack_no); + u16 default_dma_ack_no; u16 default_dma_req_no; }; =20 @@ -366,6 +370,60 @@ static void rz_dmac_set_dma_req_no(struct rz_dmac *dma= c, unsigned int index, rz_dmac_set_dmars_register(dmac, index, req_no); } =20 +/* + * Map MID/RID request number (bits[0:9] of DMA specifier) to the ICU + * DMA ACK signal number, per RZ/G3E hardware manual Table 4.6-28. + * + * Three peripheral groups cover all ACK-capable peripherals: + * + * PFC external DMA pins (DREQ0..DREQ4): + * req_no 0x000-0x004 -> ACK No. 84-88 (ack =3D req_no + 84) + * + * SSIU BUSIFs (ssip00..ssip93): + * req_no 0x161-0x198 -> ACK No. 28-83 (ack =3D req_no - 0x145) + * + * SPDIF (CH0..CH2) + SCU SRC (sr0..sr9) + DVC (cmd0..cmd1): + * req_no 0x199-0x1b4 -> ACK No. 0-27 (ack =3D req_no - 0x199) + */ +static int rz_dmac_get_ack_no(const struct rz_dmac_info *info, u16 req_no) +{ + if (!info->icu_register_dma_ack) + return -EINVAL; + + switch (req_no) { + case 0x000 ... 0x004: + /* PFC external DMA pins: ACK No. 84-88 */ + return req_no + 84; + case 0x161 ... 0x198: + /* SSIU BUSIFs: ACK No. 28-83 */ + return req_no - 0x145; + case 0x199 ... 0x1b4: + /* SPDIF + SCU SRC + DVC: ACK No. 0-27 */ + return req_no - 0x199; + default: + return -EINVAL; + } +} + +static void rz_dmac_set_dma_ack_no(struct rz_dmac *dmac, unsigned int inde= x, + int ack_no) +{ + if (ack_no < 0 || !dmac->info->icu_register_dma_ack) + return; + + dmac->info->icu_register_dma_ack(dmac->icu.pdev, dmac->icu.dmac_index, + index, ack_no); +} + +static void rz_dmac_reset_dma_ack_no(struct rz_dmac *dmac, int ack_no) +{ + if (ack_no < 0 || !dmac->info->icu_register_dma_ack) + return; + + dmac->info->icu_register_dma_ack(dmac->icu.pdev, dmac->icu.dmac_index, + dmac->info->default_dma_ack_no, ack_no); +} + static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) { struct dma_chan *chan =3D &channel->vc.chan; @@ -438,6 +496,7 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct r= z_dmac_chan *channel) channel->lmdesc.tail =3D lmdesc; =20 rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); + rz_dmac_set_dma_ack_no(dmac, channel->index, channel->dmac_ack); =20 channel->chctrl =3D 0; } @@ -491,6 +550,7 @@ static void rz_dmac_prepare_descs_for_cyclic(struct rz_= dmac_chan *channel) channel->lmdesc.tail =3D lmdesc; =20 rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); + rz_dmac_set_dma_ack_no(dmac, channel->index, channel->dmac_ack); } =20 static void rz_dmac_xfer_desc(struct rz_dmac_chan *chan) @@ -583,6 +643,8 @@ static void rz_dmac_free_chan_resources(struct dma_chan= *chan) } =20 channel->status =3D 0; + rz_dmac_reset_dma_ack_no(dmac, channel->dmac_ack); + channel->dmac_ack =3D -EINVAL; =20 spin_unlock_irqrestore(&channel->vc.lock, flags); =20 @@ -846,6 +908,7 @@ static void rz_dmac_device_synchronize(struct dma_chan = *chan) dev_warn(dmac->dev, "DMA Timeout"); =20 rz_dmac_set_dma_req_no(dmac, channel->index, dmac->info->default_dma_req_= no); + rz_dmac_reset_dma_ack_no(dmac, channel->dmac_ack); } =20 static struct rz_lmdesc * @@ -1175,6 +1238,8 @@ static bool rz_dmac_chan_filter(struct dma_chan *chan= , void *arg) channel->chcfg =3D CHCFG_FILL_TM(ch_cfg) | CHCFG_FILL_AM(ch_cfg) | CHCFG_FILL_LVL(ch_cfg) | CHCFG_FILL_HIEN(ch_cfg); =20 + channel->dmac_ack =3D rz_dmac_get_ack_no(dmac->info, channel->mid_rid); + return !test_and_set_bit(channel->mid_rid, dmac->modules); } =20 @@ -1211,6 +1276,7 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac, =20 channel->index =3D index; channel->mid_rid =3D -EINVAL; + channel->dmac_ack =3D -EINVAL; =20 /* Set io base address for each channel */ if (index < 8) { @@ -1583,6 +1649,7 @@ static int rz_dmac_resume(struct device *dev) continue; =20 rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); + rz_dmac_set_dma_ack_no(dmac, channel->index, channel->dmac_ack); =20 rz_dmac_ch_writel(channel, channel->pm_state.nxla, NXLA, 1); rz_dmac_ch_writel(channel, channel->chcfg, CHCFG, 1); @@ -1607,6 +1674,8 @@ static const struct dev_pm_ops rz_dmac_pm_ops =3D { =20 static const struct rz_dmac_info rz_dmac_v2h_info =3D { .icu_register_dma_req =3D rzv2h_icu_register_dma_req, + .icu_register_dma_ack =3D rzv2h_icu_register_dma_ack, + .default_dma_ack_no =3D RZV2H_ICU_DMAC_ACK_NO_DEFAULT, .default_dma_req_no =3D RZV2H_ICU_DMAC_REQ_NO_DEFAULT, }; =20 --=20 2.25.1