From nobody Mon Jun 8 23:56:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4577E3E5EFD; Mon, 25 May 2026 09:25:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779701133; cv=none; b=rT9lH923mwSZvySJ6uw7SWPOFadwV5jpEvcr/dRnk+FTA+rprMj5iGwaXKvj9M5LSN1LDAh230XC2ZaAxKJjvyWFbeLMhzpDJxU+Cs5UsIm3EIAl78dF5itBG5OrUftFD49bFAcygemQDfNTJlPTGqvmuVP+4FNHTqWtx4opfK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779701133; c=relaxed/simple; bh=ZmyfIH5KhFAjKsOYICrfyLRCXsbn+1dxlewuuX1LfIQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a2CuP5Wu+uasIMzmPmX2K7Tt5gkXdb8YP9nxvMWoIJrONXi8ebex78mgOOFJKOAQ2wu1jZpFtztZlttRPfztihjQKUG75B72Iiu69cgbOs5afOTA6S+HUTlDK0B73U/9LPicRdQVE7Vcj2Qqm5W8bTNgZ6O6SaOXsJyPOvmdIiI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=prAeJLbW; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="prAeJLbW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779701132; x=1811237132; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZmyfIH5KhFAjKsOYICrfyLRCXsbn+1dxlewuuX1LfIQ=; b=prAeJLbWPBcYw2kmWtovWzISTLhI+f2QSkl1K/sSW46f1mUeNXQUTuy5 BjwVywisZxB+neSmfmE/mupf7ellro/0j1Tm4k761qgQOY/gf7YThDYgC sexrhzrhQcDG2e4Q5p8C+ZbkjoGLd5PE2A0ZAtYdvGO/+LpJ9ckhpHC32 0Bk1Wj421UmpGjofOl3RrW+wx/81t2tnbzx7Jq87E0jhFU1skRr5bKj8r MoyWo/Nt1DrLtopDYxz7uTQNA/Sb3SSBtGZRnQ+E+LLobT8+y/QLFKkYp hEPrnuMpZKEF/S89Yhl7CXXAX1YAhEvdzNKCa2cXU3IbHlvjAqpF+IP5L Q==; X-CSE-ConnectionGUID: ErrMcRDBRb2Cm5bGCRCQQQ== X-CSE-MsgGUID: J4LVG0OBTUegvkqNrxcbUg== X-IronPort-AV: E=Sophos;i="6.24,167,1774335600"; d="scan'208";a="289388357" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2026 02:24:30 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.41; Mon, 25 May 2026 02:24:29 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 25 May 2026 02:24:20 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan , Conor Dooley Subject: [PATCH v7 1/5] dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible Date: Mon, 25 May 2026 14:54:01 +0530 Message-ID: <20260525092405.1514213-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260525092405.1514213-1-manikandan.m@microchip.com> References: <20260525092405.1514213-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C HCI binding. The Microchip SAMA7D65 I3C controller is based on the MIPI HCI specification but requires two clocks, so add a conditional constraint when this compatible is present. Acked-by: Conor Dooley Reviewed-by: Frank Li Signed-off-by: Manikandan Muralidharan --- Changes in v5: - drop min/maxItems around clock entries - use if/then/else clause instead of separate allOf entry - cosmetic fixes for indentation and formatting Changes in v4: - Define and describe the clock property in the top-level properties section rather than inside the if/then conditional .../devicetree/bindings/i3c/mipi-i3c-hci.yaml | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Docu= mentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml index 39bb1a1784c9..d488fb420945 100644 --- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml +++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml @@ -9,9 +9,6 @@ title: MIPI I3C HCI maintainers: - Nicolas Pitre =20 -allOf: - - $ref: /schemas/i3c/i3c.yaml# - description: | MIPI I3C Host Controller Interface =20 @@ -28,9 +25,17 @@ description: | =20 properties: compatible: - const: mipi-i3c-hci + enum: + - mipi-i3c-hci + - microchip,sama7d65-i3c-hci reg: maxItems: 1 + + clocks: + items: + - description: Peripheral bus clock + - description: System Generic clock + interrupts: maxItems: 1 =20 @@ -39,6 +44,20 @@ required: - reg - interrupts =20 +allOf: + - $ref: /schemas/i3c/i3c.yaml# + - if: + properties: + compatible: + contains: + const: microchip,sama7d65-i3c-hci + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false =20 examples: --=20 2.25.1 From nobody Mon Jun 8 23:56:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B868125AA; 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charset="utf-8" From: Durai Manickam KR Add peripheral clock description for I3C. Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Fixed indentation issues in the clock table entry drivers/clk/at91/sama7d65.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 7dee2b160ffb..ba8ff413fa2c 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -677,6 +677,7 @@ static struct { { .n =3D "uhphs_clk", .p =3D PCK_PARENT_HW_MCK5, .id =3D 101, }, { .n =3D "dsi_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 103, }, { .n =3D "lvdsc_clk", .p =3D PCK_PARENT_HW_MCK3, .id =3D 104, }, + { .n =3D "i3cc_clk", .p =3D PCK_PARENT_HW_MCK8, .id =3D 105, }, }; =20 /* --=20 2.25.1 From nobody Mon Jun 8 23:56:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B17B93E63A1; Mon, 25 May 2026 09:24:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779701089; cv=none; b=fG501XCEhc/ARPSdJyRXH5pj2Ou88oN9UeHmCbkio+kSi3631v1i2rhsHYFE1raVWuJiy4GTTiWpbsYKM46YftAUC98E1yfa/x92DVou7n59qAjthhbJs/3HJUd0yq8l0b+3PPMDb65PaMXvuvI98qYxTnzsfxCYhFRug63/dz4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779701089; c=relaxed/simple; bh=JOz8CyPvTuEnYMyTAQgQxItg+5IUdou+jREaprkAVvs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DJ1h61jwhwuQAhWd8Y+b1z8e2zIV1o02CF3rlriHBuh0AcXD5t2XmHStu3dcG/nFBGDEzgVwI4/aQqxcc1WA85Z6fyNxvvGL6WpvPuRYg5RXpm1QEc6uehxAiWhapk/Psb7w5r/lZHXKSyuGdcFwJxCeqedGW+tCHn6BdjE50Pg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=2cwM4Dka; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="2cwM4Dka" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779701088; x=1811237088; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JOz8CyPvTuEnYMyTAQgQxItg+5IUdou+jREaprkAVvs=; b=2cwM4DkanOR1TtMcmtHTM+8Dzr0iWrQhEwruQSDVGDUr72Oy8cTxbXts 0EoxNmfxYuIiY3a/S8UNMJ9FFIt276fx00aah4kEQOmufxG4SsRCbw93H qeL/k4kWgxs89N7BFmKbOQXfOAXOkjbnOsEEu4kt7VlAgOqmqtGKYl/D+ 5CQ4dSAlhDLrxJzf++p5c1e05eqwWDCRW6uH9iJP8vSSFE2MrYyiG40B8 ABfGWoaWZypTY6PGtHms5tz2SCfq+FVrQPJA9mllYoYwEvx6ewX27XvUV RJe89kI9uIIlLHgOiHHreoCb3quUPPTnD4FE0khAfR759O0ny2pEvkYcT g==; X-CSE-ConnectionGUID: B8MMbkFuT/KNheQJC2z/Sw== X-CSE-MsgGUID: iAMsBOFnQWaGu8ORH0hQSQ== X-IronPort-AV: E=Sophos;i="6.24,167,1774335600"; d="scan'208";a="58412018" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2026 02:24:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.41; Mon, 25 May 2026 02:24:46 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 25 May 2026 02:24:38 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v7 3/5] i3c: mipi-i3c-hci: add microchip sama7d65 SoC compatible with the required quirk Date: Mon, 25 May 2026 14:54:03 +0530 Message-ID: <20260525092405.1514213-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260525092405.1514213-1-manikandan.m@microchip.com> References: <20260525092405.1514213-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for microchip sama7d65 SoC I3C HCI master only IP with additional clock support to enable bulk clock acquisition and apply the required quirks. Reviewed-by: Adrian Hunter Signed-off-by: Manikandan Muralidharan Reviewed-by: Frank Li --- Changes in v7: - Use (void *)(ulong) cast instead of direct (void *) cast in of_device_id.data for pointer-size safety across architectures - Update commit message body to explicitly mention quirk application Changes in v6: - Reorder local variable definitions in i3c_hci_probe in descending order of line length Changes in v5: - Remove HCI_QUIRK_CLK_SUPPORT quirk and call devm_clk_bulk_get_all_enabled unconditionally, eliminating the need for a clock-specific quirk flag Changes in v4: - Remove the clock index variable MCHP_I3C_CLK_IDX as it is no longer needed after switching to bulk clock handling Changes in v3: - Make use of existing HCI_QUIRK_* code base instead of introducing separate MCHP_HCI_QUIRK_* flags - Introduce HCI_QUIRK_CLK_SUPPORT to handle peripheral and system generic clk in bulk Changes in v2: - Platform specific changes integrated in the existing mipi-i3c-hci driver by introducing separate MCHP_HCI_QUIRK_* quirks and vendor specific quirk files rather than a standalone driver drivers/i3c/master/mipi-i3c-hci/core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index b781dbed2165..4cdf2abd4219 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -969,6 +970,7 @@ static int i3c_hci_init(struct i3c_hci *hci) static int i3c_hci_probe(struct platform_device *pdev) { const struct mipi_i3c_hci_platform_data *pdata =3D pdev->dev.platform_dat= a; + struct clk_bulk_data *clks; struct i3c_hci *hci; int irq, ret; =20 @@ -1001,6 +1003,11 @@ static int i3c_hci_probe(struct platform_device *pde= v) if (!hci->quirks && platform_get_device_id(pdev)) hci->quirks =3D platform_get_device_id(pdev)->driver_data; =20 + ret =3D devm_clk_bulk_get_all_enabled(&pdev->dev, &clks); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get clocks\n"); + ret =3D i3c_hci_init(hci); if (ret) return ret; @@ -1031,6 +1038,9 @@ static void i3c_hci_remove(struct platform_device *pd= ev) =20 static const __maybe_unused struct of_device_id i3c_hci_of_match[] =3D { { .compatible =3D "mipi-i3c-hci", }, + { .compatible =3D "microchip,sama7d65-i3c-hci", + .data =3D (void *)(ulong)(HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | + HCI_QUIRK_RESP_BUF_THLD) }, {}, }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); --=20 2.25.1 From nobody Mon Jun 8 23:56:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97B5539A80E; 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charset="utf-8" From: Durai Manickam KR Add I3C controller for sama7d65 SoC. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Remove clock-names property as the driver acquires and enables clocks in bulk using devm_clk_bulk_get_all_enabled arch/arm/boot/dts/microchip/sama7d65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 67253bbc08df..ec200848c153 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -1055,5 +1055,13 @@ gic: interrupt-controller@e8c11000 { #address-cells =3D <0>; interrupt-controller; }; + + i3c: i3c@e9000000 { + compatible =3D "microchip,sama7d65-i3c-hci"; + reg =3D <0xe9000000 0x300>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>; + status =3D "disabled"; + }; }; }; --=20 2.25.1 From nobody Mon Jun 8 23:56:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D4053E8320; Mon, 25 May 2026 09:25:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779701106; cv=none; b=qSIud4Oz2AaLPeBKngQBgxN5iQ4qpLNoutkcd7creKisEo9BTmQ1DvkXbovQEAwFUGLq9BCT6sgIar0YfthA9pNXSm+1Br5UBjFaRpa6npdRp0bc9o/hkRmZplZNrze3epw/c/QES6R9wuy+Y8Qazoqyhcy4vL2G7w838z+/KjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779701106; c=relaxed/simple; bh=6AUu28k/Clqbv8wTtKnnwKjWBW9XtjZIigR38lrNNYw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nVIW2e5Mdmp2oiviluSlSKLYqFaTvJTvMAUbmlyxlMc7mrQ42pZWtFAgfaqimUX2GobUL2vJWEoOVD2wVr0wIti3o/4y2uaBLRtSWiYeQvzPtBbDMT6V7s1X2uG7zcyVKgYmwPvP+YmxbCoM0GylMEwLkG0ENnAYgUkR8mcTc1I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=r7Mk1wHK; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="r7Mk1wHK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779701105; x=1811237105; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6AUu28k/Clqbv8wTtKnnwKjWBW9XtjZIigR38lrNNYw=; b=r7Mk1wHK6JmYRX2gFQTXt3Yh9/I1pBlz7YS/lzMSlOIVlUPxPXdiUUSb YdhJSkvCbl5j3h3yV+but5+ByMaUo1F6KlMNiUzirsN81aC1o5nl+xES1 1ffFHkYnPNVtKohE8oMMJaltgv0uQaMs7all8acUb+lmDZuY4X9NbBUzt fPdrk20edtTeOIez6TaAMzMLZKtQOFrLmmrTE/ty0sQbHgM7RPNKXyh9v f2yorbE3/C94B7W/Um6hdwzJh6azSMHZPmUhtAN12mNXhp1EecWU7JA5Q od6SnWdt8DDDRiZLPS1vyGR09jdhGhLMVgG+pGMhTqohczCQioySodTVf g==; X-CSE-ConnectionGUID: w72KhTerRzCNpgloKDd3vQ== X-CSE-MsgGUID: /Y7BedzdS4eyqLDAz5w4zw== X-IronPort-AV: E=Sophos;i="6.24,167,1774335600"; d="scan'208";a="57215514" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2026 02:25:04 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.41; Mon, 25 May 2026 02:25:04 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 25 May 2026 02:24:55 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan , Durai Manickam KR Subject: [PATCH v7 5/5] ARM: configs: at91: sama7: add sama7d65 i3c-hci Date: Mon, 25 May 2026 14:54:05 +0530 Message-ID: <20260525092405.1514213-6-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260525092405.1514213-1-manikandan.m@microchip.com> References: <20260525092405.1514213-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the configs needed for I3C framework and microchip sama7d65 i3c-hci driver. Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea Signed-off-by: Manikandan Muralidharan --- arch/arm/configs/sama7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defc= onfig index e52f671ccec4..6470c7d3fe8a 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -117,6 +117,8 @@ CONFIG_HW_RANDOM=3Dy CONFIG_I2C=3Dy CONFIG_I2C_CHARDEV=3Dy CONFIG_I2C_AT91=3Dy +CONFIG_I3C=3Dy +CONFIG_MIPI_I3C_HCI=3Dy CONFIG_SPI=3Dy CONFIG_SPI_ATMEL=3Dy CONFIG_SPI_ATMEL_QUADSPI=3Dy --=20 2.25.1