From nobody Tue Jun 9 01:01:18 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF6B03AA1B2; Mon, 25 May 2026 06:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779691677; cv=none; b=JZGJwOpte435hgBZldbUsWmSp69QpYhFLGimRLuyo8BcfzesyvT7O4RvJiWAhnozxNHafHMhEGpGeKJk16zPDbxkcoy+eICKHpSix5H1u9pyhtdQ7AmbL4JPi6rDV3hrfDVFrmYb8mRvj9MHxenoWm07QhnOJaZCfqwFPqJ0J6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779691677; c=relaxed/simple; bh=8IJtxE6ig879Om2zQsEpoJwAJxcysV9GjhnS8w61yPE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d82DPD3uE6B/BULfBgIBgvECvL/VJHEGFDOfbaEdapSU0Xo33XsGkgddt8u0lY0gehcTMu/Ie7dmpeQ6wbsEjUzYP7lTg+IabWkC24tFhuAxomqRqlLA1xeEsd2vvyXjVjgXpv5JIlS+TBym1AR4Mtf5arCIVDqQO4WEFcLbIGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HF+datPj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HF+datPj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4A78CC2BCB3; Mon, 25 May 2026 06:47:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779691676; bh=8IJtxE6ig879Om2zQsEpoJwAJxcysV9GjhnS8w61yPE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HF+datPjSxS3b5PgXXMxnBM3jF1xWKk0kHemKUPIm88QAyU9IAWOkfPI9J9R95SZj s3Zl5r4c81sCZSo2+5U+nW314g55ayDxkiXF3ayYbKCuC95Q+u4eVeCTxbEP7tcqGI Zvf2ofIZGsg15dBfZy6UG73yczAqk6eSCqj+0C9B0nxTTNJURM0NsuPNDgxHkUtKkW EKly34hSsZZVV7xJcJAnYyqPgsUa+K1O12dbQvZMZadaWSuNTWRbs6uHZTa33ZP2Z/ Kn5EaXABwXKKbDRs4fI5lKnTpPqFmfiX7Em76/pRm8bisQNyEss4CFj4+ZOTVTwQZ6 BQ2hjHDTAWFrQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3696ACD5BBF; Mon, 25 May 2026 06:47:56 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Mon, 25 May 2026 01:47:44 -0500 Subject: [PATCH v2 1/2] spi: tegra210-quad: Allocate DMA memory for DMA engine Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260525-tegra194-qspi-iommu-v2-1-a11c53f804b2@gmail.com> References: <20260525-tegra194-qspi-iommu-v2-0-a11c53f804b2@gmail.com> In-Reply-To: <20260525-tegra194-qspi-iommu-v2-0-a11c53f804b2@gmail.com> To: Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Laxman Dewangan , Mark Brown , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-tegra@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, devicetree@vger.kernel.org, Thierry Reding , Aaron Kling X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779691675; l=4772; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=l7YzDxh5xjjzC7rsRABKlUS2hzABVlzgeHIZyzIWkrM=; b=1CpmXZNayhDytsA6U5Qt3+xyw/X7Eb6AGh0QR7nvO2tUVzPwtmzzzjdw398yo30DQVIpDEIyd bl3Q0/WH8EFCpg1Oe/n3LOBMq4SK7Mpln8fxiexCXagp6RW6EfEmPtX X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling When the SPI controllers are running in DMA mode, it is the DMA engine that performs the memory accesses rather than the SPI controller. Pass the DMA engine's struct device pointer to the DMA API to make sure the correct DMA operations are used. Suggested-by: Thierry Reding Signed-off-by: Aaron Kling --- drivers/spi/spi-tegra210-quad.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index db28dd556484b2..588a929a97850a 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -226,11 +226,13 @@ struct tegra_qspi { struct completion xfer_completion; struct spi_transfer *curr_xfer; =20 + struct device *rx_dma_dev; struct dma_chan *rx_dma_chan; u32 *rx_dma_buf; dma_addr_t rx_dma_phys; struct dma_async_tx_descriptor *rx_dma_desc; =20 + struct device *tx_dma_dev; struct dma_chan *tx_dma_chan; u32 *tx_dma_buf; dma_addr_t tx_dma_phys; @@ -574,15 +576,15 @@ static int tegra_qspi_dma_map_xfer(struct tegra_qspi = *tqspi, struct spi_transfer len =3D DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * = 4; =20 if (t->tx_buf) { - t->tx_dma =3D dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEV= ICE); - if (dma_mapping_error(tqspi->dev, t->tx_dma)) + t->tx_dma =3D dma_map_single(tqspi->tx_dma_dev, (void *)tx_buf, len, DMA= _TO_DEVICE); + if (dma_mapping_error(tqspi->tx_dma_dev, t->tx_dma)) return -ENOMEM; } =20 if (t->rx_buf) { - t->rx_dma =3D dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_D= EVICE); - if (dma_mapping_error(tqspi->dev, t->rx_dma)) { - dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); + t->rx_dma =3D dma_map_single(tqspi->rx_dma_dev, (void *)rx_buf, len, DMA= _FROM_DEVICE); + if (dma_mapping_error(tqspi->rx_dma_dev, t->rx_dma)) { + dma_unmap_single(tqspi->tx_dma_dev, t->tx_dma, len, DMA_TO_DEVICE); return -ENOMEM; } } @@ -597,9 +599,9 @@ static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi= *tqspi, struct spi_trans len =3D DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * = 4; =20 if (t->tx_buf) - dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); + dma_unmap_single(tqspi->tx_dma_dev, t->tx_dma, len, DMA_TO_DEVICE); if (t->rx_buf) - dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); + dma_unmap_single(tqspi->rx_dma_dev, t->rx_dma, len, DMA_FROM_DEVICE); } =20 static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, s= truct spi_transfer *t) @@ -745,7 +747,7 @@ static int tegra_qspi_start_cpu_based_transfer(struct t= egra_qspi *qspi, struct s static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi) { if (tqspi->tx_dma_buf) { - dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, + dma_free_coherent(tqspi->tx_dma_dev, tqspi->dma_buf_size, tqspi->tx_dma_buf, tqspi->tx_dma_phys); tqspi->tx_dma_buf =3D NULL; } @@ -756,7 +758,7 @@ static void tegra_qspi_deinit_dma(struct tegra_qspi *tq= spi) } =20 if (tqspi->rx_dma_buf) { - dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, + dma_free_coherent(tqspi->rx_dma_dev, tqspi->dma_buf_size, tqspi->rx_dma_buf, tqspi->rx_dma_phys); tqspi->rx_dma_buf =3D NULL; } @@ -782,6 +784,7 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) } =20 tqspi->rx_dma_chan =3D dma_chan; + tqspi->rx_dma_dev =3D dmaengine_get_dma_device(tqspi->rx_dma_chan); =20 dma_chan =3D dma_request_chan(tqspi->dev, "tx"); if (IS_ERR(dma_chan)) { @@ -790,15 +793,19 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqs= pi) } =20 tqspi->tx_dma_chan =3D dma_chan; + tqspi->tx_dma_dev =3D dmaengine_get_dma_device(tqspi->tx_dma_chan); } else { if (!device_iommu_mapped(tqspi->dev)) { dev_warn(tqspi->dev, "IOMMU not enabled in device-tree, falling back to PIO mode\n"); return 0; } + + tqspi->rx_dma_dev =3D tqspi->dev; + tqspi->tx_dma_dev =3D tqspi->dev; } =20 - dma_buf =3D dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys= , GFP_KERNEL); + dma_buf =3D dma_alloc_coherent(tqspi->rx_dma_dev, tqspi->dma_buf_size, &d= ma_phys, GFP_KERNEL); if (!dma_buf) { err =3D -ENOMEM; goto err_out; @@ -807,7 +814,7 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) tqspi->rx_dma_buf =3D dma_buf; tqspi->rx_dma_phys =3D dma_phys; =20 - dma_buf =3D dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys= , GFP_KERNEL); + dma_buf =3D dma_alloc_coherent(tqspi->tx_dma_dev, tqspi->dma_buf_size, &d= ma_phys, GFP_KERNEL); if (!dma_buf) { err =3D -ENOMEM; goto err_out; --=20 2.53.0 From nobody Tue Jun 9 01:01:18 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF9503AA1BA; Mon, 25 May 2026 06:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779691677; cv=none; b=btSzLAIi3BiwUL4XeOGRw2Z62iX7s+oOTpyxCkz1PL22IzP1hlKC/RvahxWV6/g5iOJe6GAfQhhuLawmOE/nu9FWWiYuoNjL9+KC4M+1I1C6WtomBhLcQC27sCx1iawPGEvxx8vO42tgQJ5mX2n+e908uWQegUTVh0lhjKBFs5g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779691677; c=relaxed/simple; bh=rQtWtz9PaBC5kO/YmeSFs1AL2c5xXsa62gy6hOf0BC4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Mon, 25 May 2026 06:47:56 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Mon, 25 May 2026 01:47:45 -0500 Subject: [PATCH v2 2/2] arm64: tegra: Enable DMA Support on Tegra194 QSPI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260525-tegra194-qspi-iommu-v2-2-a11c53f804b2@gmail.com> References: <20260525-tegra194-qspi-iommu-v2-0-a11c53f804b2@gmail.com> In-Reply-To: <20260525-tegra194-qspi-iommu-v2-0-a11c53f804b2@gmail.com> To: Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Laxman Dewangan , Mark Brown , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-tegra@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, devicetree@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779691675; l=1118; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=KjSbPkVlCYH0lmqUb9TdWBRiwbc5n5A4wUaKdi0Q4ak=; b=PBjXCsxlPIs64wXAC3rv9Jl/iDRaXY0pG7TZaawi+0P9HpR2fOtGfRnlvlgqjKFs1D5MLuduh dV+Gq/kPkXYA63Uajrq8p3bL7jiD7BePTNcpBzrltxNxMjBOVFAbTfp X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Without dma enabled pio mode is used and flash storage such as the one on the p3668 module times out and cannot complete any transfers. In some cases, these timeouts cause hangs and cbb faults. Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts= /nvidia/tegra194.dtsi index 1d659454a6f9fe..e2ddbc6715d5e8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -923,6 +923,8 @@ spi@3270000 { <&bpmp TEGRA194_CLK_QSPI0_PM>; clock-names =3D "qspi", "qspi_out"; resets =3D <&bpmp TEGRA194_RESET_QSPI0>; + dmas =3D <&gpcdma 5>, <&gpcdma 5>; + dma-names =3D "rx", "tx"; status =3D "disabled"; }; =20 @@ -1013,6 +1015,8 @@ spi@3300000 { <&bpmp TEGRA194_CLK_QSPI1_PM>; clock-names =3D "qspi", "qspi_out"; resets =3D <&bpmp TEGRA194_RESET_QSPI1>; + dmas =3D <&gpcdma 6>, <&gpcdma 6>; + dma-names =3D "rx", "tx"; status =3D "disabled"; }; =20 --=20 2.53.0