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[34.38.141.231]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454cfcaesm241824825e9.4.2026.05.25.05.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 05:50:29 -0700 (PDT) From: Tudor Ambarus Date: Mon, 25 May 2026 12:50:21 +0000 Subject: [PATCH v5 1/5] dt-bindings: thermal: Add Google GS101 TMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260525-acpm-tmu-v5-1-85fde739752e@linaro.org> References: <20260525-acpm-tmu-v5-0-85fde739752e@linaro.org> In-Reply-To: <20260525-acpm-tmu-v5-0-85fde739752e@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Alim Akhtar Cc: jyescas@google.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-hardening@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tudor Ambarus , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779713428; l=3371; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=DAUUHdnV6Bz6+/JxuE+k0hPb6SNHwiYOqoiSfSYzQUs=; b=ULkkI8n2UPTnqvUWoHoTUCDJ4MK6ZX+UVIFvysuu2RleXY/AfOM/GGmGmIu4wMR82yOPy1RW4 OLHQ5e8X18nBxHYr/DkmwVIAVM0SLz/ezkJaIIoPA5PdDiemOxCXLee X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Document the Thermal Management Unit (TMU) found on the Google GS101 SoC. The GS101 TMU utilizes a hybrid control model shared between the Application Processor (AP) and the ACPM (Alive Clock and Power Manager) firmware. This hybrid ACPM TMU architecture is also present on other Samsung Exynos SoCs (e.g., AutoV920, Exynos850). While the TMU is a standard memory-mapped IP block, on this platform the AP's direct register access is restricted to the interrupt pending (INTPEND) registers for event identification. High-level functional tasks, such as sensor initialization, threshold programming, and temperature reads, are delegated to the ACPM firmware. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski --- .../bindings/thermal/google,gs101-tmu-top.yaml | 68 ++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top= .yaml b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml new file mode 100644 index 000000000000..d0eb2393d581 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/google,gs101-tmu-top.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos ACPM Thermal Management Unit (TMU) + +maintainers: + - Tudor Ambarus + +description: + The Samsung Exynos ACPM TMU is a thermal sensor block found on Exynos + based platforms (such as Google GS101 and Exynos850). It supports + both direct register-level access and firmware-mediated management + via the ACPM (Alive Clock and Power Manager) firmware. + + On these platforms, the hardware is managed in a hybrid fashion. The + Application Processor (AP) maintains direct memory-mapped access + exclusively to the interrupt pending registers to identify thermal + events. All other functional aspects - including sensor + initialization, threshold configuration, and temperature acquisition + - are handled by the ACPM firmware. The AP coordinates these + operations through the ACPM IPC protocol. + +properties: + compatible: + const: google,gs101-tmu-top + + reg: + maxItems: 1 + + clocks: + items: + - description: APB peripheral clock (PCLK) for TMU register access. + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + + samsung,acpm-ipc: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the ACPM IPC node. + +required: + - compatible + - reg + - clocks + - interrupts + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + thermal-sensor@100a0000 { + compatible =3D "google,gs101-tmu-top"; + reg =3D <0x100a0000 0x800>; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + samsung,acpm-ipc =3D <&acpm_ipc>; + }; --=20 2.54.0.746.g67dd491aae-goog From nobody Mon Jun 8 23:57:49 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC65C382294 for ; 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[34.38.141.231]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454cfcaesm241824825e9.4.2026.05.25.05.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 05:50:29 -0700 (PDT) From: Tudor Ambarus Date: Mon, 25 May 2026 12:50:22 +0000 Subject: [PATCH v5 2/5] thermal: samsung: Add Exynos ACPM TMU driver GS101 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260525-acpm-tmu-v5-2-85fde739752e@linaro.org> References: <20260525-acpm-tmu-v5-0-85fde739752e@linaro.org> In-Reply-To: <20260525-acpm-tmu-v5-0-85fde739752e@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Alim Akhtar Cc: jyescas@google.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-hardening@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tudor Ambarus , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779713428; l=17724; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=RghTm9nn3Z1bLgEKIHg5Mlfb92Glx51GU4wS21jsGRw=; b=f/6BAEweD7+4psiV+aCDjrUIHo5QzbLFwRZWdsxLtShGCyG7hcEGUy1D3pcZFEO6/RSTpMUBN 76G+A0a+YN6CBLQFFTazsFlxjp8tu3Q+ptML8MKEtvlZ95cyWtugMkS X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add driver for the Thermal Management Unit (TMU) managed via the Alive Clock and Power Manager (ACPM), found on Samsung Exynos SoCs such as Google GS101 (and Exynos850, autov920, etc.). The TMU on utilizes a hybrid management model shared between the Application Processor (AP) and the ACPM firmware. The driver maintains direct memory-mapped access to the TMU interrupt pending registers to identify thermal events, while delegating functional tasks - such as sensor initialization, threshold configuration, and temperature acquisition - to the ACPM firmware via the ACPM IPC protocol. Signed-off-by: Tudor Ambarus Acked-by: Krzysztof Kozlowski --- drivers/thermal/samsung/Kconfig | 17 ++ drivers/thermal/samsung/Makefile | 2 + drivers/thermal/samsung/acpm-tmu.c | 547 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 566 insertions(+) diff --git a/drivers/thermal/samsung/Kconfig b/drivers/thermal/samsung/Kcon= fig index f4eff5a41a84..0d3ffbdc66f0 100644 --- a/drivers/thermal/samsung/Kconfig +++ b/drivers/thermal/samsung/Kconfig @@ -9,3 +9,20 @@ config EXYNOS_THERMAL the TMU, reports temperature and handles cooling action if defined. This driver uses the Exynos core thermal APIs and TMU configuration data from the supported SoCs. + +config EXYNOS_ACPM_THERMAL + tristate "Exynos ACPM thermal management unit driver" + depends on THERMAL_OF + depends on EXYNOS_ACPM_PROTOCOL || (COMPILE_TEST && !EXYNOS_ACPM_PROTOCOL) + help + Support for the Thermal Management Unit (TMU) on Samsung Exynos SoCs + (such as Google GS101 and Exynos850). + + The TMU on these platforms is managed through a hybrid architecture. + This driver handles direct register access for thermal interrupt status + monitoring and communicates with the Alive Clock and Power Manager + (ACPM) firmware via the ACPM IPC protocol for functional sensor control + and configuration. + + Select this if you want to monitor device temperature and enable + thermal mitigation on Samsung Exynos ACPM based devices. diff --git a/drivers/thermal/samsung/Makefile b/drivers/thermal/samsung/Mak= efile index f139407150d2..daed80647c34 100644 --- a/drivers/thermal/samsung/Makefile +++ b/drivers/thermal/samsung/Makefile @@ -4,3 +4,5 @@ # obj-$(CONFIG_EXYNOS_THERMAL) +=3D exynos_thermal.o exynos_thermal-y :=3D exynos_tmu.o +obj-$(CONFIG_EXYNOS_ACPM_THERMAL) +=3D exynos_acpm_thermal.o +exynos_acpm_thermal-y :=3D acpm-tmu.o diff --git a/drivers/thermal/samsung/acpm-tmu.c b/drivers/thermal/samsung/a= cpm-tmu.c new file mode 100644 index 000000000000..d4e42b23c0c1 --- /dev/null +++ b/drivers/thermal/samsung/acpm-tmu.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2019 Samsung Electronics Co., Ltd. + * Copyright 2025 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +#define EXYNOS_TMU_SENSOR(i) BIT(i) +#define EXYNOS_TMU_SENSORS_MAX_COUNT 16 + +#define GS101_CPUCL2_SENSOR_MASK (EXYNOS_TMU_SENSOR(0) | \ + EXYNOS_TMU_SENSOR(6) | \ + EXYNOS_TMU_SENSOR(7) | \ + EXYNOS_TMU_SENSOR(8) | \ + EXYNOS_TMU_SENSOR(9)) +#define GS101_CPUCL1_SENSOR_MASK (EXYNOS_TMU_SENSOR(4) | \ + EXYNOS_TMU_SENSOR(5)) +#define GS101_CPUCL0_SENSOR_MASK (EXYNOS_TMU_SENSOR(1) | \ + EXYNOS_TMU_SENSOR(2)) + +#define GS101_REG_INTPEND(i) ((i) * 0x50 + 0xf8) + +enum { + P0_INTPEND, + P1_INTPEND, + P2_INTPEND, + P3_INTPEND, + P4_INTPEND, + P5_INTPEND, + P6_INTPEND, + P7_INTPEND, + P8_INTPEND, + P9_INTPEND, + P10_INTPEND, + P11_INTPEND, + P12_INTPEND, + P13_INTPEND, + P14_INTPEND, + P15_INTPEND, + REG_INTPEND_COUNT, +}; + +struct acpm_tmu_sensor_group { + u16 mask; + u8 id; +}; + +struct acpm_tmu_sensor { + const struct acpm_tmu_sensor_group *group; + struct thermal_zone_device *tzd; + struct acpm_tmu_priv *priv; + struct mutex lock; /* protects sensor state */ + bool enabled; +}; + +struct acpm_tmu_priv { + struct regmap_field *regmap_fields[REG_INTPEND_COUNT]; + struct acpm_handle *handle; + struct device *dev; + struct clk *clk; + unsigned int mbox_chan_id; + unsigned int num_sensors; + int irq; + struct acpm_tmu_sensor sensors[] __counted_by(num_sensors); +}; + +struct acpm_tmu_driver_data { + const struct reg_field *reg_fields; + const struct acpm_tmu_sensor_group *sensor_groups; + unsigned int num_sensor_groups; + unsigned int mbox_chan_id; +}; + +#define ACPM_TMU_SENSOR_GROUP(_mask, _id) \ + { \ + .mask =3D _mask, \ + .id =3D _id, \ + } + +static const struct acpm_tmu_sensor_group gs101_sensor_groups[] =3D { + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL2_SENSOR_MASK, 0), + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL1_SENSOR_MASK, 1), + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL0_SENSOR_MASK, 2), +}; + +static const struct reg_field gs101_reg_fields[REG_INTPEND_COUNT] =3D { + [P0_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(0), 0, 31), + [P1_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(1), 0, 31), + [P2_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(2), 0, 31), + [P3_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(3), 0, 31), + [P4_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(4), 0, 31), + [P5_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(5), 0, 31), + [P6_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(6), 0, 31), + [P7_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(7), 0, 31), + [P8_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(8), 0, 31), + [P9_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(9), 0, 31), + [P10_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(10), 0, 31), + [P11_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(11), 0, 31), + [P12_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(12), 0, 31), + [P13_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(13), 0, 31), + [P14_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(14), 0, 31), + [P15_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(15), 0, 31), +}; + +static const struct regmap_config gs101_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .use_relaxed_mmio =3D true, + .max_register =3D GS101_REG_INTPEND(15), +}; + +static const struct acpm_tmu_driver_data acpm_tmu_gs101 =3D { + .reg_fields =3D gs101_reg_fields, + .sensor_groups =3D gs101_sensor_groups, + .num_sensor_groups =3D ARRAY_SIZE(gs101_sensor_groups), + .mbox_chan_id =3D 9, +}; + +static int acpm_tmu_op_tz_control(struct acpm_tmu_sensor *sensor, bool on) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops->tmu; + int ret; + + ret =3D ops->tz_control(handle, priv->mbox_chan_id, sensor->group->id, + on); + if (ret) + return ret; + + sensor->enabled =3D on; + + return 0; +} + +static int acpm_tmu_control(struct acpm_tmu_priv *priv, bool on) +{ + struct device *dev =3D priv->dev; + int i, ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + + /* Skip sensors that weren't found in DT */ + if (!sensor->tzd) + continue; + + mutex_lock(&sensor->lock); + ret =3D acpm_tmu_op_tz_control(sensor, on); + mutex_unlock(&sensor->lock); + if (ret) + break; + } + + pm_runtime_put_autosuspend(dev); + return ret; +} + +static int acpm_tmu_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct acpm_tmu_sensor *sensor =3D thermal_zone_device_priv(tz); + struct acpm_tmu_priv *priv =3D sensor->priv; + struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops->tmu; + struct device *dev =3D priv->dev; + int acpm_temp, ret; + + if (!sensor->enabled) + return -EAGAIN; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + scoped_guard(mutex, &sensor->lock) { + ret =3D ops->read_temp(handle, priv->mbox_chan_id, + sensor->group->id, &acpm_temp); + } + + pm_runtime_put_autosuspend(dev); + + if (ret) + return ret; + + *temp =3D acpm_temp * MILLIDEGREE_PER_DEGREE; + + return 0; +} + +static int acpm_tmu_update_thresholds(struct acpm_tmu_sensor *sensor, + u8 thresholds[2], u8 inten) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops->tmu; + unsigned int mbox_chan_id =3D priv->mbox_chan_id; + u8 acpm_sensor_id =3D sensor->group->id; + bool was_enabled =3D sensor->enabled; + int ret; + + guard(mutex)(&sensor->lock); + + if (was_enabled) { + ret =3D acpm_tmu_op_tz_control(sensor, false); + if (ret) + return ret; + } + + ret =3D ops->set_threshold(handle, mbox_chan_id, acpm_sensor_id, + thresholds, 2); + if (ret) + return ret; + + ret =3D ops->set_interrupt_enable(handle, mbox_chan_id, acpm_sensor_id, + inten); + if (ret) + return ret; + + /* Restore based on cached state. */ + if (was_enabled) + ret =3D acpm_tmu_op_tz_control(sensor, true); + + return ret; +} + +static int acpm_tmu_set_trips(struct thermal_zone_device *tz, int low, int= high) +{ + struct acpm_tmu_sensor *sensor =3D thermal_zone_device_priv(tz); + struct acpm_tmu_priv *priv =3D sensor->priv; + struct device *dev =3D priv->dev; + u8 thresholds[2] =3D {}; + u8 inten =3D 0; + int ret; + + /* If a valid lower bound exists, set the threshold and enable its interr= upt */ + if (low > -INT_MAX) { + thresholds[0] =3D clamp_val(low / MILLIDEGREE_PER_DEGREE, 0, 255); + inten |=3D BIT(0); + } + + /* If a valid upper bound exists, set the threshold and enable its interr= upt */ + if (high < INT_MAX) { + thresholds[1] =3D clamp_val(high / MILLIDEGREE_PER_DEGREE, 0, 255); + inten |=3D BIT(1); + } + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret =3D acpm_tmu_update_thresholds(sensor, thresholds, inten); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static const struct thermal_zone_device_ops acpm_tmu_sensor_ops =3D { + .get_temp =3D acpm_tmu_get_temp, + .set_trips =3D acpm_tmu_set_trips, +}; + +static int acpm_tmu_has_pending_irq(struct acpm_tmu_sensor *sensor, + bool *pending_irq) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + unsigned long mask =3D sensor->group->mask; + int i, ret; + u32 val; + + guard(mutex)(&sensor->lock); + + for_each_set_bit(i, &mask, EXYNOS_TMU_SENSORS_MAX_COUNT) { + ret =3D regmap_field_read(priv->regmap_fields[i], &val); + if (ret) + return ret; + + if (val) { + *pending_irq =3D true; + break; + } + } + + return 0; +} + +static irqreturn_t acpm_tmu_thread_fn(int irq, void *id) +{ + struct acpm_tmu_priv *priv =3D id; + struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops->tmu; + struct device *dev =3D priv->dev; + int i, ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, "Failed to resume: %d\n", ret); + return IRQ_NONE; + } + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + bool pending_irq =3D false; + + if (!sensor->tzd) + continue; + + ret =3D acpm_tmu_has_pending_irq(sensor, &pending_irq); + if (ret || !pending_irq) + continue; + + thermal_zone_device_update(sensor->tzd, + THERMAL_EVENT_UNSPECIFIED); + + scoped_guard(mutex, &sensor->lock) { + ret =3D ops->clear_tz_irq(handle, priv->mbox_chan_id, + sensor->group->id); + if (ret) + dev_err(priv->dev, "Sensor %d: failed to clear IRQ (%d)\n", + i, ret); + } + } + + pm_runtime_put_autosuspend(dev); + + return IRQ_HANDLED; +} + +static const struct of_device_id acpm_tmu_match[] =3D { + { .compatible =3D "google,gs101-tmu-top" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, acpm_tmu_match); + +static int acpm_tmu_probe(struct platform_device *pdev) +{ + const struct acpm_tmu_driver_data *data =3D &acpm_tmu_gs101; + struct acpm_handle *acpm_handle; + struct device *dev =3D &pdev->dev; + struct acpm_tmu_priv *priv; + struct regmap *regmap; + void __iomem *base; + int i, ret; + + acpm_handle =3D devm_acpm_get_by_phandle(dev); + if (IS_ERR(acpm_handle)) + return dev_err_probe(dev, PTR_ERR(acpm_handle), + "Failed to get ACPM handle\n"); + + priv =3D devm_kzalloc(dev, + struct_size(priv, sensors, data->num_sensor_groups), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->handle =3D acpm_handle; + priv->mbox_chan_id =3D data->mbox_chan_id; + priv->num_sensors =3D data->num_sensor_groups; + + platform_set_drvdata(pdev, priv); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), "Failed to ioremap resource\n"); + + regmap =3D devm_regmap_init_mmio(dev, base, &gs101_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n"); + + ret =3D devm_regmap_field_bulk_alloc(dev, regmap, priv->regmap_fields, + data->reg_fields, REG_INTPEND_COUNT); + if (ret) + return dev_err_probe(dev, ret, + "Unable to map syscon registers\n"); + + priv->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "Failed to get the clock\n"); + + priv->irq =3D platform_get_irq(pdev, 0); + if (priv->irq < 0) + return dev_err_probe(dev, priv->irq, "Failed to get irq\n"); + + ret =3D devm_request_threaded_irq(dev, priv->irq, NULL, + acpm_tmu_thread_fn, IRQF_ONESHOT, + dev_name(dev), priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request irq\n"); + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to resume device\n"); + + ret =3D acpm_handle->ops->tmu.init(acpm_handle, priv->mbox_chan_id); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to init TMU\n"); + goto err_pm_put; + } + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + + mutex_init(&sensor->lock); + sensor->group =3D &data->sensor_groups[i]; + sensor->priv =3D priv; + + sensor->tzd =3D devm_thermal_of_zone_register(dev, i, sensor, + &acpm_tmu_sensor_ops); + if (IS_ERR(sensor->tzd)) { + ret =3D PTR_ERR(sensor->tzd); + if (ret =3D=3D -ENODEV) { + sensor->tzd =3D NULL; + dev_dbg(dev, "Sensor %d not used in DT, skipping\n", i); + continue; + } + + ret =3D dev_err_probe(dev, ret, "Failed to register sensor %d\n", i); + goto err_pm_put; + } + + ret =3D devm_thermal_add_hwmon_sysfs(dev, sensor->tzd); + if (ret) + dev_warn(dev, "Failed to add hwmon sysfs!\n"); + } + + ret =3D acpm_tmu_control(priv, true); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to enable TMU\n"); + goto err_pm_put; + } + + pm_runtime_put_autosuspend(dev); + + return 0; + +err_pm_put: + pm_runtime_put_sync(dev); + return ret; +} + +static void acpm_tmu_remove(struct platform_device *pdev) +{ + struct acpm_tmu_priv *priv =3D platform_get_drvdata(pdev); + + /* Stop IRQ first to prevent race with thread_fn */ + disable_irq(priv->irq); + + acpm_tmu_control(priv, false); +} + +static int acpm_tmu_suspend(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops->tmu; + int ret; + + ret =3D acpm_tmu_control(priv, false); + if (ret) + return ret; + + /* APB clock not required for this specific msg */ + return ops->suspend(handle, priv->mbox_chan_id); +} + +static int acpm_tmu_resume(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops->tmu; + int ret; + + /* APB clock not required for this specific msg */ + ret =3D ops->resume(handle, priv->mbox_chan_id); + if (ret) + return ret; + + return acpm_tmu_control(priv, true); +} + +static int acpm_tmu_runtime_suspend(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static int acpm_tmu_runtime_resume(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + + return clk_prepare_enable(priv->clk); +} + +static const struct dev_pm_ops acpm_tmu_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(acpm_tmu_suspend, acpm_tmu_resume) + RUNTIME_PM_OPS(acpm_tmu_runtime_suspend, acpm_tmu_runtime_resume, NULL) +}; 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Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Alim Akhtar Cc: jyescas@google.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-hardening@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tudor Ambarus , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779713428; l=988; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=j2bS/h+sguKS9/qgJjI48x6qOqG+tkwy92XDxvAI8yY=; b=wGj/ffuuA+IGQ5pRdRuMChnrz10mIrbyGhYYPnunxYqt6E370YQjJM3fCVLiK7mzpJhj+Uf/C 82tUXkViWFXCDZJnfAcgY+c8oE7hfjIUHprgnbQm2BqPxOtrLUp7s5v X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add a MAINTAINERS entry for the Samsung Exynos ACPM thermal driver. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..7ea3b9d95ccd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23660,6 +23660,14 @@ F: drivers/clk/samsung/clk-acpm.c F: drivers/firmware/samsung/exynos-acpm* F: include/linux/firmware/samsung/exynos-acpm-protocol.h =20 +SAMSUNG EXYNOS ACPM THERMAL DRIVER +M: Tudor Ambarus +L: linux-kernel@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml +F: drivers/thermal/samsung/acpm-tmu.c + SAMSUNG EXYNOS MAILBOX DRIVER M: Tudor Ambarus L: linux-kernel@vger.kernel.org --=20 2.54.0.746.g67dd491aae-goog From nobody Mon Jun 8 23:57:49 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4451C3839A3 for ; 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[34.38.141.231]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454cfcaesm241824825e9.4.2026.05.25.05.50.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 05:50:31 -0700 (PDT) From: Tudor Ambarus Date: Mon, 25 May 2026 12:50:24 +0000 Subject: [PATCH v5 4/5] arm64: dts: exynos: gs101: Add thermal management unit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260525-acpm-tmu-v5-4-85fde739752e@linaro.org> References: <20260525-acpm-tmu-v5-0-85fde739752e@linaro.org> In-Reply-To: <20260525-acpm-tmu-v5-0-85fde739752e@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Alim Akhtar Cc: jyescas@google.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-hardening@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tudor Ambarus X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779713428; l=7065; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=z5Fhpx6IUPSYAgFvZrJUnVUKezx0DwqehwsV2CJ50Xs=; b=3kUfL+Zlfc10wC65GccpAO0ZPOAehBJ+CwGSYYMwyBlA4abF5mKa9zhEwrLJ/e2DuOv0D9zzK x9O1Mlwz+gUBKJp3v8i5DgWGhBfDRSqnCqBTzSTS4H5kch6hq6l7za7 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Thermal Management Unit (TMU) support for the Google GS101 SoC. Describe the TMU using a consolidated SoC node that includes memory resources for interrupt identification and a phandle to the ACPM IPC interface for functional control. Define thermal zones for the little, mid, and big CPU clusters, including associated trip points and cooling-device maps to enable thermal mitigation. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi | 136 +++++++++++++++++++= ++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 18 +++ 2 files changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi b/arch/arm64/= boot/dts/exynos/google/gs101-tmu.dtsi new file mode 100644 index 000000000000..b27d1a539ec2 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 TMU configurations device tree source + * + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include + +/ { + thermal-zones { + cpucl2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 0>; + + trips { + big_switch_on: big-switch-on { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + big_mitigate: big-mitigate { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + big_hot: big-hot { + temperature =3D <100000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + big_critical: big-critical { + temperature =3D <105000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&big_mitigate>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 1>; + + trips { + mid_switch_on: mid-switch-on { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + mid_mitigate: mid-mitigate { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + mid_hot: mid-hot { + temperature =3D <100000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mid_critical: mid-critical { + temperature =3D <105000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&mid_mitigate>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 2>; + + trips { + little_switch_on: little-switch-on { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + little_mitigate: little-mitigate { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + little_hot: little-hot { + temperature =3D <100000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + little_critical: little-critical { + temperature =3D <105000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&little_mitigate>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 86933f22647b..b6866ef99fb3 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -74,6 +74,7 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -86,6 +87,7 @@ cpu1: cpu@100 { compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -98,6 +100,7 @@ cpu2: cpu@200 { compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -110,6 +113,7 @@ cpu3: cpu@300 { compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -122,6 +126,7 @@ cpu4: cpu@400 { compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -134,6 +139,7 @@ cpu5: cpu@500 { compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -146,6 +152,7 @@ cpu6: cpu@600 { compatible =3D "arm,cortex-x1"; reg =3D <0x0600>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -158,6 +165,7 @@ cpu7: cpu@700 { compatible =3D "arm,cortex-x1"; reg =3D <0x0700>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -639,6 +647,15 @@ watchdog_cl1: watchdog@10070000 { status =3D "disabled"; }; =20 + tmu_top: thermal-sensor@100a0000 { + compatible =3D "google,gs101-tmu-top"; + reg =3D <0x100a0000 0x800>; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + samsung,acpm-ipc =3D <&acpm_ipc>; + #thermal-sensor-cells =3D <1>; + }; + trng: rng@10141400 { compatible =3D "google,gs101-trng", "samsung,exynos850-trng"; @@ -1862,3 +1879,4 @@ timer { }; =20 #include "gs101-pinctrl.dtsi" +#include "gs101-tmu.dtsi" --=20 2.54.0.746.g67dd491aae-goog From nobody Mon Jun 8 23:57:49 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BB773839B8 for ; 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[34.38.141.231]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454cfcaesm241824825e9.4.2026.05.25.05.50.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 05:50:32 -0700 (PDT) From: Tudor Ambarus Date: Mon, 25 May 2026 12:50:25 +0000 Subject: [PATCH v5 5/5] arm64: defconfig: enable Exynos ACPM thermal support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260525-acpm-tmu-v5-5-85fde739752e@linaro.org> References: <20260525-acpm-tmu-v5-0-85fde739752e@linaro.org> In-Reply-To: <20260525-acpm-tmu-v5-0-85fde739752e@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Alim Akhtar Cc: jyescas@google.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-hardening@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tudor Ambarus X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779713428; l=812; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=0Frkhb5ER+1m5KgNQbdP8ycXkPjLHDxA2xf3r2hyTAM=; b=ysDvGnb5sGnYo8XyHtqcLtMEVBuxYqkwONOnmQLPxdEJXX+Z8JRyBK2v1SJeQkFgvjbrITrcE +ypUtdm16g9B+l1i2lE9lC28ZQzQWSfcXVHHHo8co3aVihoSxuORly3 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Enable the Exynos ACPM thermal driver (CONFIG_EXYNOS_ACPM_THERMAL) to allow temperature monitoring and thermal management on Samsung Exynos SoCs that use the Alive Clock and Power Manager (ACPM) protocol. Signed-off-by: Tudor Ambarus --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d905a0777f93..3fe76a4c2633 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -793,6 +793,7 @@ CONFIG_BCM2711_THERMAL=3Dm CONFIG_BCM2835_THERMAL=3Dm CONFIG_BRCMSTB_THERMAL=3Dm CONFIG_EXYNOS_THERMAL=3Dy +CONFIG_EXYNOS_ACPM_THERMAL=3Dm CONFIG_TEGRA_SOCTHERM=3Dm CONFIG_TEGRA_BPMP_THERMAL=3Dm CONFIG_GENERIC_ADC_THERMAL=3Dm --=20 2.54.0.746.g67dd491aae-goog