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Sun, 24 May 2026 12:39:00 -0700 (PDT) From: Wadim Mueller To: wbg@kernel.org Cc: krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wadim Mueller Subject: [PATCH v5 1/3] dt-bindings: counter: add gpio-counter binding Date: Sun, 24 May 2026 21:38:44 +0200 Message-ID: <20260524193846.19216-2-wafgo01@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260524193846.19216-1-wafgo01@gmail.com> References: <20260515153616.157605-1-wafgo01@gmail.com> <20260524193846.19216-1-wafgo01@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a binding for a generic GPIO-based counter. Two GPIOs (signal-a, signal-b) drive the counter; an optional index GPIO loads a preset. The counter function (quadrature, pulse-direction, increase/decrease) is choosen at runtime through the counter sysfs interface. Signed-off-by: Wadim Mueller Acked-by: Conor Dooley --- .../bindings/counter/gpio-counter.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/gpio-counter.= yaml diff --git a/Documentation/devicetree/bindings/counter/gpio-counter.yaml b/= Documentation/devicetree/bindings/counter/gpio-counter.yaml new file mode 100644 index 000000000..4bd972b61 --- /dev/null +++ b/Documentation/devicetree/bindings/counter/gpio-counter.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/gpio-counter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO-based Counter + +maintainers: + - Wadim Mueller + +description: + GPIO-based software counter. Decodes up to two primary signals (A + and B) and an optional index pulse via edge-triggered GPIO interrupts + into a count. Supports quadrature X1/X2/X4, pulse-direction, and + pure increase/decrease modes; the mode is selected at runtime via + the counter sysfs ABI. + +properties: + compatible: + const: gpio-counter + + signal-a-gpios: + maxItems: 1 + description: + Signal A input (encoder phase A in quadrature modes; pulse + input in pulse-direction and increase/decrease modes). + + signal-b-gpios: + maxItems: 1 + description: + Signal B input (encoder phase B in quadrature modes; direction + input in pulse-direction mode; unused in increase/decrease). + + index-gpios: + maxItems: 1 + description: + Optional index (Z) input. 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Sun, 24 May 2026 12:39:03 -0700 (PDT) Received: from sefo-laptop ([2a02:8071:50c5:5c0::361b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45eb6c9ba2esm22339674f8f.8.2026.05.24.12.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 May 2026 12:39:02 -0700 (PDT) From: Wadim Mueller To: wbg@kernel.org Cc: krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wadim Mueller Subject: [PATCH v5 2/3] counter: add GPIO-based counter driver Date: Sun, 24 May 2026 21:38:45 +0200 Message-ID: <20260524193846.19216-3-wafgo01@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260524193846.19216-1-wafgo01@gmail.com> References: <20260515153616.157605-1-wafgo01@gmail.com> <20260524193846.19216-1-wafgo01@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a platform driver that turns plain GPIOs into a counter device. Edge interrupts on the signal-a, signal-b (and optional index) lines are decoded in software using a 2-bit Gray-code parity trick for the quadrature X4 mode and direct edge checks for the other modes. Supports COUNTER_FUNCTION_QUADRATURE_X1_{A,B} / X2_{A,B} / X4, PULSE_DIRECTION, INCREASE and DECREASE. Sleepable GPIO providers (I2C/SPI expanders) are rejected at probe time becouse the ISRs run in hardirq context. Signed-off-by: Wadim Mueller --- drivers/counter/Kconfig | 17 + drivers/counter/Makefile | 1 + drivers/counter/gpio-counter.c | 744 +++++++++++++++++++++++++++++++++ 3 files changed, 762 insertions(+) create mode 100644 drivers/counter/gpio-counter.c diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index d30d22dfe..c20044032 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -68,6 +68,23 @@ config INTEL_QEP To compile this driver as a module, choose M here: the module will be called intel-qep. =20 +config GPIO_COUNTER + tristate "GPIO-based counter driver" + depends on GPIOLIB + help + Select this option to enable the GPIO-based counter driver. It + reads A/B and an optional index signal via edge-triggered GPIO + interrupts and decodes them according to the selected mode: + Quadrature X1/X2/X4 (rotary or linear encoders), pulse-direction, + and pure increase / decrease pulse counters. + + This is useful on SoCs that lack a dedicated hardware quadrature + decoder or pulse counter, or where the signals are wired to + generic GPIO pins rather than to a dedicated peripheral. + + To compile this driver as a module, choose M here: the + module will be called gpio-counter. + config INTERRUPT_CNT tristate "Interrupt counter driver" depends on GPIOLIB diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index fa3c1d08f..3959d69fb 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_STM32_TIMER_CNT) +=3D stm32-timer-cnt.o obj-$(CONFIG_STM32_LPTIMER_CNT) +=3D stm32-lptimer-cnt.o obj-$(CONFIG_TI_EQEP) +=3D ti-eqep.o obj-$(CONFIG_FTM_QUADDEC) +=3D ftm-quaddec.o +obj-$(CONFIG_GPIO_COUNTER) +=3D gpio-counter.o obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) +=3D microchip-tcb-capture.o obj-$(CONFIG_INTEL_QEP) +=3D intel-qep.o obj-$(CONFIG_TI_ECAP_CAPTURE) +=3D ti-ecap-capture.o diff --git a/drivers/counter/gpio-counter.c b/drivers/counter/gpio-counter.c new file mode 100644 index 000000000..f50cec33a --- /dev/null +++ b/drivers/counter/gpio-counter.c @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GPIO-based Counter Driver + * + * Decodes A/B (and optional Index) signals from GPIO lines in software. + * Supports quadrature X1/X2/X4, pulse-direction, and pure + * increase/decrease modes. + * + * Copyright (C) 2026 CMBlu Energy AG + * Author: Wadim Mueller + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum gpio_counter_signal_id { + GPIO_COUNTER_SIGNAL_A =3D 0, + GPIO_COUNTER_SIGNAL_B, + GPIO_COUNTER_SIGNAL_INDEX, +}; + +struct gpio_counter_priv { + struct gpio_desc *gpio_a; + struct gpio_desc *gpio_b; + struct gpio_desc *gpio_index; + + int irq_a; + int irq_b; + int irq_index; + + spinlock_t lock; /* protects count, ceiling, preset, function, direction,= enabled */ + + u64 count; + u64 ceiling; + u64 preset; + bool preset_enabled; + bool enabled; + enum counter_count_direction direction; + enum counter_function function; + + int prev_a; + int prev_b; + + struct counter_count cnts[1]; + struct counter_signal signals[3]; + struct counter_synapse synapses[3]; +}; + +/* X4 decode via 2-bit Gray-code parity. */ +#define GPIO_COUNTER_STATE_CHANGED(pa, pb, ca, cb) ((pa) ^ (pb) ^ (ca) ^ (= cb)) +#define GPIO_COUNTER_GET_DIRECTION(pb, ca) \ + (((pb) ^ (ca)) ? COUNTER_COUNT_DIRECTION_FORWARD : \ + COUNTER_COUNT_DIRECTION_BACKWARD) + +static void gpio_counter_update(struct gpio_counter_priv *priv, int delta) +{ + if (delta > 0) { + priv->direction =3D COUNTER_COUNT_DIRECTION_FORWARD; + if (priv->count >=3D priv->ceiling) + return; + priv->count++; + } else if (delta < 0) { + priv->direction =3D COUNTER_COUNT_DIRECTION_BACKWARD; + if (priv->count =3D=3D 0) + return; + priv->count--; + } +} + +static int gpio_counter_a_delta(struct gpio_counter_priv *priv, int a, int= b, + int prev_a, int prev_b) +{ + enum counter_count_direction dir; + + switch (priv->function) { + case COUNTER_FUNCTION_QUADRATURE_X4: + if (!GPIO_COUNTER_STATE_CHANGED(prev_a, prev_b, a, b)) + return 0; + dir =3D GPIO_COUNTER_GET_DIRECTION(prev_b, a); + return (dir =3D=3D COUNTER_COUNT_DIRECTION_FORWARD) ? 1 : -1; + + case COUNTER_FUNCTION_QUADRATURE_X2_A: + return (a =3D=3D b) ? -1 : 1; + + case COUNTER_FUNCTION_QUADRATURE_X1_A: + if (a && priv->direction =3D=3D COUNTER_COUNT_DIRECTION_FORWARD) + return 1; + if (!a && priv->direction =3D=3D COUNTER_COUNT_DIRECTION_BACKWARD) + return -1; + return 0; + + case COUNTER_FUNCTION_PULSE_DIRECTION: + if (!prev_a && a) + return b ? -1 : 1; + return 0; + + case COUNTER_FUNCTION_INCREASE: + if (!prev_a && a) + return 1; + return 0; + + case COUNTER_FUNCTION_DECREASE: + if (!prev_a && a) + return -1; + return 0; + + default: + return 0; + } +} + +static int gpio_counter_b_delta(struct gpio_counter_priv *priv, int a, int= b, + int prev_a, int prev_b) +{ + enum counter_count_direction dir; + + switch (priv->function) { + case COUNTER_FUNCTION_QUADRATURE_X4: + if (!GPIO_COUNTER_STATE_CHANGED(prev_a, prev_b, a, b)) + return 0; + dir =3D GPIO_COUNTER_GET_DIRECTION(prev_b, a); + return (dir =3D=3D COUNTER_COUNT_DIRECTION_FORWARD) ? 1 : -1; + + case COUNTER_FUNCTION_QUADRATURE_X2_B: + return (a =3D=3D b) ? 1 : -1; + + case COUNTER_FUNCTION_QUADRATURE_X1_B: + if (b && priv->direction =3D=3D COUNTER_COUNT_DIRECTION_FORWARD) + return 1; + if (!b && priv->direction =3D=3D COUNTER_COUNT_DIRECTION_BACKWARD) + return -1; + return 0; + + default: + return 0; + } +} + +static irqreturn_t gpio_counter_a_isr(int irq, void *dev_id) +{ + struct counter_device *counter =3D dev_id; + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + int a, b, delta; + + /* !! normalises away negative gpiod_get_value() errors. */ + a =3D !!gpiod_get_value(priv->gpio_a); + b =3D !!gpiod_get_value(priv->gpio_b); + + spin_lock_irqsave(&priv->lock, flags); + + delta =3D gpio_counter_a_delta(priv, a, b, priv->prev_a, priv->prev_b); + gpio_counter_update(priv, delta); + + priv->prev_a =3D a; + priv->prev_b =3D b; + + spin_unlock_irqrestore(&priv->lock, flags); + + counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); + + return IRQ_HANDLED; +} + +static irqreturn_t gpio_counter_b_isr(int irq, void *dev_id) +{ + struct counter_device *counter =3D dev_id; + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + int a, b, delta; + + a =3D !!gpiod_get_value(priv->gpio_a); + b =3D !!gpiod_get_value(priv->gpio_b); + + spin_lock_irqsave(&priv->lock, flags); + + delta =3D gpio_counter_b_delta(priv, a, b, priv->prev_a, priv->prev_b); + gpio_counter_update(priv, delta); + + priv->prev_a =3D a; + priv->prev_b =3D b; + + spin_unlock_irqrestore(&priv->lock, flags); + + counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); + + return IRQ_HANDLED; +} + +static irqreturn_t gpio_counter_index_isr(int irq, void *dev_id) +{ + struct counter_device *counter =3D dev_id; + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + if (priv->preset_enabled) { + priv->count =3D priv->preset; + if (priv->count > priv->ceiling) + priv->count =3D priv->ceiling; + } + + spin_unlock_irqrestore(&priv->lock, flags); + + counter_push_event(counter, COUNTER_EVENT_INDEX, 0); + + return IRQ_HANDLED; +} + +static int gpio_counter_count_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *val =3D priv->count; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_counter_count_write(struct counter_device *counter, + struct counter_count *count, u64 val) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + if (val > priv->ceiling) { + spin_unlock_irqrestore(&priv->lock, flags); + return -EINVAL; + } + + priv->count =3D val; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const enum counter_function gpio_counter_functions[] =3D { + COUNTER_FUNCTION_INCREASE, COUNTER_FUNCTION_DECREASE, + COUNTER_FUNCTION_PULSE_DIRECTION, COUNTER_FUNCTION_QUADRATURE_X1_A, + COUNTER_FUNCTION_QUADRATURE_X1_B, COUNTER_FUNCTION_QUADRATURE_X2_A, + COUNTER_FUNCTION_QUADRATURE_X2_B, COUNTER_FUNCTION_QUADRATURE_X4, +}; + +static int gpio_counter_function_read(struct counter_device *counter, + struct counter_count *count, + enum counter_function *function) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *function =3D priv->function; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_counter_function_write(struct counter_device *counter, + struct counter_count *count, + enum counter_function function) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + priv->function =3D function; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const enum counter_synapse_action gpio_counter_synapse_actions[] = =3D { + COUNTER_SYNAPSE_ACTION_NONE, + COUNTER_SYNAPSE_ACTION_RISING_EDGE, + COUNTER_SYNAPSE_ACTION_FALLING_EDGE, + COUNTER_SYNAPSE_ACTION_BOTH_EDGES, +}; + +static const enum counter_synapse_action gpio_counter_index_synapse_action= s[] =3D { + COUNTER_SYNAPSE_ACTION_NONE, + COUNTER_SYNAPSE_ACTION_RISING_EDGE, +}; + +static int gpio_counter_action_read(struct counter_device *counter, + struct counter_count *count, + struct counter_synapse *synapse, + enum counter_synapse_action *action) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + enum gpio_counter_signal_id signal_id =3D synapse->signal->id; + enum counter_function function; + enum counter_count_direction direction; + unsigned long flags; + + if (signal_id =3D=3D GPIO_COUNTER_SIGNAL_INDEX) { + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + return 0; + } + + spin_lock_irqsave(&priv->lock, flags); + function =3D priv->function; + direction =3D priv->direction; + spin_unlock_irqrestore(&priv->lock, flags); + + *action =3D COUNTER_SYNAPSE_ACTION_NONE; + + switch (function) { + case COUNTER_FUNCTION_QUADRATURE_X4: + *action =3D COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + return 0; + + case COUNTER_FUNCTION_QUADRATURE_X2_A: + if (signal_id =3D=3D GPIO_COUNTER_SIGNAL_A) + *action =3D COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + return 0; + + case COUNTER_FUNCTION_QUADRATURE_X2_B: + if (signal_id =3D=3D GPIO_COUNTER_SIGNAL_B) + *action =3D COUNTER_SYNAPSE_ACTION_BOTH_EDGES; + return 0; + + case COUNTER_FUNCTION_QUADRATURE_X1_A: + if (signal_id =3D=3D GPIO_COUNTER_SIGNAL_A) { + if (direction =3D=3D COUNTER_COUNT_DIRECTION_FORWARD) + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + else + *action =3D COUNTER_SYNAPSE_ACTION_FALLING_EDGE; + } + return 0; + + case COUNTER_FUNCTION_QUADRATURE_X1_B: + if (signal_id =3D=3D GPIO_COUNTER_SIGNAL_B) { + if (direction =3D=3D COUNTER_COUNT_DIRECTION_FORWARD) + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + else + *action =3D COUNTER_SYNAPSE_ACTION_FALLING_EDGE; + } + return 0; + + case COUNTER_FUNCTION_PULSE_DIRECTION: + case COUNTER_FUNCTION_INCREASE: + case COUNTER_FUNCTION_DECREASE: + if (signal_id =3D=3D GPIO_COUNTER_SIGNAL_A) + *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; + return 0; + + default: + return -EINVAL; + } +} + +static int gpio_counter_signal_read(struct counter_device *counter, + struct counter_signal *signal, + enum counter_signal_level *level) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + struct gpio_desc *gpio; + int ret; + + switch (signal->id) { + case GPIO_COUNTER_SIGNAL_A: + gpio =3D priv->gpio_a; + break; + case GPIO_COUNTER_SIGNAL_B: + gpio =3D priv->gpio_b; + break; + case GPIO_COUNTER_SIGNAL_INDEX: + gpio =3D priv->gpio_index; + break; + default: + return -EINVAL; + } + + ret =3D gpiod_get_value(gpio); + if (ret < 0) + return ret; + + *level =3D ret ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; + return 0; +} + +static int gpio_counter_watch_validate(struct counter_device *counter, + const struct counter_watch *watch) +{ + if (watch->channel !=3D 0) + return -EINVAL; + + switch (watch->event) { + case COUNTER_EVENT_CHANGE_OF_STATE: + case COUNTER_EVENT_INDEX: + return 0; + default: + return -EINVAL; + } +} + +static const struct counter_ops gpio_counter_ops =3D { + .count_read =3D gpio_counter_count_read, + .count_write =3D gpio_counter_count_write, + .function_read =3D gpio_counter_function_read, + .function_write =3D gpio_counter_function_write, + .action_read =3D gpio_counter_action_read, + .signal_read =3D gpio_counter_signal_read, + .watch_validate =3D gpio_counter_watch_validate, +}; + +static int gpio_counter_ceiling_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *val =3D priv->ceiling; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_counter_ceiling_write(struct counter_device *counter, + struct counter_count *count, u64 val) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + /* Leave count untouched on shrink; matches intel-qep / ti-eqep / stm32-t= imer-cnt. */ + spin_lock_irqsave(&priv->lock, flags); + priv->ceiling =3D val; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_counter_enable_read(struct counter_device *counter, + struct counter_count *count, u8 *enable) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *enable =3D priv->enabled; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_counter_enable_write(struct counter_device *counter, + struct counter_count *count, u8 enable) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + bool want =3D enable; + bool changed; + + spin_lock_irqsave(&priv->lock, flags); + changed =3D priv->enabled !=3D want; + if (changed) + priv->enabled =3D want; + spin_unlock_irqrestore(&priv->lock, flags); + + if (!changed) + return 0; + + if (want) { + enable_irq(priv->irq_a); + enable_irq(priv->irq_b); + if (priv->irq_index) + enable_irq(priv->irq_index); + } else { + disable_irq(priv->irq_a); + disable_irq(priv->irq_b); + if (priv->irq_index) + disable_irq(priv->irq_index); + } + + return 0; +} + +static int gpio_counter_direction_read(struct counter_device *counter, + struct counter_count *count, + u32 *direction) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *direction =3D priv->direction; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_counter_preset_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *val =3D priv->preset; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_counter_preset_write(struct counter_device *counter, + struct counter_count *count, u64 val) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + int ret =3D 0; + + spin_lock_irqsave(&priv->lock, flags); + if (val > priv->ceiling) { + ret =3D -EINVAL; + goto out; + } + priv->preset =3D val; +out: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int gpio_counter_preset_enable_read(struct counter_device *counter, + struct counter_count *count, u8 *val) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + *val =3D priv->preset_enabled; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int gpio_counter_preset_enable_write(struct counter_device *counter, + struct counter_count *count, u8 val) +{ + struct gpio_counter_priv *priv =3D counter_priv(counter); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + priv->preset_enabled =3D val; + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static struct counter_comp gpio_counter_count_ext[] =3D { + COUNTER_COMP_CEILING(gpio_counter_ceiling_read, + gpio_counter_ceiling_write), + COUNTER_COMP_ENABLE(gpio_counter_enable_read, + gpio_counter_enable_write), + COUNTER_COMP_DIRECTION(gpio_counter_direction_read), + COUNTER_COMP_PRESET(gpio_counter_preset_read, + gpio_counter_preset_write), + COUNTER_COMP_PRESET_ENABLE(gpio_counter_preset_enable_read, + gpio_counter_preset_enable_write), +}; + +static int gpio_counter_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct counter_device *counter; + struct gpio_counter_priv *priv; + bool has_index; + int num_signals; + int num_synapses; + int ret; + + counter =3D devm_counter_alloc(dev, sizeof(*priv)); + if (!counter) + return -ENOMEM; + + priv =3D counter_priv(counter); + spin_lock_init(&priv->lock); + + priv->gpio_a =3D devm_gpiod_get(dev, "signal-a", GPIOD_IN); + if (IS_ERR(priv->gpio_a)) + return dev_err_probe(dev, PTR_ERR(priv->gpio_a), + "failed to get signal-a GPIO\n"); + + priv->gpio_b =3D devm_gpiod_get(dev, "signal-b", GPIOD_IN); + if (IS_ERR(priv->gpio_b)) + return dev_err_probe(dev, PTR_ERR(priv->gpio_b), + "failed to get signal-b GPIO\n"); + + priv->gpio_index =3D devm_gpiod_get_optional(dev, "index", GPIOD_IN); + if (IS_ERR(priv->gpio_index)) + return dev_err_probe(dev, PTR_ERR(priv->gpio_index), + "failed to get index GPIO\n"); + + has_index =3D !!priv->gpio_index; + + if (gpiod_cansleep(priv->gpio_a) || gpiod_cansleep(priv->gpio_b) || + (has_index && gpiod_cansleep(priv->gpio_index))) + return dev_err_probe(dev, -EINVAL, + "GPIO controller may sleep; not supported in IRQ context\n"); + + priv->irq_a =3D gpiod_to_irq(priv->gpio_a); + if (priv->irq_a < 0) + return dev_err_probe(dev, priv->irq_a, + "failed to get IRQ for signal-a\n"); + + priv->irq_b =3D gpiod_to_irq(priv->gpio_b); + if (priv->irq_b < 0) + return dev_err_probe(dev, priv->irq_b, + "failed to get IRQ for signal-b\n"); + + if (has_index) { + priv->irq_index =3D gpiod_to_irq(priv->gpio_index); + if (priv->irq_index < 0) + return dev_err_probe(dev, priv->irq_index, + "failed to get IRQ for index\n"); + } + + priv->prev_a =3D !!gpiod_get_value(priv->gpio_a); + priv->prev_b =3D !!gpiod_get_value(priv->gpio_b); + + priv->function =3D COUNTER_FUNCTION_QUADRATURE_X4; + priv->direction =3D COUNTER_COUNT_DIRECTION_FORWARD; + priv->ceiling =3D U64_MAX; + priv->enabled =3D false; + + num_signals =3D has_index ? 3 : 2; + num_synapses =3D num_signals; + + priv->signals[GPIO_COUNTER_SIGNAL_A].id =3D GPIO_COUNTER_SIGNAL_A; + priv->signals[GPIO_COUNTER_SIGNAL_A].name =3D "Signal A"; + + priv->signals[GPIO_COUNTER_SIGNAL_B].id =3D GPIO_COUNTER_SIGNAL_B; + priv->signals[GPIO_COUNTER_SIGNAL_B].name =3D "Signal B"; + + priv->synapses[0].actions_list =3D gpio_counter_synapse_actions; + priv->synapses[0].num_actions =3D + ARRAY_SIZE(gpio_counter_synapse_actions); + priv->synapses[0].signal =3D &priv->signals[GPIO_COUNTER_SIGNAL_A]; + + priv->synapses[1].actions_list =3D gpio_counter_synapse_actions; + priv->synapses[1].num_actions =3D + ARRAY_SIZE(gpio_counter_synapse_actions); + priv->synapses[1].signal =3D &priv->signals[GPIO_COUNTER_SIGNAL_B]; + + if (has_index) { + priv->signals[GPIO_COUNTER_SIGNAL_INDEX].id =3D + GPIO_COUNTER_SIGNAL_INDEX; + priv->signals[GPIO_COUNTER_SIGNAL_INDEX].name =3D "Index"; + + priv->synapses[2].actions_list =3D + gpio_counter_index_synapse_actions; + priv->synapses[2].num_actions =3D + ARRAY_SIZE(gpio_counter_index_synapse_actions); + priv->synapses[2].signal =3D + &priv->signals[GPIO_COUNTER_SIGNAL_INDEX]; + } + + priv->cnts[0].id =3D 0; + priv->cnts[0].name =3D "Count"; + priv->cnts[0].functions_list =3D gpio_counter_functions; + priv->cnts[0].num_functions =3D ARRAY_SIZE(gpio_counter_functions); + priv->cnts[0].synapses =3D priv->synapses; + priv->cnts[0].num_synapses =3D num_synapses; + priv->cnts[0].ext =3D gpio_counter_count_ext; + priv->cnts[0].num_ext =3D ARRAY_SIZE(gpio_counter_count_ext); + + counter->name =3D dev_name(dev); + counter->parent =3D dev; + counter->ops =3D &gpio_counter_ops; + counter->signals =3D priv->signals; + counter->num_signals =3D num_signals; + counter->counts =3D priv->cnts; + counter->num_counts =3D ARRAY_SIZE(priv->cnts); + + ret =3D devm_request_irq(dev, priv->irq_a, gpio_counter_a_isr, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_NO_AUTOEN, + "gpio-counter-a", counter); + if (ret) + return dev_err_probe(dev, ret, + "failed to request IRQ for signal-a\n"); + + ret =3D devm_request_irq(dev, priv->irq_b, gpio_counter_b_isr, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_NO_AUTOEN, + "gpio-counter-b", counter); + if (ret) + return dev_err_probe(dev, ret, + "failed to request IRQ for signal-b\n"); + + if (has_index) { + ret =3D devm_request_irq(dev, priv->irq_index, + gpio_counter_index_isr, + IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, + "gpio-counter-index", counter); + if (ret) + return dev_err_probe(dev, ret, + "failed to request IRQ for index\n"); + } + + ret =3D devm_counter_add(dev, counter); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add counter\n"); + + dev_info(dev, "GPIO counter registered (signals: A, B%s)\n", + has_index ? ", Index" : ""); + + return 0; +} + +static const struct of_device_id gpio_counter_of_match[] =3D { + { .compatible =3D "gpio-counter" }, + {} +}; +MODULE_DEVICE_TABLE(of, gpio_counter_of_match); + +static struct platform_driver gpio_counter_driver =3D { + .probe =3D gpio_counter_probe, + .driver =3D { + .name =3D "gpio-counter", + .of_match_table =3D gpio_counter_of_match, + }, +}; +module_platform_driver(gpio_counter_driver); + +MODULE_ALIAS("platform:gpio-counter"); +MODULE_AUTHOR("Wadim Mueller "); +MODULE_DESCRIPTION("GPIO-based counter driver (quadrature, pulse-direction= , increase/decrease)"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("COUNTER"); --=20 2.52.0 From nobody Tue Jun 9 00:59:03 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A538A316189 for ; Sun, 24 May 2026 19:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 24 May 2026 12:39:05 -0700 (PDT) Received: from sefo-laptop ([2a02:8071:50c5:5c0::361b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45eb6c9ba2esm22339674f8f.8.2026.05.24.12.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 May 2026 12:39:04 -0700 (PDT) From: Wadim Mueller To: wbg@kernel.org Cc: krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wadim Mueller Subject: [PATCH v5 3/3] MAINTAINERS: add entry for GPIO counter driver Date: Sun, 24 May 2026 21:38:46 +0200 Message-ID: <20260524193846.19216-4-wafgo01@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260524193846.19216-1-wafgo01@gmail.com> References: <20260515153616.157605-1-wafgo01@gmail.com> <20260524193846.19216-1-wafgo01@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Cover the gpio-counter driver and its device-tree binding. Signed-off-by: Wadim Mueller --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 06a8c7457..14f1a4e9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10984,6 +10984,13 @@ S: Supported F: Documentation/admin-guide/gpio/gpio-aggregator.rst F: drivers/gpio/gpio-aggregator.c =20 +GPIO COUNTER DRIVER +M: Wadim Mueller +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/counter/gpio-counter.yaml +F: drivers/counter/gpio-counter.c + GPIO IR Transmitter M: Sean Young L: linux-media@vger.kernel.org --=20 2.52.0