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charset="utf-8" From: "Guo Ren (Alibaba DAMO Academy)" Add nr_guest_files in per-HART local config to represent the number of guest files available on a particular HART whereas the nr_guest_files in the global config represents the number of guest files available across all HARTs. This allows KVM RISC-V to use nr_guest_files from per-HART local config for asymmetric big.Little systems. Signed-off-by: Guo Ren (Alibaba DAMO Academy) Acked-by: Thomas Gleixner Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-state.c | 9 ++++----- include/linux/irqchip/riscv-imsic.h | 5 ++++- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index e3ed874d89e7..b8d1bbbf42f7 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -920,13 +920,12 @@ int __init imsic_setup_state(struct fwnode_handle *fw= node, void *opaque) local->msi_va =3D mmios_va[index] + reloff; =20 /* - * KVM uses global->nr_guest_files to determine the available guest - * interrupt files on each CPU. Take the minimum number of guest - * interrupt files across all CPUs to avoid KVM incorrectly allocating - * an unexisted or unmapped guest interrupt file on some CPUs. + * KVM uses both local->nr_guest_files and global->nr_guest_files + * to determine the available guest interrupt files on each CPU. */ nr_guest_files =3D (resource_size(&mmios[index]) - reloff) / IMSIC_MMIO_= PAGE_SZ - 1; - global->nr_guest_files =3D min(global->nr_guest_files, nr_guest_files); + local->nr_guest_files =3D min((BIT(global->guest_index_bits) - 1), nr_gu= est_files); + global->nr_guest_files =3D min(global->nr_guest_files, local->nr_guest_f= iles); =20 nr_handlers++; } diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h index 4b348836de7a..61af3a5bea09 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -40,6 +40,9 @@ struct imsic_local_config { phys_addr_t msi_pa; void __iomem *msi_va; + + /* Number of guest interrupt files per-HART */ + u32 nr_guest_files; }; =20 struct imsic_global_config { @@ -68,7 +71,7 @@ struct imsic_global_config { /* Number of guest interrupt identities */ u32 nr_guest_ids; =20 - /* Number of guest interrupt files per core */ + /* Number of guest interrupt files across all HARTs */ u32 nr_guest_files; =20 /* Per-CPU IMSIC addresses */ --=20 2.43.0 From nobody Sun May 24 17:49:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 071E336A02F; Sun, 24 May 2026 13:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779628879; cv=none; b=ZIbFJdFQVX7V0GdOsyopFQuYT3AHGlYe5KwzvWN3cfPMKR57TqNNBrdBB2He14QYH8447iYyJQiw/qcyLdFKIzTR57AmplySHVOKsbN6wQIStqhmImBcfQfHCqjqPlncsEtrxL+xxjk+HJ9dCenlIB84yz3weM0gtU6BBgeF0FE= ARC-Message-Signature: i=1; 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charset="utf-8" From: "Guo Ren (Alibaba DAMO Academy)" Previously, the number of Hypervisor Guest External Interrupt (HGEI) lines was stored in a single global variable `kvm_riscv_aia_nr_hgei` and assumed to be the same for all HARTs. This assumption does not hold on heterogeneous RISC-V SoCs where different cores may expose different HGEIE CSR widths. Introduce `nr_hgei` field into the per-CPU `struct aia_hgei_control` and probe the actual supported HGEI count for the current HART in `kvm_riscv_aia_enable()` using the standard RISC-V CSR probe technique: csr_write(CSR_HGEIE, -1UL); nr =3D fls_long(csr_read(CSR_HGEIE)); if (nr) nr--; All HGEI allocation, free and disable paths (`kvm_riscv_aia_free_hgei()`, `kvm_riscv_aia_disable()`, etc.) now use the per-CPU value instead of the global one. The global `kvm_riscv_aia_nr_hgei` now represents the minimum number of HGEI lines across HARTs and can be used to check whether HGEI support is available or not. This makes KVM AIA robust on big.LITTLE-style asymmetric platforms. Signed-off-by: Guo Ren (Alibaba DAMO Academy) Signed-off-by: Anup Patel --- arch/riscv/kvm/aia.c | 67 +++++++++++++++++++++++++++++--------------- 1 file changed, 44 insertions(+), 23 deletions(-) diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index 5ec503288555..c289d8999aaf 100644 --- a/arch/riscv/kvm/aia.c +++ b/arch/riscv/kvm/aia.c @@ -23,6 +23,7 @@ struct aia_hgei_control { raw_spinlock_t lock; unsigned long free_bitmap; struct kvm_vcpu *owners[BITS_PER_LONG]; + unsigned int nr_hgei; }; static DEFINE_PER_CPU(struct aia_hgei_control, aia_hgei); static int hgei_parent_irq; @@ -452,7 +453,7 @@ void kvm_riscv_aia_free_hgei(int cpu, int hgei) =20 raw_spin_lock_irqsave(&hgctrl->lock, flags); =20 - if (hgei > 0 && hgei <=3D kvm_riscv_aia_nr_hgei) { + if (hgei > 0 && hgei <=3D hgctrl->nr_hgei) { if (!(hgctrl->free_bitmap & BIT(hgei))) { hgctrl->free_bitmap |=3D BIT(hgei); hgctrl->owners[hgei] =3D NULL; @@ -486,21 +487,8 @@ static irqreturn_t hgei_interrupt(int irq, void *dev_i= d) =20 static int aia_hgei_init(void) { - int cpu, rc; + int rc; struct irq_domain *domain; - struct aia_hgei_control *hgctrl; - - /* Initialize per-CPU guest external interrupt line management */ - for_each_possible_cpu(cpu) { - hgctrl =3D per_cpu_ptr(&aia_hgei, cpu); - raw_spin_lock_init(&hgctrl->lock); - if (kvm_riscv_aia_nr_hgei) { - hgctrl->free_bitmap =3D - BIT(kvm_riscv_aia_nr_hgei + 1) - 1; - hgctrl->free_bitmap &=3D ~BIT(0); - } else - hgctrl->free_bitmap =3D 0; - } =20 /* Skip SGEI interrupt setup for zero guest external interrupts */ if (!kvm_riscv_aia_nr_hgei) @@ -545,9 +533,48 @@ static void aia_hgei_exit(void) =20 void kvm_riscv_aia_enable(void) { + const struct imsic_global_config *gc; + const struct imsic_local_config *lc; + struct aia_hgei_control *hgctrl; + if (!kvm_riscv_aia_available()) return; =20 + gc =3D imsic_get_global_config(); + lc =3D (gc) ? this_cpu_ptr(gc->local) : NULL; + hgctrl =3D this_cpu_ptr(&aia_hgei); + + /* Figure-out number of bits in HGEIE */ + csr_write(CSR_HGEIE, -1UL); + hgctrl->nr_hgei =3D fls_long(csr_read(CSR_HGEIE)); + csr_write(CSR_HGEIE, 0); + if (hgctrl->nr_hgei) + hgctrl->nr_hgei--; + + /* + * Number of usable per-HART HGEI lines should be minimum of + * per-HART IMSIC guest files and number of bits in HGEIE. + */ + if (lc) + hgctrl->nr_hgei =3D min((ulong)hgctrl->nr_hgei, lc->nr_guest_files); + else + hgctrl->nr_hgei =3D 0; + + /* + * The global number of usable HGEI lines should be minimum + * across all HARTs. + */ + kvm_riscv_aia_nr_hgei =3D min(kvm_riscv_aia_nr_hgei, hgctrl->nr_hgei); + + if (hgctrl->nr_hgei) { + hgctrl->free_bitmap =3D BIT(hgctrl->nr_hgei + 1) - 1; + hgctrl->free_bitmap &=3D ~BIT(0); + } else { + hgctrl->free_bitmap =3D 0; + } + + raw_spin_lock_init(&hgctrl->lock); + csr_write(CSR_HVICTL, aia_hvictl_value(false)); csr_write(CSR_HVIPRIO1, 0x0); csr_write(CSR_HVIPRIO2, 0x0); @@ -588,7 +615,7 @@ void kvm_riscv_aia_disable(void) =20 raw_spin_lock_irqsave(&hgctrl->lock, flags); =20 - for (i =3D 0; i <=3D kvm_riscv_aia_nr_hgei; i++) { + for (i =3D 0; i <=3D hgctrl->nr_hgei; i++) { vcpu =3D hgctrl->owners[i]; if (!vcpu) continue; @@ -634,14 +661,8 @@ int kvm_riscv_aia_init(void) csr_write(CSR_HGEIE, 0); if (kvm_riscv_aia_nr_hgei) kvm_riscv_aia_nr_hgei--; - - /* - * Number of usable HGEI lines should be minimum of per-HART - * IMSIC guest files and number of bits in HGEIE - */ if (gc) - kvm_riscv_aia_nr_hgei =3D min((ulong)kvm_riscv_aia_nr_hgei, - gc->nr_guest_files); + kvm_riscv_aia_nr_hgei =3D min(kvm_riscv_aia_nr_hgei, gc->nr_guest_files); else kvm_riscv_aia_nr_hgei =3D 0; =20 --=20 2.43.0