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([58.84.60.222]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb56958c8sm62453205ad.13.2026.05.24.04.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 May 2026 04:18:33 -0700 (PDT) From: Udaya Kiran Challa To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, me@brighamcampbell.com, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Udaya Kiran Challa Subject: [PATCH v3] dt-bindings: clock: via,vt8500: Convert to DT Schema Date: Sun, 24 May 2026 16:47:57 +0530 Message-ID: <20260524111813.39810-1-challauday369@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the VIA/Wondermedia VT8500 and Wondermedia WM8xxx series SoCs clock controller binding from the legacy text format to DT schema. Signed-off-by: Udaya Kiran Challa --- Changelog: Changes since v2: - Drop redundant description for clocks - Disable reg property for device clocks - Fix schema hierarchy to match actual DTS structure Link to v2:https://lore.kernel.org/all/20260521170810.19702-1-challauday369= @gmail.com/ Changes since v1: - Add default value for divisor-mask - Add required properties compatible and model - Fix example node name - Update example size cells and reg value Link to v1:https://lore.kernel.org/all/20260520025131.17772-1-challauday369= @gmail.com/ --- .../bindings/clock/via,vt8500-clock.yaml | 179 ++++++++++++++++++ .../devicetree/bindings/clock/vt8500.txt | 74 -------- 2 files changed, 179 insertions(+), 74 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/via,vt8500-cloc= k.yaml delete mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt diff --git a/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml = b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml new file mode 100644 index 000000000000..035925969655 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml @@ -0,0 +1,179 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/via,vt8500-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500 Clock Controller + +maintainers: + - Michael Turquette + - Stephen Boyd + +description: + Clock controller bindings for VIA/Wondermedia VT8500 and Wondermedia WM8= xxx + series SoCs. + +properties: + clocks: + type: object + additionalProperties: true + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + required: + - "#address-cells" + - "#size-cells" + + patternProperties: + "^[a-z0-9]+(@[0-9a-f]+)?$": + type: object + + properties: + compatible: + enum: + - via,vt8500-pll-clock + - wm,wm8650-pll-clock + - wm,wm8750-pll-clock + - wm,wm8850-pll-clock + - via,vt8500-device-clock + + reg: + maxItems: 1 + description: + Offset of the PLL register within the PMC register space. + + clocks: + maxItems: 1 + + "#clock-cells": + const: 0 + + enable-reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Offset of the clock enable register within the PMC + register space. + + enable-bit: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 31 + description: + Bit index controlling clock enable. + + divisor-reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Offset of the clock divisor register within the PMC + register space. + + divisor-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x1f + description: + Bitmask describing the divisor field inside divisor-reg. + + required: + - compatible + - "#clock-cells" + + allOf: + - if: + properties: + compatible: + enum: + - via,vt8500-pll-clock + - wm,wm8650-pll-clock + - wm,wm8750-pll-clock + - wm,wm8850-pll-clock + then: + required: + - reg + - clocks + + - if: + properties: + compatible: + const: via,vt8500-device-clock + then: + properties: + reg: false + + required: + - clocks + + anyOf: + - required: + - enable-reg + - enable-bit + + - required: + - divisor-reg + + additionalProperties: false + +required: + - clocks + +additionalProperties: false + +examples: + - | + pmc@d8130000 { + compatible =3D "via,vt8500-pmc"; + reg =3D <0xd8130000 0x1000>; + + clocks { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ref24: clock-24000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + ref25: clock-25000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + plla: clock@200 { + compatible =3D "wm,wm8650-pll-clock"; + #clock-cells =3D <0>; + clocks =3D <&ref25>; + reg =3D <0x200>; + }; + + clkarm: arm { + compatible =3D "via,vt8500-device-clock"; + #clock-cells =3D <0>; + clocks =3D <&plla>; + divisor-reg =3D <0x300>; + }; + + clkuart0: uart0 { + compatible =3D "via,vt8500-device-clock"; + #clock-cells =3D <0>; + clocks =3D <&ref24>; + enable-reg =3D <0x250>; + enable-bit =3D <1>; + }; + + clksdhc: sdhc { + compatible =3D "via,vt8500-device-clock"; + #clock-cells =3D <0>; + clocks =3D <&plla>; + divisor-reg =3D <0x328>; + divisor-mask =3D <0x3f>; + enable-reg =3D <0x254>; + enable-bit =3D <18>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documenta= tion/devicetree/bindings/clock/vt8500.txt deleted file mode 100644 index 91d71cc0314a..000000000000 --- a/Documentation/devicetree/bindings/clock/vt8500.txt +++ /dev/null @@ -1,74 +0,0 @@ -Device Tree Clock bindings for arch-vt8500 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock - "wm,wm8650-pll-clock" - for a WM8650 PLL clock - "wm,wm8750-pll-clock" - for a WM8750 PLL clock - "wm,wm8850-pll-clock" - for a WM8850 PLL clock - "via,vt8500-device-clock" - for a VT/WM device clock - -Required properties for PLL clocks: -- reg : shall be the control register offset from PMC base for the pll clo= ck. -- clocks : shall be the input parent clock phandle for the clock. This sho= uld - be the reference clock. -- #clock-cells : from common clock binding; shall be set to 0. - -Required properties for device clocks: -- clocks : shall be the input parent clock phandle for the clock. This sho= uld - be a pll output. -- #clock-cells : from common clock binding; shall be set to 0. - - -Device Clocks - -Device clocks are required to have one or both of the following sets of -properties: - - -Gated device clocks: - -Required properties: -- enable-reg : shall be the register offset from PMC base for the enable - register. -- enable-bit : shall be the bit within enable-reg to enable/disable the cl= ock. - - -Divisor device clocks: - -Required property: -- divisor-reg : shall be the register offset from PMC base for the divisor - register. -Optional property: -- divisor-mask : shall be the mask for the divisor register. Defaults to 0= x1f - if not specified. - - -For example: - -ref25: ref25M { - #clock-cells =3D <0>; - compatible =3D "fixed-clock"; - clock-frequency =3D <25000000>; -}; - -plla: plla { - #clock-cells =3D <0>; - compatible =3D "wm,wm8650-pll-clock"; - clocks =3D <&ref25>; - reg =3D <0x200>; -}; - -sdhc: sdhc { - #clock-cells =3D <0>; - compatible =3D "via,vt8500-device-clock"; - clocks =3D <&pllb>; - divisor-reg =3D <0x328>; - divisor-mask =3D <0x3f>; - enable-reg =3D <0x254>; - enable-bit =3D <18>; -}; --=20 2.43.0