From nobody Sun May 24 18:44:12 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 867C63A8733 for ; Sun, 24 May 2026 16:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779640068; cv=none; b=UMQ5Sl66Nz4V7vGJHsi0K/tPTCcYXkTqMbOMbCwJIuUUIQUvuJcBdT2DYGLgtOQCYakQaJhfYGBVhdzj82BgjMKFk6xP0utWqJ4XmdRD54mRjiuSLtmrWSDE84DQ/2CbCXWpYRPx1SUS1JsgnycSMYRNxupztnhcSXkUCF2kIo0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779640068; c=relaxed/simple; bh=3XI839pwxOLRxjr8d7Rv3qpB1MWRN40cGsaWsPNwOV0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NITnh6s7BJxsukwz3kk58p74I/Uz+YXGGuRkpkEwKlrVRRWK6o3W18JmVFAtu38CTMvKi/jJhMIs+H3rtLJc4fQd6+LT7AuYxAF8HkAHf0JNGWHRgftIpWkD871rWMaOLd3/Uc9FFHZUf5zwmPoq1V3ZGMeH9O8u7dKg14+PqCk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=oesAuBRh; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="oesAuBRh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1779640063; bh=3XI839pwxOLRxjr8d7Rv3qpB1MWRN40cGsaWsPNwOV0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oesAuBRhT6O91wQCN1909BKv8YMxG/S/GIg6BmO0P9hhH96OJD0upGonxP0I5V20F 21JIiuqU5/1QOB6/5qQR3Yz/CA8napkQRkz6evHu7AMVSbSD93Z/4jM74goayNAFVz 5b/MVk1VsFSTenSNHtWYtmew/Hl2V/eZx1XdeE61db2sR8a6X6capn52Pq5O+rJ/Ow 9p6l2iHiBApDYJ0BGN580fl2Jqf51OugWc4KCrc8QgnA7ou2A5xqL1VjwMPZX5K18W 6G/8VuXxl4SmWDfOZXRcL5qrcUtRnvpDYdbNAOtGQwyEPq0y+zrvFPhx0qUazVCqvD NkVEfUI+yvLnw== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id DF54317E0977; Sun, 24 May 2026 18:27:42 +0200 (CEST) From: Cristian Ciocaltea Date: Sun, 24 May 2026 19:27:28 +0300 Subject: [PATCH 1/2] drm/rockchip: vop2: Rename CSC_BT2020 to CSC_BT2020L Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-vop2-bg-yuv-v1-1-dcb6a52923f5@collabora.com> References: <20260524-vop2-bg-yuv-v1-0-dcb6a52923f5@collabora.com> In-Reply-To: <20260524-vop2-bg-yuv-v1-0-dcb6a52923f5@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 Rename CSC_BT2020 to CSC_BT2020L for consistency with the other limited-range enum members (CSC_BT601L, CSC_BT709L) and to distinguish it from a potential future full-range BT.2020 variant. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index a160077a507f..64ac07cb1b0d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -658,7 +658,7 @@ static int vop2_convert_csc_mode(int csc_mode) case V4L2_COLORSPACE_JPEG: return CSC_BT601F; case V4L2_COLORSPACE_BT2020: - return CSC_BT2020; + return CSC_BT2020L; default: return CSC_BT709L; } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.h index 37722652844a..ffcb39c130aa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -373,7 +373,7 @@ enum vop_csc_format { CSC_BT601L, CSC_BT709L, CSC_BT601F, - CSC_BT2020, + CSC_BT2020L, }; =20 enum src_factor_mode { --=20 2.54.0 From nobody Sun May 24 18:44:12 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29AA93955C1 for ; Sun, 24 May 2026 16:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779640069; cv=none; b=JQ1dYw0Muy+BW9GKMSQmyAED31Yfb8V2P1gRhqH4RwfzWoGazs+V+n6pdiXmVyGcRjJJK9QHDCo/KWm4cxBROdoxFZBeuisNmYXB/TqgsYt3bhEYw3yV1c5Q9wpez09bktHCpp0iiGLhkHmnzPBtRMvqxV5mRUabXwIJOshI/qU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779640069; c=relaxed/simple; bh=vMUwbHaZbWb66jZ7iCMLMPvsaOQ2sMZq+JqO8SMiEww=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uGVLL3Wx+GGyAatTUYAqYNc6ff8aAvSAqZpAwRriuND2bL0Qu3VoQVp+KpB8xU/JHyYny3C3AtwxFDLaQ4UCdsSwC6/sQ8F9Sko7MxNyR/sXL9iYL+SDGmz3o4Zy6LeUVb3xnWV3SI8LCVzfmr2uB4HDMG0ofWMgBYO3UR4T4ng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Wt6Oovyh; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Wt6Oovyh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1779640063; bh=vMUwbHaZbWb66jZ7iCMLMPvsaOQ2sMZq+JqO8SMiEww=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Wt6OovyhHdAuiw09WvJxFvTmER1N/qZZr3Jxc+vd4z+yhxjuLcXSA4psnQdf2Z06j MH1DyvBUt8L95MDosMTsNnO8ga3cgpL5iq7spoDFgRJlP7CTIK8AcXAeYbTF4af2eZ D27ksPPwqPCOdqhffIgUU5rdU/HhJK9W2za1XLeYeuvquZj4M4AXQLGl/n8kdNXL7V D85NwWf5bm2ye2EIqxrdeum6pgxWkQe+Kb5wohrcj3jVfup7rp6/QxVdIi5bvA6kvS QIOCiFfHsBDnmGYo804Y3gRHaTImv8/4BmMbGm22Fcs1DBeYumPULVEhTF+1EP8o0e ffKpAqgXi8YJQ== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id AE3E717E0AE5; Sun, 24 May 2026 18:27:43 +0200 (CEST) From: Cristian Ciocaltea Date: Sun, 24 May 2026 19:27:29 +0300 Subject: [PATCH 2/2] drm/rockchip: vop2: Add YUV support to background color Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-vop2-bg-yuv-v1-2-dcb6a52923f5@collabora.com> References: <20260524-vop2-bg-yuv-v1-0-dcb6a52923f5@collabora.com> In-Reply-To: <20260524-vop2-bg-yuv-v1-0-dcb6a52923f5@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 The VOP2 background color must be programmed with 10-bit precision, using YUV format when the overlay operates in YUV mode, and RGB otherwise. Add the required RGB-to-YCbCr conversion logic, covering all color spaces supported by the display controller: BT601L, BT601F, BT709L and BT2020L. Since the color is currently programmed to hardware on every atomic commit, minimize the computation cost by splitting the work across the two paths: in atomic_enable(), perform the conversion unconditionally (the hardware state is unknown after power-on), while in atomic_flush(), perform it only when the DRM property has actually changed. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 152 +++++++++++++++++++++++= +--- 1 file changed, 137 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 64ac07cb1b0d..e3f7ed2ff285 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -644,6 +644,88 @@ static void vop2_setup_scale(struct vop2 *vop2, const = struct vop2_win *win, } } =20 +/* + * RGB-to-YCbCr conversion based on color_to_ycbcr() and rgb2ycbcr() from + * drivers/media/common/v4l2-tpg/v4l2-tpg-core.c. + * + * Limited-range Y offset & chroma midpoint are expressed in 16-bit space. + */ +#define RGB2YUV_LIMITED_Y_OFFSET (16 << 8) +#define RGB2YUV_CHROMA_OFFSET (128 << 8) +#define COEFF(v, r) ((s32)(0.5 + (v) * (r) * 256.0)) + +struct rgb2yuv_matrix { + s32 y_r, y_g, y_b; + s32 cb_r, cb_g, cb_b; + s32 cr_r, cr_g, cr_b; + s32 y_offset; +}; + +/* BT.601 Limited range */ +static const struct rgb2yuv_matrix rgb2yuv_bt601l =3D { + .y_r =3D COEFF(0.299, 219), .y_g =3D COEFF(0.587, 219), .y_b =3D C= OEFF(0.114, 219), + .cb_r =3D COEFF(-0.1687, 224), .cb_g =3D COEFF(-0.3313, 224), .cb_b =3D C= OEFF(0.5, 224), + .cr_r =3D COEFF(0.5, 224), .cr_g =3D COEFF(-0.4187, 224), .cr_b =3D C= OEFF(-0.0813, 224), + .y_offset =3D RGB2YUV_LIMITED_Y_OFFSET, +}; + +/* BT.601 Full range */ +static const struct rgb2yuv_matrix rgb2yuv_bt601f =3D { + .y_r =3D COEFF(0.299, 255), .y_g =3D COEFF(0.587, 255), .y_b =3D C= OEFF(0.114, 255), + .cb_r =3D COEFF(-0.1687, 255), .cb_g =3D COEFF(-0.3313, 255), .cb_b =3D C= OEFF(0.5, 255), + .cr_r =3D COEFF(0.5, 255), .cr_g =3D COEFF(-0.4187, 255), .cr_b =3D C= OEFF(-0.0813, 255), + .y_offset =3D 0, +}; + +/* BT.709 Limited range */ +static const struct rgb2yuv_matrix rgb2yuv_bt709l =3D { + .y_r =3D COEFF(0.2126, 219), .y_g =3D COEFF(0.7152, 219), .y_b =3D C= OEFF(0.0722, 219), + .cb_r =3D COEFF(-0.1146, 224), .cb_g =3D COEFF(-0.3854, 224), .cb_b =3D C= OEFF(0.5, 224), + .cr_r =3D COEFF(0.5, 224), .cr_g =3D COEFF(-0.4542, 224), .cr_b =3D C= OEFF(-0.0458, 224), + .y_offset =3D RGB2YUV_LIMITED_Y_OFFSET, +}; + +/* BT.2020 Limited range */ +static const struct rgb2yuv_matrix rgb2yuv_bt2020l =3D { + .y_r =3D COEFF(0.2627, 219), .y_g =3D COEFF(0.6780, 219), .y_b =3D C= OEFF(0.0593, 219), + .cb_r =3D COEFF(-0.1396, 224), .cb_g =3D COEFF(-0.3604, 224), .cb_b =3D C= OEFF(0.5, 224), + .cr_r =3D COEFF(0.5, 224), .cr_g =3D COEFF(-0.4598, 224), .cr_b =3D C= OEFF(-0.0402, 224), + .y_offset =3D RGB2YUV_LIMITED_Y_OFFSET, +}; + +static const struct rgb2yuv_matrix * +vop2_rgb2yuv_get_matrix(enum vop_csc_format csc) +{ + switch (csc) { + case CSC_BT601L: + return &rgb2yuv_bt601l; + case CSC_BT601F: + return &rgb2yuv_bt601f; + case CSC_BT2020L: + return &rgb2yuv_bt2020l; + case CSC_BT709L: + default: + return &rgb2yuv_bt709l; + } +} + +/* Convert an RGB (16bpc) to YUV444 (16bpc). */ +static void vop2_rgb16_to_yuv16(enum vop_csc_format csc, u16 r, u16 g, u16= b, + u16 *y, u16 *cb, u16 *cr) +{ + const struct rgb2yuv_matrix *m =3D vop2_rgb2yuv_get_matrix(csc); + s64 rs =3D r, gs =3D g, bs =3D b; + s64 ys, cbs, crs; + + ys =3D m->y_r * rs + m->y_g * gs + m->y_b * bs; + cbs =3D m->cb_r * rs + m->cb_g * gs + m->cb_b * bs; + crs =3D m->cr_r * rs + m->cr_g * gs + m->cr_b * bs; + + *y =3D (ys >> 16) + m->y_offset; + *cb =3D (cbs >> 16) + RGB2YUV_CHROMA_OFFSET; + *cr =3D (crs >> 16) + RGB2YUV_CHROMA_OFFSET; +} + static int vop2_convert_csc_mode(int csc_mode) { switch (csc_mode) { @@ -1554,12 +1636,58 @@ static void vop2_dither_setup(struct drm_crtc *crtc= , u32 *dsp_ctrl) DITHER_DOWN_ALLEGRO); } =20 -static void vop2_post_config(struct drm_crtc *crtc) +static void vop2_bgcolor_setup(struct drm_crtc *crtc, bool force, + struct drm_crtc_state *new_crtc_state, + struct drm_crtc_state *old_crtc_state) +{ + struct rockchip_crtc_state *new_vcstate =3D to_rockchip_crtc_state(new_cr= tc_state); + struct rockchip_crtc_state *old_vcstate =3D to_rockchip_crtc_state(old_cr= tc_state); + struct vop2_video_port *vp =3D to_vop2_video_port(crtc); + u64 bgcolor =3D new_crtc_state->background_color; + u16 y, cb, cr; + u32 val; + + if (!force && old_crtc_state->background_color =3D=3D bgcolor && + old_vcstate->color_space =3D=3D new_vcstate->color_space) + return; + + /* + * Background color is programmed with 10 bits of precision, using YUV + * format when operating in YUV overlay mode, and RGB otherwise. + */ + if (new_vcstate->yuv_overlay) { + vop2_rgb16_to_yuv16(new_vcstate->color_space, + DRM_ARGB64_GETR(bgcolor), + DRM_ARGB64_GETG(bgcolor), + DRM_ARGB64_GETB(bgcolor), + &y, &cb, &cr); + + val =3D FIELD_PREP(RK3568_VP_DSP_BG__DSP_BG_RED, cr >> 6); + FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_GREEN, &val, y >> 6); + FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_BLUE, &val, cb >> 6); + } else { + /* + * Since performance is more important than accuracy here, make + * use of the DRM_ARGB64_GET*_BPCS() helpers. + */ + val =3D FIELD_PREP(RK3568_VP_DSP_BG__DSP_BG_RED, + DRM_ARGB64_GETR_BPCS(bgcolor, 10)); + FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_GREEN, &val, + DRM_ARGB64_GETG_BPCS(bgcolor, 10)); + FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_BLUE, &val, + DRM_ARGB64_GETB_BPCS(bgcolor, 10)); + } + + vop2_vp_write(vp, RK3568_VP_DSP_BG, val); +} + +static void vop2_post_config(struct drm_crtc *crtc, bool force, + struct drm_crtc_state *new_crtc_state, + struct drm_crtc_state *old_crtc_state) { struct vop2_video_port *vp =3D to_vop2_video_port(crtc); struct vop2 *vop2 =3D vp->vop2; - struct drm_display_mode *mode =3D &crtc->state->adjusted_mode; - u64 bgcolor =3D crtc->state->background_color; + struct drm_display_mode *mode =3D &new_crtc_state->adjusted_mode; u16 vtotal =3D mode->crtc_vtotal; u16 hdisplay =3D mode->crtc_hdisplay; u16 hact_st =3D mode->crtc_htotal - mode->crtc_hsync_start; @@ -1605,15 +1733,7 @@ static void vop2_post_config(struct drm_crtc *crtc) vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); } =20 - /* - * Background color is programmed with 10 bits of precision. - * Since performance is more important than accuracy here, - * make use of the DRM_ARGB64_GET*_BPCS() helpers. - */ - val =3D FIELD_PREP(RK3568_VP_DSP_BG__DSP_BG_RED, DRM_ARGB64_GETR_BPCS(bgc= olor, 10)); - FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_GREEN, &val, DRM_ARGB64_GETG_BPCS(b= gcolor, 10)); - FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_BLUE, &val, DRM_ARGB64_GETB_BPCS(bg= color, 10)); - vop2_vp_write(vp, RK3568_VP_DSP_BG, val); + vop2_bgcolor_setup(crtc, force, new_crtc_state, old_crtc_state); } =20 static int us_to_vertical_line(struct drm_display_mode *mode, int us) @@ -1628,8 +1748,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, struct vop2 *vop2 =3D vp->vop2; const struct vop2_data *vop2_data =3D vop2->data; const struct vop2_video_port_data *vp_data =3D &vop2_data->vp[vp->id]; + struct drm_crtc_state *old_crtc_state =3D drm_atomic_get_old_crtc_state(s= tate, crtc); struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); - struct rockchip_crtc_state *vcstate =3D to_rockchip_crtc_state(crtc->stat= e); + struct rockchip_crtc_state *vcstate =3D to_rockchip_crtc_state(crtc_state= ); struct drm_display_mode *mode =3D &crtc->state->adjusted_mode; unsigned long clock =3D mode->crtc_clock * 1000; u16 hsync_len =3D mode->crtc_hsync_end - mode->crtc_hsync_start; @@ -1799,7 +1920,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, =20 clk_set_rate(vp->dclk, clock); =20 - vop2_post_config(crtc); + vop2_post_config(crtc, true, crtc_state, old_crtc_state); =20 vop2_cfg_done(vp); =20 @@ -1874,6 +1995,7 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *c= rtc, struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); + struct drm_crtc_state *old_crtc_state =3D drm_atomic_get_old_crtc_state(s= tate, crtc); struct vop2_video_port *vp =3D to_vop2_video_port(crtc); struct vop2 *vop2 =3D vp->vop2; =20 @@ -1881,7 +2003,7 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *c= rtc, if (!drm_atomic_crtc_needs_modeset(crtc_state) && crtc_state->color_mgmt_= changed) vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state); =20 - vop2_post_config(crtc); + vop2_post_config(crtc, false, crtc_state, old_crtc_state); =20 vop2_cfg_done(vp); =20 --=20 2.54.0