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Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- include/linux/mlx5/mlx5_ifc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 49f3ad4b1a7c548e57da0004a7a7c1e0e03f3534..f56de77cde3aa015c00d13e3240= 2e9ccb8ef9468 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1116,7 +1116,10 @@ struct mlx5_ifc_qos_cap_bits { u8 log_esw_max_sched_depth[0x4]; u8 reserved_at_10[0x10]; =20 - u8 reserved_at_20[0x9]; + u8 reserved_at_20[0x2]; + u8 packet_pacing_req_ud[0x1]; + u8 packet_pacing_req_uc[0x1]; + u8 reserved_at_24[0x5]; u8 esw_cross_esw_sched[0x1]; u8 reserved_at_2a[0x1]; u8 log_max_qos_nic_queue_group[0x5]; @@ -3707,7 +3710,8 @@ struct mlx5_ifc_qpc_bits { u8 cur_retry_count[0x3]; u8 reserved_at_39b[0x5]; =20 - u8 reserved_at_3a0[0x20]; + u8 reserved_at_3a0[0x10]; + u8 packet_pacing_rate_limit_index[0x10]; =20 u8 reserved_at_3c0[0x8]; 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Sun, 24 May 2026 08:38:41 -0700 From: Edward Srouji Date: Sun, 24 May 2026 18:38:03 +0300 Subject: [PATCH rdma-next 2/8] RDMA/mlx5: Refactor raw packet QP rate limit handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260524-packet-pacing-v1-2-3d79439f8d08@nvidia.com> References: <20260524-packet-pacing-v1-0-3d79439f8d08@nvidia.com> In-Reply-To: <20260524-packet-pacing-v1-0-3d79439f8d08@nvidia.com> To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , "Jason Gunthorpe" , Selvin Xavier , "Kalesh AP" , Abhijit Gangurde , Allen Hubbe CC: , , , Edward Srouji , "Maher Sanalla" , Michael Guralnik X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779637112; l=7364; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=aMdzEQA2h9Tbl/OwxGv4RhGEW1T9ZhYtVG93Cu5pOmQ=; b=E+V3FECwioAEmjTevNqO+RkWDNgD/qjzaZqAx0Fqy3vB5zCzyWvzTmARDQUkDbu1LrJkyyHkI FuCfoWePhWvAYMswl/xSG1ezVC6UjPNkXHBfwHQSpj11gbVmmlaXZzV X-Developer-Key: i=edwards@nvidia.com; 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Use qp_rl_commit() to commit changes to QP once FW call succeeds, and qp_rl_rollback() to rollback changes done to the FW rate limit table in the prepare stage, in case the modify operation fails. These helpers will be reused for extending rate limit support to additional QP types in the following patch. Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/qp.c | 168 ++++++++++++++++++++++++++----------= ---- 1 file changed, 110 insertions(+), 58 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/q= p.c index 6f88f9c52ad09860474824c88fdc73858045bbd0..fde319a021908317d96f3cdd212= ea5ebf691f13a 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -64,12 +64,19 @@ enum { MLX5_QP_RM_GO_BACK_N =3D 0x1, }; =20 +struct mlx5_rate_limit_ctx { + struct mlx5_rate_limit rl_old; + struct mlx5_rate_limit rl_desired; + u16 rl_desired_index; + bool rl_changed; +}; + struct mlx5_modify_raw_qp_param { u16 operation; =20 u32 set_mask; /* raw_qp_set_mask_map */ =20 - struct mlx5_rate_limit rl; + struct mlx5_rate_limit_ctx rl_ctx; =20 u8 rq_q_ctr_id; u32 port; @@ -3833,15 +3840,88 @@ static int modify_raw_packet_qp_rq( return err; } =20 +static int qp_rl_parse(struct mlx5_ib_dev *dev, + const struct ib_qp_attr *attr, + const struct mlx5_ib_modify_qp *ucmd, + struct mlx5_rate_limit *rl_desired) +{ + rl_desired->rate =3D attr->rate_limit; + + if (ucmd->burst_info.max_burst_sz) { + if (!attr->rate_limit || + !MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) + return -EINVAL; + rl_desired->max_burst_sz =3D ucmd->burst_info.max_burst_sz; + } + + if (ucmd->burst_info.typical_pkt_sz) { + if (!attr->rate_limit || + !MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) + return -EINVAL; + rl_desired->typical_pkt_sz =3D ucmd->burst_info.typical_pkt_sz; + } + + return 0; +} + +static int qp_rl_prepare(struct mlx5_ib_dev *dev, + struct mlx5_ib_qp *qp, u16 op, + struct mlx5_rate_limit_ctx *ctx) +{ + int err; + + ctx->rl_old =3D qp->rl; + + if (!qp->sq.wqe_cnt) + return 0; + + if (op !=3D MLX5_CMD_OP_RTR2RTS_QP && + op !=3D MLX5_CMD_OP_RTS2RTS_QP) + return 0; + + ctx->rl_changed =3D true; + + if (ctx->rl_desired.rate) { + err =3D mlx5_rl_add_rate(dev->mdev, &ctx->rl_desired_index, + &ctx->rl_desired); + if (err) { + pr_err("Failed configuring rate limit(err %d): rate %u, max_burst_sz %u= , typical_pkt_sz %u\n", + err, ctx->rl_desired.rate, + ctx->rl_desired.max_burst_sz, + ctx->rl_desired.typical_pkt_sz); + return err; + } + } + + return 0; +} + +static void qp_rl_rollback(struct mlx5_core_dev *dev, + struct mlx5_rate_limit_ctx *ctx) +{ + if (ctx->rl_desired_index) + mlx5_rl_remove_rate(dev, &ctx->rl_desired); +} + +static void qp_rl_commit(struct mlx5_core_dev *dev, + struct mlx5_ib_qp *qp, + struct mlx5_rate_limit_ctx *ctx) +{ + if (!ctx->rl_changed) + return; + + if (ctx->rl_old.rate) + mlx5_rl_remove_rate(dev, &ctx->rl_old); + + qp->rl =3D ctx->rl_desired; +} + static int modify_raw_packet_qp_sq( struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) { + const struct mlx5_rate_limit_ctx *rl_ctx =3D &raw_qp_param->rl_ctx; struct mlx5_ib_qp *ibqp =3D sq->base.container_mibqp; - struct mlx5_rate_limit old_rl =3D ibqp->rl; - struct mlx5_rate_limit new_rl =3D old_rl; - bool new_rate_added =3D false; - u16 rl_index =3D 0; void *in; void *sqc; int inlen; @@ -3859,49 +3939,26 @@ static int modify_raw_packet_qp_sq( MLX5_SET(sqc, sqc, state, new_state); =20 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { - if (new_state !=3D MLX5_SQC_STATE_RDY) + if (new_state !=3D MLX5_SQC_STATE_RDY) { pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", __func__); - else - new_rl =3D raw_qp_param->rl; - } - - if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { - if (new_rl.rate) { - err =3D mlx5_rl_add_rate(dev, &rl_index, &new_rl); - if (err) { - pr_err("Failed configuring rate limit(err %d): \ - rate %u, max_burst_sz %u, typical_pkt_sz %u\n", - err, new_rl.rate, new_rl.max_burst_sz, - new_rl.typical_pkt_sz); - - goto out; - } - new_rate_added =3D true; + } else if (rl_ctx->rl_changed) { + MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); + /* index 0 means no limit */ + MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, + rl_ctx->rl_desired_index); } - - MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); - /* index 0 means no limit */ - MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); } =20 err =3D mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); - if (err) { - /* Remove new rate from table if failed */ - if (new_rate_added) - mlx5_rl_remove_rate(dev, &new_rl); + if (err) goto out; - } =20 - /* Only remove the old rate after new rate was set */ - if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || - (new_state !=3D MLX5_SQC_STATE_RDY)) { - mlx5_rl_remove_rate(dev, &old_rl); - if (new_state !=3D MLX5_SQC_STATE_RDY) - memset(&new_rl, 0, sizeof(new_rl)); + if (new_state !=3D MLX5_SQC_STATE_RDY) { + mlx5_rl_remove_rate(dev, &ibqp->rl); + memset(&ibqp->rl, 0, sizeof(ibqp->rl)); } =20 - ibqp->rl =3D new_rl; sq->state =3D new_state; =20 out: @@ -4376,34 +4433,29 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, raw_qp_param.port =3D attr->port_num; =20 if (attr_mask & IB_QP_RATE_LIMIT) { - raw_qp_param.rl.rate =3D attr->rate_limit; - - if (ucmd->burst_info.max_burst_sz) { - if (attr->rate_limit && - MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { - raw_qp_param.rl.max_burst_sz =3D - ucmd->burst_info.max_burst_sz; - } else { - err =3D -EINVAL; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: m8+TNd3oCqYlcNDoYV7AQvkJ4Bu8uurhShok+YWLJkRTgQmFL4IL4ScLewww7qugHOZU7gWZbej5D8GNxhNHMWkX3IWiPlcghIDW8DTXLtfq5PzYG54WxV44UsYAwmrYKbtMhjXYEQHGR7mM/tU5aeFzCu7zthU4QKQeh76zijZehMarPqv8vZ23ozRuB4ooZT2NJnnN+9pyV5yXGdMYXM/PBeoOIni8Uyq2/T+gyibilRrXYSQnX+svcpSiWIJBuS82Jj2I+1VkCr9FprKr0h3urvZN5PlH9rv/CeJUKYCys4zXKqywNPDYZRdr41BN/J6G6INt2aSc+eF5RVcmr3FT2Bhve9MUlyQ1f7CMngUXfHQXn9KHCCy4l+018Y0vxQcl1IR9PbB6So5rM3AVDKcBj7lzgCv9xYs2nU2w65JK/1PnEqId4T3NXVEfwhFL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2026 15:38:57.4436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83be2a8d-c1d6-48c1-2226-08deb9aa91da X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9754 From: Maher Sanalla Rate limiting is currently supported only for raw packet QPs, where the packet pacing index is programmed into the SQC during SQ modify. Extend rate limit support to UD and UC QPs by setting the pacing index in the QPC during RTR2RTS and RTS2RTS transitions. Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/qp.c | 107 ++++++++++++++++++++++++++++--------= ---- include/linux/mlx5/qp.h | 1 + 2 files changed, 76 insertions(+), 32 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/q= p.c index fde319a021908317d96f3cdd212ea5ebf691f13a..e96d26253e3b1fabee23947b1a6= 1ab26e7c7067f 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -2725,6 +2725,10 @@ static void destroy_qp_common(struct mlx5_ib_dev *de= v, struct mlx5_ib_qp *qp, if (err) mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", base->mqp.qpn); + if (qp->rl.rate) { + mlx5_rl_remove_rate(dev->mdev, &qp->rl); + memset(&qp->rl, 0, sizeof(qp->rl)); + } } =20 destroy_qp(dev, qp, base, udata); @@ -3673,8 +3677,10 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STAT= E][MLX5_QP_NUM_STATE][MLX5_Q MLX5_QP_OPTPAR_RNR_TIMEOUT, [MLX5_QP_ST_UC] =3D MLX5_QP_OPTPAR_ALT_ADDR_PATH | MLX5_QP_OPTPAR_RWE | - MLX5_QP_OPTPAR_PM_STATE, - [MLX5_QP_ST_UD] =3D MLX5_QP_OPTPAR_Q_KEY, + MLX5_QP_OPTPAR_PM_STATE | + MLX5_QP_OPTPAR_PP_INDEX, + [MLX5_QP_ST_UD] =3D MLX5_QP_OPTPAR_Q_KEY | + MLX5_QP_OPTPAR_PP_INDEX, [MLX5_QP_ST_XRC] =3D MLX5_QP_OPTPAR_ALT_ADDR_PATH | MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE | @@ -3693,10 +3699,12 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STA= TE][MLX5_QP_NUM_STATE][MLX5_Q MLX5_QP_OPTPAR_ALT_ADDR_PATH, [MLX5_QP_ST_UC] =3D MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_PM_STATE | - MLX5_QP_OPTPAR_ALT_ADDR_PATH, + MLX5_QP_OPTPAR_ALT_ADDR_PATH | + MLX5_QP_OPTPAR_PP_INDEX, [MLX5_QP_ST_UD] =3D MLX5_QP_OPTPAR_Q_KEY | MLX5_QP_OPTPAR_SRQN | - MLX5_QP_OPTPAR_CQN_RCV, + MLX5_QP_OPTPAR_CQN_RCV | + MLX5_QP_OPTPAR_PP_INDEX, [MLX5_QP_ST_XRC] =3D MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE | MLX5_QP_OPTPAR_RWE | @@ -3840,11 +3848,31 @@ static int modify_raw_packet_qp_rq( return err; } =20 +static bool qp_rate_limit_supported(struct mlx5_ib_dev *dev, + struct mlx5_ib_qp *qp) +{ + if (qp->type =3D=3D IB_QPT_RAW_PACKET || + qp->flags & IB_QP_CREATE_SOURCE_QPN) + return true; + + if (qp->type =3D=3D IB_QPT_UD) + return MLX5_CAP_QOS(dev->mdev, packet_pacing_req_ud); + + if (qp->type =3D=3D IB_QPT_UC) + return MLX5_CAP_QOS(dev->mdev, packet_pacing_req_uc); + + return false; +} + static int qp_rl_parse(struct mlx5_ib_dev *dev, + struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, const struct mlx5_ib_modify_qp *ucmd, struct mlx5_rate_limit *rl_desired) { + if (!qp_rate_limit_supported(dev, qp)) + return -EOPNOTSUPP; + rl_desired->rate =3D attr->rate_limit; =20 if (ucmd->burst_info.max_burst_sz) { @@ -3905,15 +3933,20 @@ static void qp_rl_rollback(struct mlx5_core_dev *de= v, =20 static void qp_rl_commit(struct mlx5_core_dev *dev, struct mlx5_ib_qp *qp, - struct mlx5_rate_limit_ctx *ctx) + struct mlx5_rate_limit_ctx *ctx, + enum ib_qp_state new_state) { - if (!ctx->rl_changed) - return; - - if (ctx->rl_old.rate) - mlx5_rl_remove_rate(dev, &ctx->rl_old); + if (ctx->rl_changed) { + if (ctx->rl_old.rate) + mlx5_rl_remove_rate(dev, &ctx->rl_old); + qp->rl =3D ctx->rl_desired; + } =20 - qp->rl =3D ctx->rl_desired; + if (new_state =3D=3D IB_QPS_RESET || new_state =3D=3D IB_QPS_ERR) { + if (qp->rl.rate) + mlx5_rl_remove_rate(dev, &qp->rl); + memset(&qp->rl, 0, sizeof(qp->rl)); + } } =20 static int modify_raw_packet_qp_sq( @@ -4220,6 +4253,7 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, struct mlx5_ib_qp *qp =3D to_mqp(ibqp); struct mlx5_ib_qp_base *base =3D &qp->trans_qp.base; struct mlx5_ib_cq *send_cq, *recv_cq; + struct mlx5_rate_limit_ctx rl_ctx =3D {}; struct mlx5_ib_pd *pd; enum mlx5_qp_state mlx5_cur, mlx5_new; void *qpc, *pri_path, *alt_path; @@ -4410,20 +4444,31 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, goto out; } =20 + if (attr_mask & IB_QP_RATE_LIMIT) { + err =3D qp_rl_parse(dev, qp, attr, ucmd, &rl_ctx.rl_desired); + if (err) + goto out; + } else { + rl_ctx.rl_desired =3D qp->rl; + } + op =3D optab[mlx5_cur][mlx5_new]; + if (!mlx5_rl_are_equal(&rl_ctx.rl_desired, &qp->rl)) { + err =3D qp_rl_prepare(dev, qp, op, &rl_ctx); + if (err) + goto out; + } optpar |=3D ib_mask_to_mlx5_opt(attr_mask); + if (rl_ctx.rl_changed) + optpar |=3D MLX5_QP_OPTPAR_PP_INDEX; optpar &=3D opt_mask[mlx5_cur][mlx5_new][mlx5_st]; =20 - if (attr_mask & IB_QP_RATE_LIMIT && qp->type !=3D IB_QPT_RAW_PACKET) { - err =3D -EOPNOTSUPP; - goto out; - } - if (qp->type =3D=3D IB_QPT_RAW_PACKET || qp->flags & IB_QP_CREATE_SOURCE_QPN) { struct mlx5_modify_raw_qp_param raw_qp_param =3D {}; =20 raw_qp_param.operation =3D op; + raw_qp_param.rl_ctx =3D rl_ctx; if (cur_state =3D=3D IB_QPS_RESET && new_state =3D=3D IB_QPS_INIT) { raw_qp_param.rq_q_ctr_id =3D set_id; raw_qp_param.set_mask |=3D MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; @@ -4432,22 +4477,8 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, if (attr_mask & IB_QP_PORT) raw_qp_param.port =3D attr->port_num; =20 - if (attr_mask & IB_QP_RATE_LIMIT) { - err =3D qp_rl_parse(dev, qp, attr, ucmd, - &raw_qp_param.rl_ctx.rl_desired); - if (err) - goto out; - - if (!mlx5_rl_are_equal(&raw_qp_param.rl_ctx.rl_desired, - &qp->rl)) { - err =3D qp_rl_prepare(dev, qp, op, - &raw_qp_param.rl_ctx); - if (err) - goto out; - } - + if (rl_ctx.rl_changed) raw_qp_param.set_mask |=3D MLX5_RAW_QP_RATE_LIMIT; - } =20 err =3D modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); if (err) { @@ -4455,8 +4486,13 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, goto out; } =20 - qp_rl_commit(dev->mdev, qp, &raw_qp_param.rl_ctx); + qp_rl_commit(dev->mdev, qp, &raw_qp_param.rl_ctx, new_state); } else { + if (rl_ctx.rl_changed) { + MLX5_SET(qpc, qpc, packet_pacing_rate_limit_index, + rl_ctx.rl_desired_index); + } + if (udata) { /* For the kernel flows, the resp will stay zero */ resp->ece_options =3D @@ -4466,6 +4502,13 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, } err =3D mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, &resp->ece_options); + + if (err) { + qp_rl_rollback(dev->mdev, &rl_ctx); + goto out; + } + + qp_rl_commit(dev->mdev, qp, &rl_ctx, new_state); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0BBQzb7KFZEPdRoZMZiN7SbdbJuWIOkToRFjyPsvoLN2GixkpD1vcLRnDaKKQlx0jYOw+TzyP40D3fqJ6RAO6Pf1h1tq+iq3DNn38997Vc09atoICKxS29XaO/ZgZ462wdPjXgzk87B+eh/bAnpaO6GBCJVgxZuu8aohT9s4w9zKUolZb5mcUXPupRiyMqOdlVMDMhrcpHlLMuz8Npkz6ROMtwpPTSFf8LxWwYFsukNzUXPKgQhfs0RYRpxfe+DEfQuv6ibYEFa8wP8AgQArxLBaKeH3+TTci8whTIDQxehBjk0jMAegYHy7+qFJq8m9ip5/mmQmxlu2ds9huwer0PHNgOT/GcizOiHKrtocQxr6aq3g0wWAMb++rKVqvY+gx0x+6TzTQQU6FKKT5rKqNZmIA7B+1KjeGLpj6DgeJhvIdiFVnylm6gxaSgHbjBnq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2026 15:39:02.7417 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c89feacb-0104-43bf-244a-08deb9aa9502 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9278 From: Maher Sanalla Allow passing a rate limit attribute in modify QP flows even when the QP is in a state that does not support packet pacing programming in the lower layers. When the user sets a rate limit during a QP transition that is not to RTS, store the value in the mlx5 QP struct and program it to FW when the QP later transitions to RTS, which is the state that allows configuring the rate limit index in the QP context. Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/mlx5_ib.h | 1 + drivers/infiniband/hw/mlx5/qp.c | 14 +++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/m= lx5/mlx5_ib.h index e156dc4d752996cc4ae465bb567b0c1305d07fed..c74a53da99393cf4d4c0823cd12= f9eccaa28f212 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -536,6 +536,7 @@ struct mlx5_ib_qp { struct list_head cq_recv_list; struct list_head cq_send_list; struct mlx5_rate_limit rl; + struct mlx5_rate_limit rl_desired; u32 underlay_qpn; u32 flags_en; /* diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/q= p.c index e96d26253e3b1fabee23947b1a61ab26e7c7067f..66ab16b017c8311d44b521c023c= faf23ac42190a 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -3946,7 +3946,11 @@ static void qp_rl_commit(struct mlx5_core_dev *dev, if (qp->rl.rate) mlx5_rl_remove_rate(dev, &qp->rl); memset(&qp->rl, 0, sizeof(qp->rl)); + memset(&qp->rl_desired, 0, sizeof(qp->rl_desired)); + return; } + + qp->rl_desired =3D ctx->rl_desired; } =20 static int modify_raw_packet_qp_sq( @@ -3990,6 +3994,7 @@ static int modify_raw_packet_qp_sq( if (new_state !=3D MLX5_SQC_STATE_RDY) { mlx5_rl_remove_rate(dev, &ibqp->rl); memset(&ibqp->rl, 0, sizeof(ibqp->rl)); + memset(&ibqp->rl_desired, 0, sizeof(ibqp->rl_desired)); } =20 sq->state =3D new_state; @@ -4449,7 +4454,7 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, if (err) goto out; } else { - rl_ctx.rl_desired =3D qp->rl; + rl_ctx.rl_desired =3D qp->rl_desired; } =20 op =3D optab[mlx5_cur][mlx5_new]; @@ -4833,6 +4838,13 @@ int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_= qp_attr *attr, attr_mask); goto out; } + } else if (attr_mask =3D=3D IB_QP_RATE_LIMIT && cur_state !=3D IB_QPS_RTS= ) { + struct mlx5_rate_limit rl_desired =3D {}; + + err =3D qp_rl_parse(dev, qp, attr, &ucmd, &rl_desired); + if (!err) + qp->rl_desired =3D rl_desired; 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Sun, 24 May 2026 08:38:52 -0700 From: Edward Srouji Date: Sun, 24 May 2026 18:38:06 +0300 Subject: [PATCH rdma-next 5/8] RDMA/mlx5: Report packet pacing capabilities when querying device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260524-packet-pacing-v1-5-3d79439f8d08@nvidia.com> References: <20260524-packet-pacing-v1-0-3d79439f8d08@nvidia.com> In-Reply-To: <20260524-packet-pacing-v1-0-3d79439f8d08@nvidia.com> To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , "Jason Gunthorpe" , Selvin Xavier , "Kalesh AP" , Abhijit Gangurde , Allen Hubbe CC: , , , Edward Srouji , "Maher Sanalla" , Michael Guralnik X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779637112; l=2431; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=aHKU0s9Lx5P7SBAnRFR+71tuNIyqpm30Z5dgLTlRjHE=; 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Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/main.c | 37 +++++++++++++++++++++++------------= -- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5= /main.c index 428811fa805b68bf6a011685e027b8407a3e1719..fee5329cf398092c5096ca67aa2= 3880b6e829177 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -1214,20 +1214,29 @@ static int mlx5_ib_query_device(struct ib_device *i= bdev, } } =20 - if (offsetofend(typeof(resp), packet_pacing_caps) <=3D uhw_outlen && - raw_support) { - if (MLX5_CAP_QOS(mdev, packet_pacing) && - MLX5_CAP_GEN(mdev, qos)) { - resp.packet_pacing_caps.qp_rate_limit_max =3D - MLX5_CAP_QOS(mdev, packet_pacing_max_rate); - resp.packet_pacing_caps.qp_rate_limit_min =3D - MLX5_CAP_QOS(mdev, packet_pacing_min_rate); - resp.packet_pacing_caps.supported_qpts |=3D - 1 << IB_QPT_RAW_PACKET; - if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && - MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) - resp.packet_pacing_caps.cap_flags |=3D - MLX5_IB_PP_SUPPORT_BURST; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: knYRznc4CPaxhDMkc3v1Y12eif1TbKE2UPkxYMqIP61xlrggAcU6JvZ5wdLJmAENVaaSsbrk5Or6tuZw3eeM58jwR+sjnS8Bbf+a6P6Pyvo6HYEbVHrhsOQ6xK91vCZScAyYLDSNhYwR6JI10BaG+UEBWPZCqB9jhYohG8UiojxclXCAA01RuqBXapvf2+uL+LgqyJSmX9ZLRCrRNES+TwerApXKXnpwu4eNYloP4z7NmVsVszUq+PKDI3K8IEWdca7n4SETpjj8UY70KAs0jss2TZrlH5p8ZyJMZF8Aq447Fb1AKX6UOef441T15nYPWDwrZkfWz2vH9IJ/e0rW5Mh+1WONucjh4eHyoG7xBHftex/cmwnRNvAwucc20VmArPb4QgOCAFJ6WqdeFlGzJvEWMpcYSQ4SqpnBElOqw0iTjOlBcANccIh+M8BbF/3w X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2026 15:39:09.4883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db50caa8-47af-486f-ccf2-08deb9aa9904 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6927 From: Maher Sanalla Rate limit transition validation for RC QPs currently relies on the IB core qp_state_table. Add a driver-level helper to validate the rate limit attribute directly during QP modify, ensuring it is only accepted for RC QPs in INIT->RTR, RTR->RTS and RTS->RTS transitions. This makes the driver responsible for rate limit validation and prepares for a follow-up IB core change that delegates IB_QP_RATE_LIMIT and all future non-standard modify attributes handling to individual vendor drivers. Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- drivers/infiniband/hw/bnxt_re/ib_verbs.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/= hw/bnxt_re/ib_verbs.c index ccb362d6d2e669160174cc562d4e3d8d22b110db..14d2533d7439f2c160ceeea3d0c= 1e2fe9abcd9f5 100644 --- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c +++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c @@ -2286,6 +2286,23 @@ static int bnxt_re_modify_shadow_qp(struct bnxt_re_d= ev *rdev, return rc; } =20 +static bool bnxt_re_is_modify_ok(enum ib_qp_attr_mask ext_mask, + enum ib_qp_type type, enum ib_qp_state cur, + enum ib_qp_state next) +{ + if (!ext_mask) + return true; + + if (ext_mask & ~IB_QP_RATE_LIMIT) + return false; + + /* Rate limit is only supported for RC QPs during specific transitions */ + return type =3D=3D IB_QPT_RC && + ((cur =3D=3D IB_QPS_INIT && next =3D=3D IB_QPS_RTR) || + (cur =3D=3D IB_QPS_RTR && next =3D=3D IB_QPS_RTS) || + (cur =3D=3D IB_QPS_RTS && next =3D=3D IB_QPS_RTS)); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: iezn/YCZ2peFE3KKih9yzJWqg/CJSi2LvYyfAUm5MUkC1LsoC1pu/62iccNF38kl6Vu+GCjAV2zIdvUrk2N3A+St9CIVnHD5cMqEvB0IO70IFjq5L9Quw/80gV4WFkWZz44cd6KKuQQDWu0mEhZ43B7DhbQxXrQKvF88CFvJBV/3PtN8GBIBGuRNfmNUOUTcbZkicPAoy27uyg1/qWTgHeOjVawogdz9zNivVvACL71ujARYaHI94YmAemCwz1nOT8tGpx4DNtRPNju0WP1o6Sa6F3NT541NuvV5+uiHqAN1IE7m+Wl87eJAHSsuvHzj+60+3rDa4UumK7qmNmzH6j35op+qBdv9u27i55Fifm5t+2Hc89yVsAfAz7zcW19Xt20wEtAJk5MOfACBb7b5vrXT16Eae/VPkI90V7u4KrPLNY0vP73l71qlpfxapj/k X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2026 15:39:17.3062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f0cb663-1576-430d-4503-08deb9aa9db2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000099.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9143 From: Maher Sanalla Rate limit transition validation for RC QPs currently relies on the IB core qp_state_table. Add a driver-level helper to validate the rate limit attribute directly during QP modify, ensuring it is only accepted for RC QPs in INIT->RTR, RTR->RTS and RTS->RTS transitions. This makes the driver responsible for rate limit validation and prepares for a follow-up IB core change that delegates IB_QP_RATE_LIMIT and all future non-standard modify attributes handling to individual vendor drivers. Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- drivers/infiniband/hw/ionic/ionic_controlpath.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/ionic/ionic_controlpath.c b/drivers/infi= niband/hw/ionic/ionic_controlpath.c index 2b01345848ddb7ee9b34e5c9bb074912734536e1..72e111027f1f5fede5aa21f0265= 219392f29a3ee 100644 --- a/drivers/infiniband/hw/ionic/ionic_controlpath.c +++ b/drivers/infiniband/hw/ionic/ionic_controlpath.c @@ -2535,6 +2535,23 @@ static bool ionic_qp_cur_state_is_ok(enum ib_qp_stat= e q_state, return false; } =20 +static bool ionic_is_modify_ok(enum ib_qp_attr_mask ext_mask, + enum ib_qp_type type, enum ib_qp_state cur, + enum ib_qp_state next) +{ + if (!ext_mask) + return true; + + if (ext_mask & ~IB_QP_RATE_LIMIT) + return false; + + /* Rate limit is only supported for RC QPs during specific transitions */ + return type =3D=3D IB_QPT_RC && + ((cur =3D=3D IB_QPS_INIT && next =3D=3D IB_QPS_RTR) || + (cur =3D=3D IB_QPS_RTR && next =3D=3D IB_QPS_RTS) || + (cur =3D=3D IB_QPS_RTS && next =3D=3D IB_QPS_RTS)); +} + static int ionic_check_modify_qp(struct ionic_qp *qp, struct ib_qp_attr *a= ttr, int mask) { @@ -2547,7 +2564,9 @@ static int ionic_check_modify_qp(struct ionic_qp *qp,= struct ib_qp_attr *attr, !ionic_qp_cur_state_is_ok(qp->state, attr->cur_qp_state)) return -EINVAL; =20 - if (!ib_modify_qp_is_ok(cur_state, next_state, qp->ibqp.qp_type, mask)) + if (!ib_modify_qp_is_ok(cur_state, next_state, qp->ibqp.qp_type, mask) || + !ionic_is_modify_ok(mask & ~IB_QP_ATTR_STANDARD_BITS, + qp->ibqp.qp_type, cur_state, next_state)) return -EINVAL; =20 /* unprivileged qp not allowed privileged qkey */ --=20 2.49.0 From nobody Sun May 24 17:49:07 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010053.outbound.protection.outlook.com [52.101.46.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C4E2399019; Sun, 24 May 2026 15:39:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 24 May 2026 08:39:08 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 24 May 2026 08:39:08 -0700 Received: from [10.135.59.1] (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sun, 24 May 2026 08:39:04 -0700 From: Edward Srouji Date: Sun, 24 May 2026 18:38:09 +0300 Subject: [PATCH rdma-next 8/8] IB/core: Delegate IB_QP_RATE_LIMIT validation to drivers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260524-packet-pacing-v1-8-3d79439f8d08@nvidia.com> References: <20260524-packet-pacing-v1-0-3d79439f8d08@nvidia.com> In-Reply-To: <20260524-packet-pacing-v1-0-3d79439f8d08@nvidia.com> To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , "Jason Gunthorpe" , Selvin Xavier , "Kalesh AP" , Abhijit Gangurde , Allen Hubbe CC: , , , Edward Srouji , "Maher Sanalla" , Michael Guralnik X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qfWXnP4jQHVsxmgtI4l3BWLS2sLv4tx5uk+rng3yfkG5b7eiy6oIM8vXglMWfTCin2F5jtlwAXNAgr1o4GtdHz37683gfYHPQmKbm4MkxfqnP/IdatDwVasK+CH2qv1oG1HHiL9OSjvfj2C2UIvTZnVre/ZuiSGcvwYQVw8FVeYd5K4RSDjfWJW09AgXGX+uslWG9IhrvfnWfpLOqHX1S/3Q5aTna7AaqXpPaYnX9bV/HmaAhXFhXj8ALUDTV85uZO56uc5OF1PkebSEE3JUmC+NcCEBuWvs5NkfepDJbmVTtqZR425akcKjjevSao8tn0ErNz2KG+srnkWIS6gO0BETgD/xAmWg1cgcXt+M+s3v8AKM4zP+dwVBtulbqeW6tHVu4G5yi22KcZes8nSz6E/1QBe7eniZtYsWAyp45IwGUAPs4D4VcwADcvQHGGip X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2026 15:39:21.0123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75cfd5ba-e9f9-422d-84ee-08deb9aa9fe9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000099.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8017 From: Maher Sanalla Remove IB_QP_RATE_LIMIT from the qp_state_table and instead pass it through ib_modify_qp_is_ok() unconditionally. This delegates rate limit attribute validation to the individual drivers that support it. As rate limit support expands to additional QP types and transitions across different vendors, centralizing this policy in the core becomes impractical. Each driver is better positioned to enforce its own supported QP types and transitions over non-standard attributes. Future support for non-standard attributes will be handled per vendor driver instead of in generic IB core qp_state_table. Signed-off-by: Maher Sanalla Reviewed-by: Michael Guralnik Signed-off-by: Edward Srouji --- drivers/infiniband/core/verbs.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verb= s.c index bac87de9cc6735c5d25420a7fac8facdd77d5f09..d105106fe9dc2a86001f771c0b7= ab887e576642d 100644 --- a/drivers/infiniband/core/verbs.c +++ b/drivers/infiniband/core/verbs.c @@ -1538,8 +1538,7 @@ static const struct { IB_QP_PKEY_INDEX), [IB_QPT_RC] =3D (IB_QP_ALT_PATH | IB_QP_ACCESS_FLAGS | - IB_QP_PKEY_INDEX | - IB_QP_RATE_LIMIT), + IB_QP_PKEY_INDEX), [IB_QPT_XRC_INI] =3D (IB_QP_ALT_PATH | IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX), @@ -1587,8 +1586,7 @@ static const struct { IB_QP_ALT_PATH | IB_QP_ACCESS_FLAGS | IB_QP_MIN_RNR_TIMER | - IB_QP_PATH_MIG_STATE | - IB_QP_RATE_LIMIT), + IB_QP_PATH_MIG_STATE), [IB_QPT_XRC_INI] =3D (IB_QP_CUR_STATE | IB_QP_ALT_PATH | IB_QP_ACCESS_FLAGS | @@ -1602,7 +1600,6 @@ static const struct { IB_QP_QKEY), [IB_QPT_GSI] =3D (IB_QP_CUR_STATE | IB_QP_QKEY), - [IB_QPT_RAW_PACKET] =3D IB_QP_RATE_LIMIT, } } }, @@ -1622,8 +1619,7 @@ static const struct { IB_QP_ACCESS_FLAGS | IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE | - IB_QP_MIN_RNR_TIMER | - IB_QP_RATE_LIMIT), + IB_QP_MIN_RNR_TIMER), [IB_QPT_XRC_INI] =3D (IB_QP_CUR_STATE | IB_QP_ACCESS_FLAGS | IB_QP_ALT_PATH | @@ -1637,7 +1633,6 @@ static const struct { IB_QP_QKEY), [IB_QPT_GSI] =3D (IB_QP_CUR_STATE | IB_QP_QKEY), - [IB_QPT_RAW_PACKET] =3D IB_QP_RATE_LIMIT, } }, [IB_QPS_SQD] =3D { @@ -1775,7 +1770,7 @@ bool ib_modify_qp_is_ok(enum ib_qp_state cur_state, e= num ib_qp_state next_state, if ((mask & req_param) !=3D req_param) return false; =20 - if (mask & ~(req_param | opt_param | IB_QP_STATE)) + if (mask & ~(req_param | opt_param | IB_QP_STATE | IB_QP_RATE_LIMIT)) return false; =20 return true; --=20 2.49.0