From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC86C38F646; Sun, 24 May 2026 10:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618939; cv=none; b=V22IIZAmV0FnOQu04nXF3Dh3FxVwbvf+dTgBkZhyUbw0/B0wMQa9o9Sm5VEJ+JtiH6mrsSNGPOOD9bwpfiPVz7oVFbzA+akIwxm1ESBM/hoqbMa36uZM3nUD7EBejJRpP3Q/njo0T5qEb3yxjDxJCjbI89UsohjaXJ9wWtn5pLQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618939; c=relaxed/simple; bh=DwcVGf55Ebihg1MbnvXiFFLAExefrkwKIieqBYgf39Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BProyQUM5bi23/lVCuo7PtglIxxyO3wR1BaQjVlymCKzk8Te3vewUXrRgO5Ps0Pfe7MO9hEZ3EdBUouHIpRInjqO3hD6t73spsCc5pSWvILA2HlYubKNVqzmvb0CZ5tNqgFR/iEnmKoT/JO+iH+l0tg6CxCDgZ3hMMyjz6+Mirw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MaxiRtlf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MaxiRtlf" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7CF0FC2BCB8; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618939; bh=DwcVGf55Ebihg1MbnvXiFFLAExefrkwKIieqBYgf39Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MaxiRtlftacvo28wrzE8pitzym30fXhe00/GQ2wmx9/INQfGdFixawRxFvcopX9/d w9RpcfoaMzDka0a3WmiOg0s/8ftqXr4PgxdieCu/VCcPuQgyii6jKBNERno/pdNT9I dA2gOVxAjt+6kK7wpPfYNR3+mpxuJdHO3yDuXHmwqd324/j8xYIlryTRCPhCiXkoOb HiWTKc+tWbmVNYGb7R5pr+0IoacYkpiI1Xm5LxYGCvgXpBmnkZgXv96RJtjay4Wpd/ yAzHbmBSXTlIxiuQI8Hg/3zQ5xEeOHsvKNO7ldwOtALjhFWpXQEn3NLWgxWXIF6fFM spF6ygzPrc3Ew== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 684DBCD5BAB; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:18 +0100 Subject: [PATCH v14 01/12] dt-bindings: iio: frequency: add adf41513 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-1-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=9537; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=/EYODO6CXKC1vAUrEhocUM0AElaF6JP80c4HuEwBXMk=; b=+Q31eJf4nvXzVJJCCQFiCeo+fV1hvKLMx1HSyXiVSxf9DVoMEzvdtNQ7gucyoUtFlDAhpQSdv yKvdYnN0fW0DUDhc4Gr4ZGWQJdkNWttfhteVpZ71UqYuAcCoXxzTYOO X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar DT-bindings for ADF41513, an ultralow noise PLL frequency synthesizer that can be used to implement local oscillators (LOs) as high as 26.5 GHz. Some properties are based upon an existing PLL device properties (e.g. ADF4350). Reviewed-by: Krzysztof Kozlowski Signed-off-by: Rodrigo Alencar --- .../bindings/iio/frequency/adi,adf41513.yaml | 227 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 234 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.y= aml b/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml new file mode 100644 index 000000000000..f4fae9210382 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,adf41513.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADF41513 PLL Frequency Synthesizer + +maintainers: + - Rodrigo Alencar + +description: + The ADF41513 is an ultralow noise frequency synthesizer that can be used= to + implement local oscillators (LOs) as high as 26.5 GHz in the upconversio= n and + downconversion sections of wireless receivers and transmitters. The ADF4= 1510 + supports frequencies up to 10 GHz. + + https://www.analog.com/en/products/adf41510.html + https://www.analog.com/en/products/adf41513.html + +properties: + compatible: + enum: + - adi,adf41510 + - adi,adf41513 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + clocks: + maxItems: 1 + description: Clock that provides the reference input frequency. + + avdd1-supply: + description: PFD and Up and Down Digital Driver Power Supply (3.3 V) + + avdd2-supply: + description: RF Buffer and Prescaler Power Supply (3.3 V) + + avdd3-supply: + description: N Divider Power Supply (3.3 V) + + avdd4-supply: + description: R Divider and Lock Detector Power Supply (3.3 V) + + avdd5-supply: + description: Sigma-Delta Modulator and SPI Power Supply (3.3 V) + + vp-supply: + description: Charge Pump Power Supply (3.3 V) + + enable-gpios: + description: + GPIO that controls the chip enable pin. A logic low on this pin + powers down the device and puts the charge pump output into + three-state mode. + maxItems: 1 + + lock-detect-gpios: + description: + GPIO for lock detect functionality. When configured for digital lock + detect, this pin will output a logic high when the PLL is locked. + maxItems: 1 + + adi,power-up-frequency-mhz: + minimum: 1000 + maximum: 26500 + default: 10000 + description: + The PLL tunes to this frequency during the initialization sequence. + This property should be set to a frequency supported by the loop fil= ter + and VCO used in the design. Range is 1 GHz to 26.5 GHz for ADF41513, + and 1 GHz to 10 GHz for ADF41510. + + adi,reference-div-factor: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 1 + description: + Value for the reference division factor (R Counter). The driver will + increment R Counter as needed to achieve a PFD frequency within the + allowed range. High R counter values will reduce the PFD frequency, = which + lowers the frequency resolution, and affects phase noise performance. + As it affects the PFD frequency, this value depends on the loop filt= er + design. + + adi,reference-doubler-enable: + description: + Enables the reference doubler when deriving the PFD frequency. + The maximum reference frequency when the doubler is enabled is 225 M= Hz. + As it affects the PFD frequency, this value depends on the loop filt= er + design. + type: boolean + + adi,reference-div2-enable: + description: + Enables the reference divide-by-2 function when deriving the PFD + frequency. As it affects the PFD frequency, this value depends on the + loop filter design. + type: boolean + + adi,charge-pump-resistor-ohms: + minimum: 1800 + maximum: 10000 + default: 2700 + description: + External charge pump resistor (R_SET) value in ohms. This sets the m= aximum + charge pump current along with the charge pump current setting. + + adi,charge-pump-current-microamp: + minimum: 81 + maximum: 7200 + description: + Charge pump current (I_CP) in microamps. The value will be rounded t= o the + nearest supported value. Range of acceptable values depends on the + charge pump resistor value, such that 810 mV <=3D I_CP * R_SET <=3D = 12960 mV. + This value depends on the loop filter and the VCO design. + + adi,logic-level-1v8-enable: + description: + Set MUXOUT and DLD logic levels to 1.8V. Default is 3.3V. + type: boolean + + adi,phase-detector-polarity-positive-enable: + description: + Set phase detector polarity to positive. Default is negative. + Use positive polarity with non-inverting loop filter and VCO with + positive tuning slope, or with inverting loop filter and VCO with + negative tuning slope. + type: boolean + + adi,lock-detector-count: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 64 + description: + Sets the value for Lock Detector count of the PLL, which determines = the + number of consecutive phase detector cycles that must be within the = lock + detector window before lock is declared. Lower values increase the l= ock + detection sensitivity, while higher values provides a more stable lo= ck + detection. Applications that consume the lock detect signal may requ= ire + different settings based on system requirements. + enum: [2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192] + + adi,phase-resync-period-ns: + default: 0 + description: + When this value is non-zero, enable phase resync functionality, which + produces a consistent output phase offset with respect to the input + reference. The value specifies the resync period in nanoseconds, used + to configure clock dividers with respect to the PFD frequency. This = value + should be set to a value that is at least as long as the worst case = lock + time, i.e., it depends mostly on the loop filter design. + + adi,le-sync-enable: + description: + Synchronizes Load Enable (LE) transitions with the reference signal = to + avoid asynchronous glitches in the output. This is recommended when = using + the PLL as a frequency synthesizer, where the reference signal will = always + be present while the device is being configured. When using the PLL = as a + frequency tracker, where the reference signal may be absent, LE sync + should be left disabled. + type: boolean + +dependencies: + adi,charge-pump-resistor-ohms: [ 'adi,charge-pump-current-microamp' ] + +required: + - compatible + - reg + - clocks + - avdd1-supply + - avdd2-supply + - avdd3-supply + - avdd4-supply + - avdd5-supply + - vp-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + const: adi,adf41510 + then: + properties: + adi,power-up-frequency-mhz: + maximum: 10000 + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pll@0 { + compatible =3D "adi,adf41513"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + clocks =3D <&ref_clk>; + avdd1-supply =3D <&avdd1_3v3>; + avdd2-supply =3D <&avdd2_3v3>; + avdd3-supply =3D <&avdd3_3v3>; + avdd4-supply =3D <&avdd4_3v3>; + avdd5-supply =3D <&avdd5_3v3>; + vp-supply =3D <&vp_3v3>; + enable-gpios =3D <&gpio0 10 GPIO_ACTIVE_HIGH>; + lock-detect-gpios =3D <&gpio0 11 GPIO_ACTIVE_HIGH>; + + adi,power-up-frequency-mhz =3D <15500>; + adi,charge-pump-current-microamp =3D <3600>; + adi,charge-pump-resistor-ohms =3D <2700>; + adi,reference-doubler-enable; + adi,lock-detector-count =3D <64>; + adi,phase-resync-period-ns =3D <0>; + adi,phase-detector-polarity-positive-enable; + adi,le-sync-enable; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 3115538ce829..e1c3a26a6e2f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1662,6 +1662,13 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ade9000.yaml F: drivers/iio/adc/ade9000.c =20 +ANALOG DEVICES INC ADF41513 DRIVER +M: Rodrigo Alencar +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml + ANALOG DEVICES INC ADF4377 DRIVER M: Antoniu Miclaus L: linux-iio@vger.kernel.org --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC8FA38F658; Sun, 24 May 2026 10:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618939; cv=none; b=F4haujFaVjG/vCTbKjbWaqKPNo6SLWYxaCxgIzJXUboRSSyF7NBPvLTBpmnPGDb71LciaMOr7e24pRlG7bqiX1pZyN6U8uFyhG/yjmox1n5CAUaE1o7a2ZBrVrjrU4Lc6zN7REteqNjWLUq9UrXDQ12+VRISEBl17edzQ87Ko4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618939; c=relaxed/simple; bh=fEpQ52qwEX2E5hNxyn7ssHZ/AkOROrSM19L+xOMsKpE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tGzHmY4nvDXXuxSQMHf7yVfeOCJnXaMVGeVKhExEUeyKwq1j3eEpzIcj0Q2CiQX7+LLPAr4dHIreaPMDnDvUHmZe/bQMXECBuc+NM9vFGsB8u6PfZgy+OqxfVF6m4qPRJqTTZ3MVLCe1cmHUq/2aLfLqX4mJ1wj0ldEMJrrBre4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZQepbM3O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZQepbM3O" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8A8CBC2BCC7; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618939; bh=fEpQ52qwEX2E5hNxyn7ssHZ/AkOROrSM19L+xOMsKpE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZQepbM3O0ZgBRhWr6X/n0TfT9/1QcA2vDVhAQLpxFlGhA7w/ffTXBNiR5O3pe+GeI cyZ4L9JlPakyXEDrY+mKG4rVHFUhIoWOBRDRRIgS36rO/Z1HxojwpzPN8m9I62jBxZ 3eGgRtbxW1MQ2xs11ZOVTFEQsHZpWcijR8XI3G6t/BsJeH8c2ryBFcshvUAw0FbD/N ZEbjBcZh3ve3J5j3rH1s4v/RHpGOB9yWU8k4MPWM5oDJDUFiUa3Dd1tXK3M/jdiORQ F3jeNQu6uNSHXH+E2p1hzgj8uJVISk79WDyfAasvbrZaTRN0AY8p+5GzpfYfe4HsaC VeSudqOKzdO4A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 758F4CD5BB1; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:19 +0100 Subject: [PATCH v14 02/12] lib: kstrtox: add local _parse_integer_limit_init() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-2-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=2791; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=UxUL9EGcYZLlZrE68BZiyyEJoU0744KsS7KUqiWM08U=; b=XEe/ZsJtxx7p3Xh8mIq6R0eAnYwC+N5/ll9mzNpjifP1PQhy+bPzRMs61Dtkk+7biiIUSP0x0 KgtKG9yxHeNCh+zB2XJF+7knAW1xDp3jrzXBWoEh8DoCuEAr62+cgCx X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add parsing helper that accepts an initial value for the accumulated result when parsing an 64-bit integer. It reuses current implementation for _parse_integer_limit(), which now consumes the new function with init =3D 0. The diff algorithm would have the documentation header and prototype of _parse_integer_limit() moved around so it is adjusted according to guidelines. Signed-off-by: Rodrigo Alencar --- lib/kstrtox.c | 41 ++++++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/lib/kstrtox.c b/lib/kstrtox.c index 97be2a39f537..bd63c55b8490 100644 --- a/lib/kstrtox.c +++ b/lib/kstrtox.c @@ -39,23 +39,15 @@ const char *_parse_integer_fixup_radix(const char *s, u= nsigned int *base) return s; } =20 -/* - * Convert non-negative integer string representation in explicitly given = radix - * to an integer. A maximum of max_chars characters will be converted. - * - * Return number of characters consumed maybe or-ed with overflow bit. - * If overflow occurs, result integer (incorrect) is still returned. - * - * Don't you dare use this function. - */ -noinline -unsigned int _parse_integer_limit(const char *s, unsigned int base, unsign= ed long long *p, - size_t max_chars) +static unsigned int _parse_integer_limit_init(const char *s, unsigned int = base, + unsigned long long init, + unsigned long long *p, + size_t max_chars) { unsigned long long res; unsigned int rv; =20 - res =3D 0; + res =3D init; rv =3D 0; while (max_chars--) { unsigned int c =3D *s; @@ -87,6 +79,29 @@ unsigned int _parse_integer_limit(const char *s, unsigne= d int base, unsigned lon return rv; } =20 +/** + * _parse_integer_limit() - Convert integer string representation to an in= teger + * limiting the number of characters parsed. + * @s: The start of the string. + * @base: The number base to use. + * @p: Where to write the result of the conversion. + * @max_chars: Maximum amount of characters to consume. + * + * Convert non-negative integer string representation in explicitly given = radix + * to an integer. A maximum of max_chars characters will be converted. + * + * Avoid using this function directly, consider kstrto*() functions instea= d. + * + * Return: Number of characters consumed maybe or-ed with overflow bit. + * If overflow occurs, result integer (incorrect) is still returned. + */ +noinline +unsigned int _parse_integer_limit(const char *s, unsigned int base, + unsigned long long *p, size_t max_chars) +{ + return _parse_integer_limit_init(s, base, 0, p, max_chars); +} + noinline unsigned int _parse_integer(const char *s, unsigned int base, unsigned lon= g long *p) { --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEE253911B8; Sun, 24 May 2026 10:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618939; cv=none; b=qB2Srk6gwTm9W2GfHthIMmziSq271RIbrRX9c8WC9dfcJNhGE5hsOt/n/6WHW0V+wAMHK5QRPRNY78f2mInBsUZQa3QCJIYRYBkYwheNt5obhSolWI9ETutlwqLaVnma09sT964V2mqhM4PKKRzlhJZI40alu4cT5Z6fOXhCnXA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618939; c=relaxed/simple; bh=CORvr0UdfFniwScEKu2H4oM/0Asr8GBcGggS48OKTBQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EdNgX10IgPoeL5IZ3AUCqVLVOOe+vpudqH0m09grGYThi+IEro4cjNinKzeCKXZoGZs0ZDgun9FM9dWqJqv3leadYhY9hQFJIMIyGhqIDeE8fn7SYr1xry58PtlSLg2MpREztSsMtqVzwW0ngWghuU608E8vJp8jwgxY6gO+qe0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tldxYBra; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tldxYBra" Received: by smtp.kernel.org (Postfix) with ESMTPS id 94204C2BCC9; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618939; bh=CORvr0UdfFniwScEKu2H4oM/0Asr8GBcGggS48OKTBQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tldxYBraD+ZRljEUHZ+htX8s4lbwQyMS9nGaFCELUOKbDdhyeP99Aa5470WuCnA4R CqDPZSkVBwcU/I1r3D5GdIl8aWtp26QXHyGipcwUXiKzpF6E+AA6xEvogDWwnRoGfk b6jc5YDDKq0mmLpFrgFcLc4p1vCsHDYziaqmKICb17cA1qGnML5FO7t8cq/y0wXCW9 0qPDxGt7G/B8890WmGu24HwbPBBx2HiihIYqvIfBDeFXd1PGoB9Wz0v7aJHB47wmWE lVl5IjIxcBT+c4j3ZFP3628Ie8lvmIqibxO/XxLvauNhbVUDtB2tZwFcyGxWO5gzXD I48Dwq1+8g/3Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83425CD5BC9; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:20 +0100 Subject: [PATCH v14 03/12] lib: kstrtox: add kstrtoudec64() and kstrtodec64() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-3-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=4931; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=Pr5+NBfQy2PXMwkQMZ2Ccvc7BauaEGWsUrxgWkFdXyQ=; b=YAMwck6udsPaY1M75aI8QepsV5GHwyG8JaanUI/sTZN38CvT615i0Q/qD912vOMI8V73GE2yQ 6uw74rQnkGyBfq+/kgHuibRggK0ATQ2X9Mg0P86NXI2N2eYMblVE7qj X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add helpers that parses decimal numbers into 64-bit number, i.e., decimal point numbers with pre-defined scale are parsed into a 64-bit value (fixed precision). After the decimal point, digits beyond the specified scale are ignored. Signed-off-by: Rodrigo Alencar --- include/linux/kstrtox.h | 3 ++ lib/kstrtox.c | 100 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 103 insertions(+) diff --git a/include/linux/kstrtox.h b/include/linux/kstrtox.h index 6ea897222af1..bec2fc17bde0 100644 --- a/include/linux/kstrtox.h +++ b/include/linux/kstrtox.h @@ -97,6 +97,9 @@ int __must_check kstrtou8(const char *s, unsigned int bas= e, u8 *res); int __must_check kstrtos8(const char *s, unsigned int base, s8 *res); int __must_check kstrtobool(const char *s, bool *res); =20 +int __must_check kstrtoudec64(const char *s, unsigned int scale, u64 *res); +int __must_check kstrtodec64(const char *s, unsigned int scale, s64 *res); + int __must_check kstrtoull_from_user(const char __user *s, size_t count, u= nsigned int base, unsigned long long *res); int __must_check kstrtoll_from_user(const char __user *s, size_t count, un= signed int base, long long *res); int __must_check kstrtoul_from_user(const char __user *s, size_t count, un= signed int base, unsigned long *res); diff --git a/lib/kstrtox.c b/lib/kstrtox.c index bd63c55b8490..ab43d16659ce 100644 --- a/lib/kstrtox.c +++ b/lib/kstrtox.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include =20 @@ -407,6 +408,105 @@ int kstrtobool(const char *s, bool *res) } EXPORT_SYMBOL(kstrtobool); =20 +static int _kstrtoudec64(const char *s, unsigned int scale, u64 *res) +{ + u64 _res =3D 0; + unsigned int rv_int, rv_frac; + + rv_int =3D _parse_integer(s, 10, &_res); + if (rv_int & KSTRTOX_OVERFLOW) + return -ERANGE; + s +=3D rv_int; + + if (*s =3D=3D '.') + s++; /* skip decimal point */ + + rv_frac =3D _parse_integer_limit_init(s, 10, _res, &_res, scale); + if (rv_frac & KSTRTOX_OVERFLOW) + return -ERANGE; + s +=3D rv_frac; + + if (!rv_int && !rv_frac && !isdigit(*s)) + return -EINVAL; /* no digits at all */ + + while (isdigit(*s)) /* truncate digits */ + s++; + + if (*s =3D=3D '\n') + s++; + if (*s) + return -EINVAL; + + if (_res && (scale > (19 + rv_frac) || /* log10(2^64) =3D 19.26 */ + check_mul_overflow(_res, int_pow(10, scale - rv_frac), &_res))) + return -ERANGE; + + *res =3D _res; + return 0; +} + +/** + * kstrtoudec64() - Convert a string to an unsigned 64-bit value that repr= esents + * a scaled decimal number. + * @s: The start of the string. The string must be null-terminated, and ma= y also + * include a single newline before its terminating null. The first charac= ter + * may also be a plus sign, but not a minus sign. Digits beyond the speci= fied + * scale are ignored. + * @scale: The number of digits to the right of the decimal point. For exa= mple, + * a scale of 2 would mean the number is represented with two decimal pla= ces, + * so "123.45" would be represented as 12345. + * @res: Where to write the result of the conversion on success. + * + * Return: 0 on success, -ERANGE on overflow and -EINVAL on parsing error. + */ +noinline +int kstrtoudec64(const char *s, unsigned int scale, u64 *res) +{ + if (s[0] =3D=3D '+') + s++; + return _kstrtoudec64(s, scale, res); +} +EXPORT_SYMBOL(kstrtoudec64); + +/** + * kstrtodec64() - Convert a string to a signed 64-bit value that represen= ts a + * scaled decimal number. + * @s: The start of the string. The string must be null-terminated, and ma= y also + * include a single newline before its terminating null. The first charac= ter + * may also be a plus sign or a minus sign. Digits beyond the specified s= cale + * are ignored. + * @scale: The number of digits to the right of the decimal point. For exa= mple, + * a scale of 5 would mean the number is represented with five decimal pl= aces, + * so "-3.141592" would be represented as -314159. + * @res: Where to write the result of the conversion on success. + * + * Return: 0 on success, -ERANGE on overflow and -EINVAL on parsing error. + */ +noinline +int kstrtodec64(const char *s, unsigned int scale, s64 *res) +{ + u64 tmp; + int rv; + + if (s[0] =3D=3D '-') { + rv =3D _kstrtoudec64(s + 1, scale, &tmp); + if (rv < 0) + return rv; + if ((s64)-tmp > 0) + return -ERANGE; + *res =3D -tmp; + } else { + rv =3D kstrtoudec64(s, scale, &tmp); + if (rv < 0) + return rv; + if ((s64)tmp < 0) + return -ERANGE; + *res =3D tmp; + } + return 0; +} +EXPORT_SYMBOL(kstrtodec64); + /* * Since "base" would be a nonsense argument, this open-codes the * _from_user helper instead of using the helper macro below. --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDD8239060B; Sun, 24 May 2026 10:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618939; cv=none; b=iAFRDUNgARwLLGoOTCj9ybIos7XKnaJLbo4M+LRtr6SurXA3Brv/pK5rWi1ZL777glx95TNPvVDRdpGT536orDBerg2PnwKNVvXfKuaM1wzE3xmjbGxpcyPaND5DlNYS7ZVmZZd1Iu4+90W8xrDyWESFwQZfQLY8UUIZz98CfiM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618939; c=relaxed/simple; bh=ydOOETwVPIVdxokFO0pLH6Pbvwwut/iLOoUl42GwnbI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ubQ/yHy0W5rIle60Cs0Pb8QiFJQpQTmJ31hIDsEdRHYQSqUxvnN0p5lIW2C/AGtY0i7THwE9mT1eM6nXutiNtW2kZcYVja8pN/IdwmXE+zTdRCO3KURyO1eVHI2UE2iIKgnnvF5d6ACZGCu43cnlXQmgy2eLGuY8CmdDLFOAeFE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mQ1gTFdI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mQ1gTFdI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9CD7AC2BCF5; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618939; bh=ydOOETwVPIVdxokFO0pLH6Pbvwwut/iLOoUl42GwnbI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mQ1gTFdInnRyGvUdsl5r2Ge65GAvBp+5xtrtkzqjSN6o36n17Wx6BKVgZ0ZHyqrxn ajwIoI1TzaCkmm8EjDTCUhp2LXhwzx2riuEAzNe+L/YskD5zWioyboIwxVoN6poENP MTvnNCc3gMsMtweNGyYQL1RodC9QLdhWuG/koiw2dZo4QmkSyjgh/jeDYc6a0NtQR6 mLVt3DkH2BHDFdFW3iz/xL2Txq4ToB3wHlPSa1/7c2gwex0PS+qj4v9Yz9fqRMZXMl 4WTq4zaaUpnvZCBlwLlRph8koHwD8+PdMgMnHOFkfXfxTt5omGHMSnG5XoUFOxBOtc gMiE5RV9YYjHA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93530CD5BC8; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:21 +0100 Subject: [PATCH v14 04/12] lib: test-kstrtox: tests for kstrtodec64() and kstrtoudec64() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-4-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=5961; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=ILKtuoSEjAYtcOeMxSGbbH39S1bSrTsjARVlbHrXTsc=; b=6wNfjMN/cJaDXnAal7rirsALXl5zm8yAEp+XJRAxB/XR4GAVMROqjnJSMXf/cYtMfN5sOPPKD 31mtbw/TbYBAQG4EDk8Ak4jTAjIKy/I9K/LAqtPtwhVFAk2njadd2Dl X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add tests for decimal parsing helpers kstrtodec64() and kstrtoudec64(). The test infrastructure is reused from other kstrto*() functions, i.e., the decimal parsers have fixed base of 10, so base field is used as scale input for the helpers. Reviewed-by: Andy Shevchenko Signed-off-by: Rodrigo Alencar --- lib/test-kstrtox.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 182 insertions(+) diff --git a/lib/test-kstrtox.c b/lib/test-kstrtox.c index ee87fef66cb5..145d268bbccc 100644 --- a/lib/test-kstrtox.c +++ b/lib/test-kstrtox.c @@ -703,6 +703,182 @@ static void __init test_kstrtos8_fail(void) TEST_FAIL(kstrtos8, s8, "%hhd", test_s8_fail); } =20 +static void __init test_kstrtoudec64_ok(void) +{ + DECLARE_TEST_OK(u64, struct test_udec64); + static DEFINE_TEST_OK(struct test_udec64, test_udec64_ok) =3D { + /* basic: integer.fraction, exact digits */ + {"0.0", 1, 0}, + {"1.5", 1, 15}, + {"1.234", 3, 1234}, + {"42.0", 1, 420}, + /* zero */ + {"0.0", 1, 0}, + {"0.000", 3, 0}, + /* integer only */ + {"0", 1, 0}, + {"42", 3, 42000}, + {"123.", 2, 12300}, + {"1", 1, 10}, + /* fractional only (leading dot) */ + {".5", 1, 5}, + {".5", 0, 0}, + {".123", 3, 123}, + {".001", 3, 1}, + /* zero padding: fewer fractional digits than scale */ + {"1.2", 3, 1200}, + {"1.2", 6, 1200000}, + {"0.01", 3, 10}, + {"0.1", 9, 100000000ULL}, + {"0.01", 9, 10000000}, + /* truncation: more fractional digits than scale */ + {"1.23456", 3, 1234}, + {"3.1415926535", 6, 3141592}, + {"0.999999999", 3, 999}, + {"1.99", 1, 19}, + {"1.234", 0, 1}, + /* trailing newline */ + {"1.5\n", 1, 15}, + {"42\n", 3, 42000}, + /* plus sign */ + {"+1.5", 1, 15}, + {"+.5", 1, 5}, + /* scale progression */ + {"1.", 0, 1}, + {"1.0", 1, 10}, + {"1.00", 2, 100}, + {"1.000", 3, 1000}, + {"1.000000", 6, 1000000}, + {"1.000000000", 9, 1000000000ULL}, + /* max limit check */ + {"18446744073.709551615", 9, ULLONG_MAX}, + {"18446744073709.551615", 6, ULLONG_MAX}, + {"0.18446744073709551615", 20, ULLONG_MAX}, + /* scale > 19: representable when integer part is small */ + {"0.00000000000000000001", 20, 1}, + {"0.1", 20, 10000000000000000000ULL}, + {"0.00000000000000000000001", 23, 1}, + /* truncation with scale > 19 */ + {"0.0000000000000000000012345", 23, 123}, + /* truncation with many excess digits */ + {"0.00000000000000000000000000000000423", 34, 42}, + {"1.99999999999999999999999999999999999", 3, 1999}, + }; + TEST_OK(kstrtoudec64, u64, "%llu", test_udec64_ok); +} + +static void __init test_kstrtoudec64_fail(void) +{ + static DEFINE_TEST_FAIL(test_udec64_fail) =3D { + /* empty / whitespace */ + {"", 3}, + {"\n", 3}, + /* minus sign (unsigned) */ + {"-1.5", 1}, + {"-0.5", 1}, + /* only a decimal point */ + {".", 3}, + {".", 0}, + /* only a sign */ + {"+", 3}, + /* non-digit characters */ + {"abc", 3}, + {"1.2x", 3}, + /* leading/trailing space */ + {" 1.5", 1}, + {"1.5 ", 1}, + /* overflow */ + {"18446744073710.551615", 6}, + {"99999999999999999999", 1}, + /* overflow with scale > 19 */ + {"1.0", 21}, + {"0.2", 20}, + {"0.18446744073709551616", 20}, + {"1", 20}, + }; + TEST_FAIL(kstrtoudec64, u64, "%llu", test_udec64_fail); +} + +static void __init test_kstrtodec64_ok(void) +{ + DECLARE_TEST_OK(s64, struct test_dec64); + static DEFINE_TEST_OK(struct test_dec64, test_dec64_ok) =3D { + /* basic positive */ + {"0.0", 1, 0}, + {"1.5", 1, 15}, + {"1.234", 3, 1234}, + /* basic negative */ + {"-1.5", 1, -15}, + {"-1.234", 3, -1234}, + {"-0.5", 1, -5}, + {"-0.001", 3, -1}, + /* zero (signed) */ + {"-0", 1, 0}, + {"-0.0", 1, 0}, + {"0.000", 3, 0}, + /* integer only */ + {"42", 3, 42000}, + {"-42", 3, -42000}, + /* fractional only */ + {".5", 1, 5}, + {"-.5", 1, -5}, + /* zero padding */ + {"1.2", 3, 1200}, + {"-1.2", 3, -1200}, + {"0.01", 3, 10}, + {"-0.01", 3, -10}, + /* truncation */ + {"1.23456", 3, 1234}, + {"-1.23456", 3, -1234}, + {"0.999999999", 3, 999}, + {"-0.999999999", 3, -999}, + /* trailing newline */ + {"1.5\n", 1, 15}, + {"-1.5\n", 1, -15}, + /* plus sign */ + {"+1.5", 1, 15}, + /* limits */ + {"9223372036.854775807", 9, LLONG_MAX}, + {"-9223372036.854775808", 9, LLONG_MIN}, + /* scale > 19 */ + {"0.0", 20, 0}, + {"-0.0", 20, 0}, + {"0.00000000000000000001", 20, 1}, + {"-0.00000000000000000001", 20, -1}, + {"0.009223372036854775807", 21, LLONG_MAX}, + {"-0.009223372036854775808", 21, LLONG_MIN}, + }; + TEST_OK(kstrtodec64, s64, "%lld", test_dec64_ok); +} + +static void __init test_kstrtodec64_fail(void) +{ + static DEFINE_TEST_FAIL(test_dec64_fail) =3D { + /* empty / whitespace */ + {"", 3}, + {"\n", 3}, + /* no digits after dot */ + {".", 3}, + {"-.", 3}, + /* no digits at all */ + {"+", 3}, + {"-", 3}, + /* non-digit characters */ + {"abc", 3}, + {"-1.2x", 3}, + /* signed overflow */ + {"9223372036.854775808", 9}, + {"-9223372036.854775809", 9}, + {"99999999999999999999", 1}, + /* signed overflow with scale > 19 */ + {"0.1", 20}, + {"-0.1", 20}, + {"0.09223372036854775808", 20}, + {"-0.09223372036854775809", 20}, + }; + TEST_FAIL(kstrtodec64, s64, "%lld", test_dec64_fail); +} + static int __init test_kstrtox_init(void) { test_kstrtoull_ok(); @@ -729,6 +905,12 @@ static int __init test_kstrtox_init(void) test_kstrtou8_fail(); test_kstrtos8_ok(); test_kstrtos8_fail(); + + test_kstrtoudec64_ok(); + test_kstrtoudec64_fail(); + test_kstrtodec64_ok(); + test_kstrtodec64_fail(); + return -EINVAL; } module_init(test_kstrtox_init); --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CD89391E49; Sun, 24 May 2026 10:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; cv=none; b=UszUPaIxHa6bq5b0ReqB0qSfELIhGIFzkI9k97lbg1H/s3fyHVz/wQoyhadF2IxrcJzhOAxWPeWq2DwscQkzSGuQrYVyPBfcgzcErnhn46MvX9qCsePWQfD83qjj+rLPScYDYr/FMJ7+PaT8cvptVgjUV1pJrXQ8bDnDlghB7kU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; c=relaxed/simple; bh=0MiPE4pAGNIHkDMT5fwtfqtbshqWVCMkNClPirEcpH4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jhht3wja8lQFPSIhSYGLFqatFHyeilXGjRZXQNjZ3KXGyQoRxVFT0VEFPZvHGz0jDK+5GlVk1f5xU1kMs6yuiItFAAgQUxT90X6bTCylv5hvfmCLg5DQYdEN5M/T7BnI258ZUSQX0304pjDmbFkmYNFXBM29d/jK45zwihXb1X8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jkLJDzTU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jkLJDzTU" Received: by smtp.kernel.org (Postfix) with ESMTPS id B5550C2BCFD; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618939; bh=0MiPE4pAGNIHkDMT5fwtfqtbshqWVCMkNClPirEcpH4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jkLJDzTUL+gBGYOIaiFjuI0yhqHTKco6TPkNF+rAH6gbzFhR62u/nG/RrcXYIoZaV Yt0vP4m/9IYC/KzTqr/K7H2xSoOEcVuaHXlJzvNjtxq9WpEoTjpT5q2SA9gndpp1Hh sLyJNpSkA+qPMyItHzzDj8pa/x088Aonv23TAO1v7Pm0U3YYzVMaI+Uscr3KquGCX9 h85Z5j9PcSmvgSIKjUiScVP5aX6yQHgEljLFUJdZNIkACUtJQ/QFNokTUyQT7pyNJr 29qpq5i4a9bVCn/MXtk3dY+xH36StjmkRFb5y9CR7g8tPKIFGr1viPZ1MFAngSHnuZ 6fIP+w27cXOBw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A23FDCD5BCA; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:22 +0100 Subject: [PATCH v14 05/12] lib: math: div64: add div64_s64_rem() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-5-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=2327; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=ROKa5iAD0w5bgrXddKrko8IjoFXS2V0nXvPl5DFoZoI=; b=TTPDdayI072fUDtInDbn7l1LhIxuC1ll5ixSwLmS7xwzjbRdggfd09rwzTvGCmHWFZAhNODSl lJdQ3/nfsVmBmaDbnWI6dpR1GRTTWVsg7XsduFgysWUD1547NJ+wkio X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add div64_s64_rem() function, with 32-bit implementation that uses div64_u64_rem() and a branchless approach to resolve the sign of the remainder and quotient (negation in two's complement). Reviewed-by: Andy Shevchenko Signed-off-by: Rodrigo Alencar --- include/linux/math64.h | 18 ++++++++++++++++++ lib/math/div64.c | 15 +++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/include/linux/math64.h b/include/linux/math64.h index cc305206d89f..99189410d4bb 100644 --- a/include/linux/math64.h +++ b/include/linux/math64.h @@ -57,6 +57,20 @@ static inline u64 div64_u64_rem(u64 dividend, u64 diviso= r, u64 *remainder) return dividend / divisor; } =20 +/** + * div64_s64_rem - signed 64bit divide with 64bit divisor and remainder + * @dividend: signed 64bit dividend + * @divisor: signed 64bit divisor + * @remainder: pointer to signed 64bit remainder + * + * Return: sets ``*remainder``, then returns dividend / divisor + */ +static inline s64 div64_s64_rem(s64 dividend, s64 divisor, s64 *remainder) +{ + *remainder =3D dividend % divisor; + return dividend / divisor; +} + /** * div64_u64 - unsigned 64bit divide with 64bit divisor * @dividend: unsigned 64bit dividend @@ -102,6 +116,10 @@ extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 = *remainder); extern u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder); #endif =20 +#ifndef div64_s64_rem +extern s64 div64_s64_rem(s64 dividend, s64 divisor, s64 *remainder); +#endif + #ifndef div64_u64 extern u64 div64_u64(u64 dividend, u64 divisor); #endif diff --git a/lib/math/div64.c b/lib/math/div64.c index d1e92ea24fce..0b10ded09a9b 100644 --- a/lib/math/div64.c +++ b/lib/math/div64.c @@ -158,6 +158,21 @@ u64 div64_u64(u64 dividend, u64 divisor) EXPORT_SYMBOL(div64_u64); #endif =20 +#ifndef div64_s64_rem +s64 div64_s64_rem(s64 dividend, s64 divisor, s64 *remainder) +{ + s64 quot, t, rem; + + quot =3D div64_u64_rem(abs(dividend), abs(divisor), (u64 *)&rem); + t =3D dividend >> 63; + *remainder =3D (rem ^ t) - t; + t =3D (dividend ^ divisor) >> 63; + + return (quot ^ t) - t; +} +EXPORT_SYMBOL(div64_s64_rem); +#endif + #ifndef div64_s64 s64 div64_s64(s64 dividend, s64 divisor) { --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 245D0391E64; Sun, 24 May 2026 10:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; cv=none; b=rSEeSvvmbYM/b++bhVAX4GD2BaqYrP3L2fpjSuhylITXcqRFg1K1BggPrcJvJOwWwCZD5DXq8bX6aRFfkiaq7Q36KMxvHCGB4J0Dj6yVWwPlDjVRaDtBO/X7zYmv/ing3hi8vOK1dZAnmysITi7oQcppnzVpz5/sqTonNwpF/AQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; c=relaxed/simple; bh=jmpMYdIAUQwMXnymSTHrAyeNBIsURcIx4i7V6hRSHI8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jOaYQexS6r48L6kdYW5ld5DlZidjlLYi4M0gwYPjOmAJV6GuAOYIpqUtw/YzHIyPkRllyTHZQt7ZuFtZgYUraE4gSa4P2Mz9YJdKQa3AcdNCDJactuWwASVYVzwfVOBtMLW+e+yFe28YO28gCSjda2W/Hp5PnaWu1IWiAKfkj40= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kHQ+WnGc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kHQ+WnGc" Received: by smtp.kernel.org (Postfix) with ESMTPS id B96A7C2BD01; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618939; bh=jmpMYdIAUQwMXnymSTHrAyeNBIsURcIx4i7V6hRSHI8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kHQ+WnGcu98o+30+MsDLOQ2CyL9148XgrQoBRJSnJtyVEON1u41PRfbzBEts4btIT eSCj+ewnUEtRVuRs2zrBq+0vBdOCIbK/I3wGRqne5ddAJoZALyJ7DXXRUxzeSse4qn VL9v9+y8N4jobi7cMYrNXpe8jjun9A7AjORbEYHvJ2/s+cW0yZZ7ivuTaPlVMe87Ia 1DoToqxRCjZ1BbeFXkz0WMdZ8ZxNuu/JpGKYVKi0AGaQcVdquZw0eIfIuO7vL6Rsw6 A6WR5cTPorBLQj6wbWCRV1eVBUbo3D2nzHUhKW6JrJZsCP2V5sPM7yaQFqp5QQ2Gnu NaK3xfVtzyYvQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE5E7CD5BAB; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:23 +0100 Subject: [PATCH v14 06/12] iio: core: add decimal value formatting into 64-bit value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-6-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=6182; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=QMpUYZEXYXwnvsDVpW1EnRH1hiYPiI4UJaERVqd0EzQ=; b=ZSUzmXqoeHVUJ0C/gIirGYxgXbeolceBi70BPP3WVQ4UwUh46u6cBkLRWiE3Q+zbeR5I0S5aZ e8ed3at1mgZC9dOdoWCiBHU7LwK0VfgBBS1aaBd0MRYOrVZ1PIgvxBe X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Create new format types for iio values (IIO_VAL_DECIMAL64_*), which defines the representation of fixed decimal point values into a single 64-bit number. This new format increases the range of represented values, allowing for integer parts greater than 2^32, as bits are not "wasted" in the fractional part, which can be seen in IIO_VAL_INT_PLUS_MICRO and IIO_VAL_INT_PLUS_NANO. Helpers are created to compose and decompose 64-bit decimals into integer values used in IIO formatting interfaces, which creates consistency and avoid error-prone manual assignments when using wordpart macros. When doing the parsing, kstrtodec64() is used with the scale defined by the specific decimal format type. Signed-off-by: Rodrigo Alencar --- drivers/iio/industrialio-core.c | 47 +++++++++++++++++++++++++++++++++----= ---- include/linux/iio/types.h | 30 ++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 9 deletions(-) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-cor= e.c index bd6f4f9f4533..a88088cac641 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -26,7 +27,6 @@ #include #include #include -#include =20 #include #include @@ -655,6 +655,7 @@ static ssize_t __iio_format_value(char *buf, size_t off= set, unsigned int type, int size, const int *vals) { int tmp0, tmp1; + int l =3D 0; s64 tmp2; bool scale_db =3D false; =20 @@ -698,7 +699,6 @@ static ssize_t __iio_format_value(char *buf, size_t off= set, unsigned int type, case IIO_VAL_INT_MULTIPLE: { int i; - int l =3D 0; =20 for (i =3D 0; i < size; ++i) l +=3D sysfs_emit_at(buf, offset + l, "%d ", vals[i]); @@ -707,8 +707,25 @@ static ssize_t __iio_format_value(char *buf, size_t of= fset, unsigned int type, case IIO_VAL_CHAR: return sysfs_emit_at(buf, offset, "%c", (char)vals[0]); case IIO_VAL_INT_64: - tmp2 =3D (s64)((((u64)vals[1]) << 32) | (u32)vals[0]); + tmp2 =3D iio_val_s64_from_s32s(vals); return sysfs_emit_at(buf, offset, "%lld", tmp2); + case IIO_VAL_DECIMAL64_MILLI: + case IIO_VAL_DECIMAL64_MICRO: + case IIO_VAL_DECIMAL64_NANO: + case IIO_VAL_DECIMAL64_PICO: + { + int scale =3D type - IIO_VAL_DECIMAL64_BASE; + s64 frac; + + tmp2 =3D div64_s64_rem(iio_val_s64_from_s32s(vals), + int_pow(10, scale), &frac); + if (tmp2 =3D=3D 0 && frac < 0) + l +=3D sysfs_emit_at(buf, offset, "-"); + + l +=3D sysfs_emit_at(buf, offset + l, "%lld.%0*lld", tmp2, scale, + abs(frac)); + return l; + } default: return 0; } @@ -978,6 +995,7 @@ static ssize_t iio_write_channel_info(struct device *de= v, struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); int ret, fract_mult =3D 100000; + int type, dec_scale =3D 0; int integer, fract =3D 0; long long integer64; bool is_char =3D false; @@ -988,9 +1006,11 @@ static ssize_t iio_write_channel_info(struct device *= dev, if (!indio_dev->info->write_raw) return -EINVAL; =20 - if (indio_dev->info->write_raw_get_fmt) - switch (indio_dev->info->write_raw_get_fmt(indio_dev, - this_attr->c, this_attr->address)) { + if (indio_dev->info->write_raw_get_fmt) { + type =3D indio_dev->info->write_raw_get_fmt(indio_dev, + this_attr->c, + this_attr->address); + switch (type) { case IIO_VAL_INT: fract_mult =3D 0; break; @@ -1006,12 +1026,19 @@ static ssize_t iio_write_channel_info(struct device= *dev, case IIO_VAL_CHAR: is_char =3D true; break; + case IIO_VAL_DECIMAL64_MILLI: + case IIO_VAL_DECIMAL64_MICRO: + case IIO_VAL_DECIMAL64_NANO: + case IIO_VAL_DECIMAL64_PICO: + dec_scale =3D type - IIO_VAL_DECIMAL64_BASE; + fallthrough; case IIO_VAL_INT_64: is_64bit =3D true; break; default: return -EINVAL; } + } =20 if (is_char) { char ch; @@ -1020,12 +1047,14 @@ static ssize_t iio_write_channel_info(struct device= *dev, return -EINVAL; integer =3D ch; } else if (is_64bit) { - ret =3D kstrtoll(buf, 0, &integer64); + if (dec_scale) + ret =3D kstrtodec64(buf, dec_scale, &integer64); + else + ret =3D kstrtoll(buf, 0, &integer64); if (ret) return ret; =20 - fract =3D upper_32_bits(integer64); - integer =3D lower_32_bits(integer64); + iio_val_s64_decompose(integer64, &integer, &fract); } else { ret =3D __iio_str_to_fixpoint(buf, fract_mult, &integer, &fract, scale_db); diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h index 4e3099defc1d..a47a3d7500c9 100644 --- a/include/linux/iio/types.h +++ b/include/linux/iio/types.h @@ -7,6 +7,9 @@ #ifndef _IIO_TYPES_H_ #define _IIO_TYPES_H_ =20 +#include +#include + #include =20 enum iio_event_info { @@ -34,6 +37,33 @@ enum iio_event_info { #define IIO_VAL_FRACTIONAL_LOG2 11 #define IIO_VAL_CHAR 12 =20 +#define IIO_VAL_DECIMAL64_BASE 32 +#define IIO_VAL_DECIMAL64_MILLI (IIO_VAL_DECIMAL64_BASE + 3) +#define IIO_VAL_DECIMAL64_MICRO (IIO_VAL_DECIMAL64_BASE + 6) +#define IIO_VAL_DECIMAL64_NANO (IIO_VAL_DECIMAL64_BASE + 9) +#define IIO_VAL_DECIMAL64_PICO (IIO_VAL_DECIMAL64_BASE + 12) + +static inline s64 iio_val_s64_compose(s32 val0, s32 val1) +{ + return (s64)(((u64)val1 << 32) | (u32)val0); +} + +static inline s64 iio_val_s64_from_s32s(const s32 *vals) +{ + return iio_val_s64_compose(vals[0], vals[1]); +} + +static inline void iio_val_s64_decompose(s64 dec64, s32 *val0, s32 *val1) +{ + *val0 =3D lower_32_bits(dec64); + *val1 =3D upper_32_bits(dec64); +} + +static inline void iio_val_s64_to_s32s(s64 dec64, s32 *vals) +{ + iio_val_s64_decompose(dec64, &vals[0], &vals[1]); +} + enum iio_available_type { IIO_AVAIL_LIST, IIO_AVAIL_RANGE, --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D42E391E5B; Sun, 24 May 2026 10:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; cv=none; b=laJK1Ldqu5KKS/kgmnkPvN5/eafP7hOVEXl7INm3fFvDmo3bJB6zRzDn9q7XmALFyLRaKrkA09im0Tc9211fzHHww7/gPtGv20jPTZSdUU7eek2RBTtlgxAjHIwi6vVHXOGdEYZzN4SfShCy7xUIoEXIVAN+DkoDcDHFxgszV3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; c=relaxed/simple; bh=BTfw4ErnUQlufZ6+Ud+aw9Xar0RlSj6UdoqRtZhXHSA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EWO+PItQ8+8+2gbVfZh1itAt9Ada2yI/dfEHtHKUcNXikeVtcvHtEeEShLOp2xZ2yBLXLK4++0bjBL97lP8NlS4q8jmAUrNm/lu04uzpzgAe1G7qtE9RLtxXSVQFIs31XrotcrAt5yNNMGqWrT7ijNAcENqKdXKSWSHqto6S7Gw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eFgECLP7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eFgECLP7" Received: by smtp.kernel.org (Postfix) with ESMTPS id C5010C32786; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618939; bh=BTfw4ErnUQlufZ6+Ud+aw9Xar0RlSj6UdoqRtZhXHSA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eFgECLP7wrmDhOEwFfyE2WgS4Oa3P497mxf1n1BxjCIY8Sw4heoHTVU4GLtz0QdcX Og23KtsxaWh2V1p/JuaDxpiuJ3mY+CzSMXXks1b0R0jUYW1AXi91y97IoxyQWh57Wk v3CAOeE+2HKuu5DGICC8em8NTejadEo447Fa7WDa0pngPwTu9uaEMDQ9QVQ103cnPF Mgwj+9LKmv1npc6CpstuiaSdQA/UQqvj4cKDT9FDcq3R2iTK50DNo9/HuEcb/9v1Zb rWTghExRZHQwOvdBsd1P0K5rB6WtsjSvfaJc0591RSL++DYLZaxUX8kWDoMAna2obw VMsDSzFdUyJhQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCD73CD5BB1; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:24 +0100 Subject: [PATCH v14 07/12] iio: test: iio-test-format: add test case for decimal format Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-7-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=6587; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=0lpyDhmAFr7NU6uTBMJtxvjRKP6i/Gy9oeerjG9/EKc=; b=Dt1oyxnv5JlaLCqGr0nXBRk/upfLLkby7Cz36CgKaqd7oQIdx0GYlnZoCimUqlQ1MM4VvdZoh BB3Ncl1q2HXCSgVPsVwhGbpjYTDyFCgDF0HF6Llx1XNQPrv+wIljXim X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add iio_test_iio_format_value_decimal_64() kunit test case for decimal value formatting, exploring different scales types. Also, the same iio_val_s64_to_s32s() macro used to populate local array is used in iio_test_iio_format_value_integer_64(). Signed-off-by: Rodrigo Alencar --- drivers/iio/test/iio-test-format.c | 97 +++++++++++++++++++++++++++++-----= ---- 1 file changed, 75 insertions(+), 22 deletions(-) diff --git a/drivers/iio/test/iio-test-format.c b/drivers/iio/test/iio-test= -format.c index 872dd8582003..1920dee3bfb0 100644 --- a/drivers/iio/test/iio-test-format.c +++ b/drivers/iio/test/iio-test-format.c @@ -200,56 +200,108 @@ static void iio_test_iio_format_value_multiple(struc= t kunit *test) static void iio_test_iio_format_value_integer_64(struct kunit *test) { int values[2]; - s64 value; char *buf; int ret; =20 buf =3D kunit_kmalloc(test, PAGE_SIZE, GFP_KERNEL); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); =20 - value =3D 24; - values[0] =3D lower_32_bits(value); - values[1] =3D upper_32_bits(value); + iio_val_s64_to_s32s(24, values); ret =3D iio_format_value(buf, IIO_VAL_INT_64, ARRAY_SIZE(values), values); IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "24\n"); =20 - value =3D -24; - values[0] =3D lower_32_bits(value); - values[1] =3D upper_32_bits(value); + iio_val_s64_to_s32s(-24, values); ret =3D iio_format_value(buf, IIO_VAL_INT_64, ARRAY_SIZE(values), values); IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "-24\n"); =20 - value =3D 0; - values[0] =3D lower_32_bits(value); - values[1] =3D upper_32_bits(value); + iio_val_s64_to_s32s(0, values); ret =3D iio_format_value(buf, IIO_VAL_INT_64, ARRAY_SIZE(values), values); IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "0\n"); =20 - value =3D UINT_MAX; - values[0] =3D lower_32_bits(value); - values[1] =3D upper_32_bits(value); + iio_val_s64_to_s32s(UINT_MAX, values); ret =3D iio_format_value(buf, IIO_VAL_INT_64, ARRAY_SIZE(values), values); IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "4294967295\n"); =20 - value =3D -((s64)UINT_MAX); - values[0] =3D lower_32_bits(value); - values[1] =3D upper_32_bits(value); + iio_val_s64_to_s32s(-((s64)UINT_MAX), values); ret =3D iio_format_value(buf, IIO_VAL_INT_64, ARRAY_SIZE(values), values); IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "-4294967295\n"); =20 - value =3D LLONG_MAX; - values[0] =3D lower_32_bits(value); - values[1] =3D upper_32_bits(value); + iio_val_s64_to_s32s(LLONG_MAX, values); ret =3D iio_format_value(buf, IIO_VAL_INT_64, ARRAY_SIZE(values), values); IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "9223372036854775807\n"); =20 - value =3D LLONG_MIN; - values[0] =3D lower_32_bits(value); - values[1] =3D upper_32_bits(value); + iio_val_s64_to_s32s(LLONG_MIN, values); ret =3D iio_format_value(buf, IIO_VAL_INT_64, ARRAY_SIZE(values), values); IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "-9223372036854775808\n"); } =20 +static void iio_test_iio_format_value_decimal_64(struct kunit *test) +{ + int values[2]; + char *buf; + int ret; + + buf =3D kunit_kmalloc(test, PAGE_SIZE, GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); + + /* DECIMAL64_MILLI: positive >=3D 1, value 1.234 */ + iio_val_s64_to_s32s(1234, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MILLI, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "1.234\n"); + + /* DECIMAL64_MICRO: positive >=3D 1, value 3.141592 */ + iio_val_s64_to_s32s(3141592, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MICRO, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "3.141592\n"); + + /* DECIMAL64_MILLI: positive < 1, value 0.042 */ + iio_val_s64_to_s32s(42, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MILLI, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "0.042\n"); + + /* DECIMAL64_MILLI: negative <=3D -1, value -1.234 */ + iio_val_s64_to_s32s(-1234, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MILLI, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "-1.234\n"); + + /* DECIMAL64_MILLI: negative > -1, value -0.123 */ + iio_val_s64_to_s32s(-123, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MILLI, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "-0.123\n"); + + /* DECIMAL64_MILLI: zero */ + iio_val_s64_to_s32s(0, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MILLI, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "0.000\n"); + + /* DECIMAL64_NANO: value 1.000000001 */ + iio_val_s64_to_s32s(1000000001, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_NANO, ARRAY_SIZE(values),= values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "1.000000001\n"); + + /* DECIMAL64_MICRO: large value using upper 32 bits */ + iio_val_s64_to_s32s(5000000000000042LL, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MICRO, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "5000000000.000042\n"); + + /* limits */ + iio_val_s64_to_s32s(LLONG_MAX, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_PICO, ARRAY_SIZE(values),= values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "9223372.036854775807\n"); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_NANO, ARRAY_SIZE(values),= values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "9223372036.854775807\n"); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MICRO, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "9223372036854.775807\n"); + + iio_val_s64_to_s32s(LLONG_MIN, values); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_PICO, ARRAY_SIZE(values),= values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "-9223372.036854775808\n"); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_NANO, ARRAY_SIZE(values),= values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "-9223372036.854775808\n"); + ret =3D iio_format_value(buf, IIO_VAL_DECIMAL64_MICRO, ARRAY_SIZE(values)= , values); + IIO_TEST_FORMAT_EXPECT_EQ(test, buf, ret, "-9223372036854.775808\n"); +} + static struct kunit_case iio_format_test_cases[] =3D { KUNIT_CASE(iio_test_iio_format_value_integer), KUNIT_CASE(iio_test_iio_format_value_fixedpoint), @@ -257,6 +309,7 @@ static struct kunit_case iio_format_test_cases[] =3D { KUNIT_CASE(iio_test_iio_format_value_fractional_log2), KUNIT_CASE(iio_test_iio_format_value_multiple), KUNIT_CASE(iio_test_iio_format_value_integer_64), + KUNIT_CASE(iio_test_iio_format_value_decimal_64), { } }; =20 --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CEBA391E55; Sun, 24 May 2026 10:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; cv=none; b=co4+E3fQBcCUUwML4x/USeXGdOUADNp2nrb+ZqmDUGaLPY7uPg/Lcrkyrw9FLsGegjruzBWJ9BVtJsZiflNNrIB/IBW9YdevJm/TMFSM71LZHNNm7b5bVcBnr+jnlj2L4xlhXh7SYVqvoQEkyK30FL1FONdrfLQGhwnrrE+k6qo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; c=relaxed/simple; bh=h6OYpihPGmSY0Y0KAMYGHffFNQ3NmVHtDTV5AXEeyNU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uHkyZ/bxCkF/0M3Javp10HTpmgsd5cxbbN4inXITkR/w1TbbVVP8vDckV5XlcPw+wvG4cGwVCigrx2eFtVklDTJLOlQs3R2wJkDxNi5DiZAFGSC4KgUK5wnfyE5rqifRpu6kVuUvm8i2hlZg3yzOOV/tYMBdG2FaMwXoLEpAp2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cUIX3r1M; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cUIX3r1M" Received: by smtp.kernel.org (Postfix) with ESMTPS id D488BC2BCFF; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618939; bh=h6OYpihPGmSY0Y0KAMYGHffFNQ3NmVHtDTV5AXEeyNU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cUIX3r1MRCD5avF8MFBObrB2OGsUYPgtP8VM9bsRznnjyrsS51hmD8PqyxAI8gvzC K0eLikk1Hdiq6kkUtOPFLIsAY1oKMzzj9TKpM+bHQluzizIP8AHh14X0iOBsgAesKZ yBaIiLBp9yGHRrQwfbVKA/r6ZaItB0h0hGUqp/PoE3lv10EGbZMc8WNSZ5bpAs0pgn GX3x9sRL5xjXD8UOmPG5UqzoNC7T0TgFZwKPBFb12SqosXuTd532DJMW6AXZwjfxr0 JqdzzVJnHkrFYYdVPN7LBVNrvgpsdRsq0wi8+R3YsZIhzOgxwd+y2z6J56RnP5/MVJ bWVWB32nDmx0g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD15BCD5BC9; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:25 +0100 Subject: [PATCH v14 08/12] iio: frequency: adf41513: driver implementation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-8-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=38708; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=PYq2xVeZRI7tQw0p0A/sZqYkz7VZSIWaoHEsNXD1kxk=; b=aMZhDw6I4atmSya4746OUShI7x9dUkItORbPsCsewlcfX5UQi0y73ncBKPBHVcwCB+T8rmrdy Jbq5YrYFUleDwlFbnDJnLL4x5Uj7UmMDWq1mez7Kh8PcY2ZmF5V6Ad1 X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar The driver is based on existing PLL drivers in the IIO subsystem and implements the following key features: - Integer-N and fractional-N (fixed/variable modulus) synthesis modes; - High-resolution frequency calculations using microhertz (=C2=B5Hz) precis= ion to handle sub-Hz resolution across multi-GHz frequency ranges; - IIO debugfs interface for direct register access; - FW property parsing from devicetree including charge pump settings and reference path configuration; - Power management support with suspend/resume callbacks; - Lock detect GPIO monitoring. Signed-off-by: Rodrigo Alencar --- MAINTAINERS | 1 + drivers/iio/frequency/Kconfig | 10 + drivers/iio/frequency/Makefile | 1 + drivers/iio/frequency/adf41513.c | 1109 ++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 1121 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e1c3a26a6e2f..6d695913e717 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1668,6 +1668,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml +F: drivers/iio/frequency/adf41513.c =20 ANALOG DEVICES INC ADF4377 DRIVER M: Antoniu Miclaus diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index 583cbdf4e8cd..90c6304c4bcd 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -29,6 +29,16 @@ endmenu =20 menu "Phase-Locked Loop (PLL) frequency synthesizers" =20 +config ADF41513 + tristate "Analog Devices ADF41513 PLL Frequency Synthesizer" + depends on SPI + help + Say yes here to build support for Analog Devices ADF41513 + 26.5 GHz Integer-N/Fractional-N PLL Frequency Synthesizer. + + To compile this driver as a module, choose M here: the + module will be called adf41513. + config ADF4350 tristate "Analog Devices ADF4350/ADF4351 Wideband Synthesizers" depends on SPI diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index 70d0e0b70e80..53b4d01414d8 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -5,6 +5,7 @@ =20 # When adding new entries keep the list in alphabetical order obj-$(CONFIG_AD9523) +=3D ad9523.o +obj-$(CONFIG_ADF41513) +=3D adf41513.o obj-$(CONFIG_ADF4350) +=3D adf4350.o obj-$(CONFIG_ADF4371) +=3D adf4371.o obj-$(CONFIG_ADF4377) +=3D adf4377.o diff --git a/drivers/iio/frequency/adf41513.c b/drivers/iio/frequency/adf41= 513.c new file mode 100644 index 000000000000..6f952ccc675e --- /dev/null +++ b/drivers/iio/frequency/adf41513.c @@ -0,0 +1,1109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ADF41513 SPI PLL Frequency Synthesizer driver + * + * Copyright 2026 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Registers */ +#define ADF41513_REG0 0 +#define ADF41513_REG1 1 +#define ADF41513_REG2 2 +#define ADF41513_REG3 3 +#define ADF41513_REG4 4 +#define ADF41513_REG5 5 +#define ADF41513_REG6 6 +#define ADF41513_REG7 7 +#define ADF41513_REG8 8 +#define ADF41513_REG9 9 +#define ADF41513_REG10 10 +#define ADF41513_REG11 11 +#define ADF41513_REG12 12 +#define ADF41513_REG13 13 +#define ADF41513_REG_NUM 14 + +#define ADF41513_SYNC_REG0 BIT(ADF41513_REG0) +#define ADF41513_SYNC_REG1 BIT(ADF41513_REG1) +#define ADF41513_SYNC_REG2 BIT(ADF41513_REG2) +#define ADF41513_SYNC_REG3 BIT(ADF41513_REG3) +#define ADF41513_SYNC_REG4 BIT(ADF41513_REG4) +#define ADF41513_SYNC_REG5 BIT(ADF41513_REG5) +#define ADF41513_SYNC_REG6 BIT(ADF41513_REG6) +#define ADF41513_SYNC_REG7 BIT(ADF41513_REG7) +#define ADF41513_SYNC_REG9 BIT(ADF41513_REG9) +#define ADF41513_SYNC_REG11 BIT(ADF41513_REG11) +#define ADF41513_SYNC_REG12 BIT(ADF41513_REG12) +#define ADF41513_SYNC_REG13 BIT(ADF41513_REG13) +#define ADF41513_SYNC_DIFF 0 +#define ADF41513_SYNC_ALL GENMASK(ADF41513_REG13, ADF41513_REG0) + +/* REG0 Bit Definitions */ +#define ADF41513_REG0_CTRL_BITS_MSK GENMASK(3, 0) +#define ADF41513_REG0_INT_MSK GENMASK(19, 4) +#define ADF41513_REG0_VAR_MOD_MSK BIT(28) + +/* REG1 Bit Definitions */ +#define ADF41513_REG1_FRAC1_MSK GENMASK(28, 4) +#define ADF41513_REG1_DITHER2_MSK BIT(31) + +/* REG2 Bit Definitions */ +#define ADF41513_REG2_PHASE_VAL_MSK GENMASK(15, 4) +#define ADF41513_REG2_PHASE_ADJ_MSK BIT(31) + +/* REG3 Bit Definitions */ +#define ADF41513_REG3_FRAC2_MSK GENMASK(27, 4) + +/* REG4 Bit Definitions */ +#define ADF41513_REG4_MOD2_MSK GENMASK(27, 4) + +/* REG5 Bit Definitions */ +#define ADF41513_REG5_CLK1_DIV_MSK GENMASK(15, 4) +#define ADF41513_REG5_R_CNT_MSK GENMASK(20, 16) +#define ADF41513_REG5_REF_DOUBLER_MSK BIT(21) +#define ADF41513_REG5_RDIV2_MSK BIT(22) +#define ADF41513_REG5_PRESCALER_MSK BIT(23) +#define ADF41513_REG5_LSB_P1_MSK BIT(24) +#define ADF41513_REG5_CP_CURRENT_MSK GENMASK(28, 25) +#define ADF41513_REG5_DLD_MODES_MSK GENMASK(31, 30) + +/* REG6 Bit Definitions */ +#define ADF41513_REG6_COUNTER_RESET_MSK BIT(4) +#define ADF41513_REG6_CP_TRISTATE_MSK BIT(5) +#define ADF41513_REG6_POWER_DOWN_MSK BIT(6) +#define ADF41513_REG6_PD_POLARITY_MSK BIT(7) +#define ADF41513_REG6_LDP_MSK GENMASK(9, 8) +#define ADF41513_REG6_CP_TRISTATE_PD_ON_MSK BIT(16) +#define ADF41513_REG6_SD_RESET_MSK BIT(17) +#define ADF41513_REG6_LOL_ENABLE_MSK BIT(18) +#define ADF41513_REG6_ABP_MSK BIT(19) +#define ADF41513_REG6_INT_MODE_MSK BIT(20) +#define ADF41513_REG6_BLEED_ENABLE_MSK BIT(22) +#define ADF41513_REG6_BLEED_POLARITY_MSK BIT(23) +#define ADF41513_REG6_BLEED_CURRENT_MSK GENMASK(31, 24) + +/* REG7 Bit Definitions */ +#define ADF41513_REG7_CLK2_DIV_MSK GENMASK(17, 6) +#define ADF41513_REG7_CLK_DIV_MODE_MSK GENMASK(19, 18) +#define ADF41513_REG7_PS_BIAS_MSK GENMASK(21, 20) +#define ADF41513_REG7_N_DELAY_MSK GENMASK(23, 22) +#define ADF41513_REG7_LD_CLK_SEL_MSK BIT(26) +#define ADF41513_REG7_LD_COUNT_MSK GENMASK(29, 27) + +/* REG9 Bit Definitions */ +#define ADF41513_REG9_LD_BIAS_MSK GENMASK(31, 30) + +/* REG11 Bit Definitions */ +#define ADF41513_REG11_POWER_DOWN_SEL_MSK BIT(31) + +/* REG12 Bit Definitions */ +#define ADF41513_REG12_READBACK_SEL_MSK GENMASK(19, 14) +#define ADF41513_REG12_LE_SELECT_MSK BIT(20) +#define ADF41513_REG12_MASTER_RESET_MSK BIT(22) +#define ADF41513_REG12_LOGIC_LEVEL_MSK BIT(27) +#define ADF41513_REG12_MUXOUT_MSK GENMASK(31, 28) + +/* MUXOUT Selection */ +#define ADF41513_MUXOUT_TRISTATE 0x0 +#define ADF41513_MUXOUT_DVDD 0x1 +#define ADF41513_MUXOUT_DGND 0x2 +#define ADF41513_MUXOUT_R_DIV 0x3 +#define ADF41513_MUXOUT_N_DIV 0x4 +#define ADF41513_MUXOUT_DIG_LD 0x6 +#define ADF41513_MUXOUT_SDO 0x7 +#define ADF41513_MUXOUT_READBACK 0x8 +#define ADF41513_MUXOUT_CLK1_DIV 0xA +#define ADF41513_MUXOUT_R_DIV2 0xD +#define ADF41513_MUXOUT_N_DIV2 0xE + +/* DLD Mode Selection */ +#define ADF41513_DLD_TRISTATE 0x0 +#define ADF41513_DLD_DIG_LD 0x1 +#define ADF41513_DLD_LOW 0x2 +#define ADF41513_DLD_HIGH 0x3 + +/* Prescaler Selection */ +#define ADF41513_PRESCALER_4_5 0 +#define ADF41513_PRESCALER_8_9 1 +#define ADF41513_PRESCALER_AUTO 2 + +/* Specifications */ +#define ADF41510_MAX_RF_FREQ_HZ (10ULL * HZ_PER_GHZ) +#define ADF41513_MIN_RF_FREQ_HZ (1ULL * HZ_PER_GHZ) +#define ADF41513_MAX_RF_FREQ_HZ (26500ULL * HZ_PER_MHZ) + +#define ADF41513_MIN_REF_FREQ_HZ (10 * HZ_PER_MHZ) +#define ADF41513_MAX_REF_FREQ_HZ (800 * HZ_PER_MHZ) +#define ADF41513_MAX_REF_FREQ_DOUBLER_HZ (225 * HZ_PER_MHZ) + +#define ADF41513_MAX_PFD_FREQ_INT_N_UHZ (250ULL * MEGA * MICROHZ_PER_HZ) +#define ADF41513_MAX_PFD_FREQ_FRAC_N_UHZ (125ULL * MEGA * MICROHZ_PER_HZ) +#define ADF41513_MAX_FREQ_RESOLUTION_UHZ (100ULL * KILO * MICROHZ_PER_HZ) + +#define ADF41513_MIN_INT_4_5 20 +#define ADF41513_MAX_INT_4_5 511 +#define ADF41513_MIN_INT_8_9 64 +#define ADF41513_MAX_INT_8_9 1023 + +#define ADF41513_MIN_INT_FRAC_4_5 23 +#define ADF41513_MIN_INT_FRAC_8_9 75 + +#define ADF41513_MIN_R_CNT 1 +#define ADF41513_MAX_R_CNT 32 + +#define ADF41513_MIN_R_SET 1800 +#define ADF41513_DEFAULT_R_SET 2700 +#define ADF41513_MAX_R_SET 10000 + +#define ADF41513_MIN_CP_VOLTAGE_mV 810 +#define ADF41513_DEFAULT_CP_VOLTAGE_mV 6480 +#define ADF41513_MAX_CP_VOLTAGE_mV 12960 + +#define ADF41513_MIN_CP_CURRENT_uA 81 +#define ADF41513_MAX_CP_CURRENT_uA 7200 + +#define ADF41513_LD_COUNT_FAST_MIN 2 +#define ADF41513_LD_COUNT_FAST_LIMIT 64 +#define ADF41513_LD_COUNT_MIN 64 +#define ADF41513_LD_COUNT_MAX 8192 + +#define ADF41513_FIXED_MODULUS BIT(25) +#define ADF41513_MAX_MOD2 (BIT(24) - 1) +#define ADF41513_MAX_PHASE_VAL (BIT(12) - 1) +#define ADF41513_MAX_CLK_DIVIDER (BIT(12) - 1) + +#define ADF41513_HZ_DECIMAL_SCALE 6 +#define ADF41513_PS_BIAS_INIT 0x2 +#define ADF41513_MAX_PHASE_MICRORAD ((2 * 314159265UL) / 100) + +enum adf41513_pll_mode { + ADF41513_MODE_INVALID, + ADF41513_MODE_INTEGER_N, + ADF41513_MODE_FIXED_MODULUS, + ADF41513_MODE_VARIABLE_MODULUS, +}; + +struct adf41513_chip_info { + const char *name; + u64 max_rf_freq_hz; + bool has_prescaler_8_9; +}; + +struct adf41513_data { + u64 power_up_frequency_hz; + u64 freq_resolution_uhz; + u32 charge_pump_voltage_mv; + u32 lock_detect_count; + + u8 ref_div_factor; + bool ref_doubler_en; + bool ref_div2_en; + bool phase_detector_polarity; + + bool logic_lvl_1v8_en; +}; + +struct adf41513_pll_settings { + enum adf41513_pll_mode mode; + + /* reference path parameters */ + u8 r_counter; + u8 ref_doubler; + u8 ref_div2; + u8 prescaler; + + /* frequency parameters */ + u64 target_frequency_uhz; + u64 actual_frequency_uhz; + u64 pfd_frequency_uhz; + + /* pll parameters */ + u32 frac1; + u32 frac2; + u32 mod2; + u16 int_val; +}; + +struct adf41513_state { + const struct adf41513_chip_info *chip_info; + struct spi_device *spi; + struct gpio_desc *lock_detect; + struct clk *ref_clk; + u32 ref_freq_hz; + + /* + * Lock for accessing device registers. Some operations require + * multiple consecutive R/W operations, during which the device + * shouldn't be interrupted. The buffers are also shared across + * all operations so need to be protected on stand alone reads and + * writes. + */ + struct mutex lock; + + /* Cached register values */ + u32 regs[ADF41513_REG_NUM]; + u32 regs_hw[ADF41513_REG_NUM]; + + struct adf41513_data data; + struct adf41513_pll_settings settings; + + bool powerdown; +}; + +static const char * const adf41513_power_supplies[] =3D { + "avdd1", "avdd2", "avdd3", "avdd4", "avdd5", "vp", +}; + +static int adf41513_sync_config(struct adf41513_state *st, u16 sync_mask) +{ + __be32 d32; + int ret; + + /* write registers in reverse order (R13 to R0)*/ + for (int i =3D ADF41513_REG13; i >=3D ADF41513_REG0; i--) { + if (st->regs_hw[i] =3D=3D st->regs[i] && !(sync_mask & BIT(i))) + continue; + + d32 =3D cpu_to_be32(st->regs[i] | i); + ret =3D spi_write_then_read(st->spi, &d32, sizeof(d32), NULL, 0); + if (ret < 0) + return ret; + st->regs_hw[i] =3D st->regs[i]; + dev_dbg(&st->spi->dev, "REG%d <=3D 0x%08X\n", i, st->regs[i] | i); + } + + return 0; +} + +static u64 adf41513_pll_get_rate(struct adf41513_state *st) +{ + struct adf41513_pll_settings *cfg =3D &st->settings; + + if (cfg->mode !=3D ADF41513_MODE_INVALID) + return cfg->actual_frequency_uhz; + + /* get pll settings from regs_hw */ + cfg->int_val =3D FIELD_GET(ADF41513_REG0_INT_MSK, st->regs_hw[ADF41513_RE= G0]); + cfg->frac1 =3D FIELD_GET(ADF41513_REG1_FRAC1_MSK, st->regs_hw[ADF41513_RE= G1]); + cfg->frac2 =3D FIELD_GET(ADF41513_REG3_FRAC2_MSK, st->regs_hw[ADF41513_RE= G3]); + cfg->mod2 =3D FIELD_GET(ADF41513_REG4_MOD2_MSK, st->regs_hw[ADF41513_REG4= ]); + cfg->r_counter =3D FIELD_GET(ADF41513_REG5_R_CNT_MSK, st->regs_hw[ADF4151= 3_REG5]); + cfg->ref_doubler =3D FIELD_GET(ADF41513_REG5_REF_DOUBLER_MSK, st->regs_hw= [ADF41513_REG5]); + cfg->ref_div2 =3D FIELD_GET(ADF41513_REG5_RDIV2_MSK, st->regs_hw[ADF41513= _REG5]); + cfg->prescaler =3D FIELD_GET(ADF41513_REG5_PRESCALER_MSK, st->regs_hw[ADF= 41513_REG5]); + + if (!cfg->mod2) + cfg->mod2 =3D 1; + if (!cfg->r_counter) + cfg->r_counter =3D ADF41513_MAX_R_CNT; + + /* calculate pfd frequency */ + cfg->pfd_frequency_uhz =3D (u64)st->ref_freq_hz * MICRO; + if (cfg->ref_doubler) + cfg->pfd_frequency_uhz <<=3D 1; + if (cfg->ref_div2) + cfg->pfd_frequency_uhz >>=3D 1; + cfg->pfd_frequency_uhz =3D div_u64(cfg->pfd_frequency_uhz, cfg->r_counter= ); + cfg->actual_frequency_uhz =3D (u64)cfg->int_val * cfg->pfd_frequency_uhz; + + /* check if int mode is selected */ + if (FIELD_GET(ADF41513_REG6_INT_MODE_MSK, st->regs_hw[ADF41513_REG6])) { + cfg->mode =3D ADF41513_MODE_INTEGER_N; + } else { + cfg->actual_frequency_uhz +=3D mul_u64_u32_div(cfg->pfd_frequency_uhz, + cfg->frac1, + ADF41513_FIXED_MODULUS); + + /* check if variable modulus is selected */ + if (FIELD_GET(ADF41513_REG0_VAR_MOD_MSK, st->regs_hw[ADF41513_REG0])) { + cfg->actual_frequency_uhz +=3D + mul_u64_u64_div_u64(cfg->frac2, + cfg->pfd_frequency_uhz, + (u64)cfg->mod2 * ADF41513_FIXED_MODULUS); + + cfg->mode =3D ADF41513_MODE_VARIABLE_MODULUS; + } else { + /* LSB_P1 offset */ + if (!FIELD_GET(ADF41513_REG5_LSB_P1_MSK, st->regs_hw[ADF41513_REG5])) + cfg->actual_frequency_uhz +=3D + div_u64(cfg->pfd_frequency_uhz, + 2 * ADF41513_FIXED_MODULUS); + cfg->mode =3D ADF41513_MODE_FIXED_MODULUS; + } + } + + cfg->target_frequency_uhz =3D cfg->actual_frequency_uhz; + + return cfg->actual_frequency_uhz; +} + +static int adf41513_calc_pfd_frequency(struct adf41513_state *st, + struct adf41513_pll_settings *result, + u64 fpfd_limit_uhz) +{ + result->ref_div2 =3D st->data.ref_div2_en; + result->ref_doubler =3D st->data.ref_doubler_en; + result->r_counter =3D st->data.ref_div_factor - 1; + + do { + result->r_counter++; + /* f_PFD =3D REF_IN =C3=97 ((1 + D)/(R =C3=97 (1 + T))) */ + result->pfd_frequency_uhz =3D (u64)st->ref_freq_hz * MICRO; + if (result->ref_doubler) + result->pfd_frequency_uhz <<=3D 1; + if (result->ref_div2) + result->pfd_frequency_uhz >>=3D 1; + result->pfd_frequency_uhz =3D div_u64(result->pfd_frequency_uhz, + result->r_counter); + } while (result->pfd_frequency_uhz > fpfd_limit_uhz); + + if (result->r_counter > ADF41513_MAX_R_CNT) { + dev_err(&st->spi->dev, "Cannot optimize PFD frequency\n"); + return -ERANGE; + } + + return 0; +} + +static int adf41513_calc_integer_n(struct adf41513_state *st, + struct adf41513_pll_settings *result) +{ + u32 max_int =3D st->chip_info->has_prescaler_8_9 ? + ADF41513_MAX_INT_8_9 : ADF41513_MAX_INT_4_5; + u64 freq_error_uhz; + u32 int_val =3D div64_u64_rem(result->target_frequency_uhz, result->pfd_f= requency_uhz, + &freq_error_uhz); + + /* check if freq error is within a tolerance of 1/2 resolution */ + if (freq_error_uhz > (result->pfd_frequency_uhz >> 1) && int_val < max_in= t) { + int_val++; + freq_error_uhz =3D result->pfd_frequency_uhz - freq_error_uhz; + } + + if (freq_error_uhz > st->data.freq_resolution_uhz) + return -ERANGE; + + /* set prescaler */ + if (st->chip_info->has_prescaler_8_9 && int_val >=3D ADF41513_MIN_INT_8_9= && + int_val <=3D ADF41513_MAX_INT_8_9) + result->prescaler =3D 1; + else if (int_val >=3D ADF41513_MIN_INT_4_5 && int_val <=3D ADF41513_MAX_I= NT_4_5) + result->prescaler =3D 0; + else + return -ERANGE; + + result->actual_frequency_uhz =3D (u64)int_val * result->pfd_frequency_uhz; + result->mode =3D ADF41513_MODE_INTEGER_N; + result->int_val =3D int_val; + result->frac1 =3D 0; + result->frac2 =3D 0; + result->mod2 =3D 0; + + return 0; +} + +static int adf41513_calc_fixed_mod(struct adf41513_state *st, + struct adf41513_pll_settings *result) +{ + u64 resolution_uhz =3D div_u64(result->pfd_frequency_uhz, ADF41513_FIXED_= MODULUS); + u64 target_frequency_uhz =3D result->target_frequency_uhz; + u64 freq_error_uhz; + u32 int_val, frac1; + bool lsb_p1_offset =3D !FIELD_GET(ADF41513_REG5_LSB_P1_MSK, st->regs[ADF4= 1513_REG5]); + + /* LSB_P1 adds a frequency offset of f_pfd/2^26 */ + if (lsb_p1_offset) + target_frequency_uhz -=3D resolution_uhz >> 1; + + int_val =3D div64_u64_rem(target_frequency_uhz, result->pfd_frequency_uhz, + &freq_error_uhz); + + if (st->chip_info->has_prescaler_8_9 && int_val >=3D ADF41513_MIN_INT_FRA= C_8_9 && + int_val <=3D ADF41513_MAX_INT_8_9) + result->prescaler =3D 1; + else if (int_val >=3D ADF41513_MIN_INT_FRAC_4_5 && int_val <=3D ADF41513_= MAX_INT_4_5) + result->prescaler =3D 0; + else + return -ERANGE; + + /* compute frac1 and fixed modulus error */ + frac1 =3D mul_u64_u64_div_u64(freq_error_uhz, ADF41513_FIXED_MODULUS, + result->pfd_frequency_uhz); + freq_error_uhz -=3D mul_u64_u32_div(result->pfd_frequency_uhz, frac1, + ADF41513_FIXED_MODULUS); + + /* check if freq error is within a tolerance of 1/2 resolution */ + if (freq_error_uhz > (resolution_uhz >> 1) && frac1 < (ADF41513_FIXED_MOD= ULUS - 1)) { + frac1++; + freq_error_uhz =3D freq_error_uhz < resolution_uhz ? + resolution_uhz - freq_error_uhz : 0; + } + + if (freq_error_uhz > st->data.freq_resolution_uhz) + return -ERANGE; + + /* integer part */ + result->actual_frequency_uhz =3D (u64)int_val * result->pfd_frequency_uhz; + /* fractional part */ + if (lsb_p1_offset) + result->actual_frequency_uhz +=3D (resolution_uhz >> 1); + result->actual_frequency_uhz +=3D mul_u64_u32_div(result->pfd_frequency_u= hz, frac1, + ADF41513_FIXED_MODULUS); + result->mode =3D ADF41513_MODE_FIXED_MODULUS; + result->int_val =3D int_val; + result->frac1 =3D frac1; + result->frac2 =3D 0; + result->mod2 =3D 0; + + return 0; +} + +static int adf41513_calc_variable_mod(struct adf41513_state *st, + struct adf41513_pll_settings *result) +{ + u64 freq_error_uhz, mod2; + u32 frac1, frac2; + u32 int_val =3D div64_u64_rem(result->target_frequency_uhz, + result->pfd_frequency_uhz, &freq_error_uhz); + + if (st->chip_info->has_prescaler_8_9 && int_val >=3D ADF41513_MIN_INT_FRA= C_8_9 && + int_val <=3D ADF41513_MAX_INT_8_9) + result->prescaler =3D 1; + else if (int_val >=3D ADF41513_MIN_INT_FRAC_4_5 && int_val <=3D ADF41513_= MAX_INT_4_5) + result->prescaler =3D 0; + else + return -ERANGE; + + /* calculate required mod2 based on target resolution / 2 */ + mod2 =3D DIV64_U64_ROUND_CLOSEST(result->pfd_frequency_uhz << 1, + st->data.freq_resolution_uhz * ADF41513_FIXED_MODULUS); + /* ensure mod2 is at least 2 for meaningful operation */ + mod2 =3D clamp(mod2, 2, ADF41513_MAX_MOD2); + + /* calculate frac1 and frac2 */ + frac1 =3D mul_u64_u64_div_u64(freq_error_uhz, ADF41513_FIXED_MODULUS, + result->pfd_frequency_uhz); + frac2 =3D mul_u64_u64_div_u64(freq_error_uhz, mod2 * ADF41513_FIXED_MODUL= US, + result->pfd_frequency_uhz) - mod2 * frac1; + + /* integer part */ + result->actual_frequency_uhz =3D (u64)int_val * result->pfd_frequency_uhz; + /* fractional part */ + result->actual_frequency_uhz +=3D mul_u64_u64_div_u64(mod2 * frac1 + frac= 2, + result->pfd_frequency_uhz, + mod2 * ADF41513_FIXED_MODULUS); + result->mode =3D ADF41513_MODE_VARIABLE_MODULUS; + result->int_val =3D int_val; + result->frac1 =3D frac1; + result->frac2 =3D frac2; + result->mod2 =3D mod2; + + return 0; +} + +static int adf41513_calc_pll_settings(struct adf41513_state *st, + struct adf41513_pll_settings *result, + u64 rf_out_uhz) +{ + u64 max_rf_freq_uhz =3D st->chip_info->max_rf_freq_hz * MICRO; + u64 min_rf_freq_uhz =3D ADF41513_MIN_RF_FREQ_HZ * MICRO; + u64 pfd_freq_limit_uhz; + int ret; + + if (rf_out_uhz < min_rf_freq_uhz || rf_out_uhz > max_rf_freq_uhz) { + dev_err(&st->spi->dev, "RF frequency %llu uHz out of range [%llu, %llu] = uHz\n", + rf_out_uhz, min_rf_freq_uhz, max_rf_freq_uhz); + return -EINVAL; + } + + result->target_frequency_uhz =3D rf_out_uhz; + + /* try integer-N first (best phase noise performance) */ + pfd_freq_limit_uhz =3D min(div_u64(rf_out_uhz, ADF41513_MIN_INT_4_5), + ADF41513_MAX_PFD_FREQ_INT_N_UHZ); + ret =3D adf41513_calc_pfd_frequency(st, result, pfd_freq_limit_uhz); + if (ret) + return ret; + + if (adf41513_calc_integer_n(st, result) =3D=3D 0) + return 0; + + /* try fractional-N: recompute pfd frequency if necessary */ + pfd_freq_limit_uhz =3D min(div_u64(rf_out_uhz, ADF41513_MIN_INT_FRAC_4_5), + ADF41513_MAX_PFD_FREQ_FRAC_N_UHZ); + if (pfd_freq_limit_uhz < result->pfd_frequency_uhz) { + ret =3D adf41513_calc_pfd_frequency(st, result, pfd_freq_limit_uhz); + if (ret) + return ret; + } + + /* fixed-modulus attempt */ + if (adf41513_calc_fixed_mod(st, result) =3D=3D 0) + return 0; + + /* variable-modulus attempt */ + ret =3D adf41513_calc_variable_mod(st, result); + if (ret) { + dev_err(&st->spi->dev, + "no valid PLL configuration found for %llu uHz\n", + rf_out_uhz); + return ret; + } + + return 0; +} + +static int adf41513_set_frequency(struct adf41513_state *st, u64 freq_uhz,= u16 sync_mask) +{ + struct adf41513_pll_settings result; + int ret; + + ret =3D adf41513_calc_pll_settings(st, &result, freq_uhz); + if (ret < 0) + return ret; + + /* apply computed results to pll settings */ + st->settings =3D result; + + dev_dbg(&st->spi->dev, + "%s mode: int=3D%u, frac1=3D%u, frac2=3D%u, mod2=3D%u, fpdf=3D%llu Hz, p= rescaler=3D%s\n", + (result.mode =3D=3D ADF41513_MODE_INTEGER_N) ? "integer-n" : + (result.mode =3D=3D ADF41513_MODE_FIXED_MODULUS) ? "fixed-modulus" : "va= riable-modulus", + result.int_val, result.frac1, result.frac2, result.mod2, + div64_u64(result.pfd_frequency_uhz, MICRO), + result.prescaler ? "8/9" : "4/5"); + + st->regs[ADF41513_REG0] =3D FIELD_PREP(ADF41513_REG0_INT_MSK, + st->settings.int_val); + if (st->settings.mode =3D=3D ADF41513_MODE_VARIABLE_MODULUS) + st->regs[ADF41513_REG0] |=3D ADF41513_REG0_VAR_MOD_MSK; + + st->regs[ADF41513_REG1] =3D FIELD_PREP(ADF41513_REG1_FRAC1_MSK, + st->settings.frac1); + if (st->settings.mode !=3D ADF41513_MODE_INTEGER_N) + st->regs[ADF41513_REG1] |=3D ADF41513_REG1_DITHER2_MSK; + + st->regs[ADF41513_REG3] =3D FIELD_PREP(ADF41513_REG3_FRAC2_MSK, + st->settings.frac2); + FIELD_MODIFY(ADF41513_REG4_MOD2_MSK, &st->regs[ADF41513_REG4], + st->settings.mod2); + FIELD_MODIFY(ADF41513_REG5_R_CNT_MSK, &st->regs[ADF41513_REG5], + st->settings.r_counter % ADF41513_MAX_R_CNT); + FIELD_MODIFY(ADF41513_REG5_REF_DOUBLER_MSK, &st->regs[ADF41513_REG5], + st->settings.ref_doubler); + FIELD_MODIFY(ADF41513_REG5_RDIV2_MSK, &st->regs[ADF41513_REG5], + st->settings.ref_div2); + FIELD_MODIFY(ADF41513_REG5_PRESCALER_MSK, &st->regs[ADF41513_REG5], + st->settings.prescaler); + + if (st->settings.mode =3D=3D ADF41513_MODE_INTEGER_N) { + st->regs[ADF41513_REG6] |=3D ADF41513_REG6_INT_MODE_MSK; + st->regs[ADF41513_REG6] &=3D ~ADF41513_REG6_BLEED_ENABLE_MSK; + } else { + st->regs[ADF41513_REG6] &=3D ~ADF41513_REG6_INT_MODE_MSK; + st->regs[ADF41513_REG6] |=3D ADF41513_REG6_BLEED_ENABLE_MSK; + } + + return adf41513_sync_config(st, sync_mask | ADF41513_SYNC_REG0); +} + +static int adf41513_suspend(struct adf41513_state *st) +{ + st->regs[ADF41513_REG6] |=3D FIELD_PREP(ADF41513_REG6_POWER_DOWN_MSK, 1); + return adf41513_sync_config(st, ADF41513_SYNC_DIFF); +} + +static int adf41513_resume(struct adf41513_state *st) +{ + st->regs[ADF41513_REG6] &=3D ~ADF41513_REG6_POWER_DOWN_MSK; + return adf41513_sync_config(st, ADF41513_SYNC_ALL); +} + +static ssize_t adf41513_read_resolution(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + int vals[2]; + + guard(mutex)(&st->lock); + + iio_val_s64_to_s32s(st->data.freq_resolution_uhz, vals); + return iio_format_value(buf, IIO_VAL_DECIMAL64_MICRO, ARRAY_SIZE(vals), v= als); +} + +static ssize_t adf41513_read_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u32 val; + + guard(mutex)(&st->lock); + + val =3D FIELD_GET(ADF41513_REG6_POWER_DOWN_MSK, st->regs_hw[ADF41513_REG6= ]); + return sysfs_emit(buf, "%u\n", val); +} + +static ssize_t adf41513_write_resolution(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u64 freq_uhz; + int ret; + + ret =3D kstrtoudec64(buf, ADF41513_HZ_DECIMAL_SCALE, &freq_uhz); + if (ret) + return ret; + + if (freq_uhz =3D=3D 0 || freq_uhz > ADF41513_MAX_FREQ_RESOLUTION_UHZ) + return -EINVAL; + + guard(mutex)(&st->lock); + + st->data.freq_resolution_uhz =3D freq_uhz; + return len; +} + +static ssize_t adf41513_write_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + bool val; + int ret; + + ret =3D kstrtobool(buf, &val); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + if (val) + ret =3D adf41513_suspend(st); + else + ret =3D adf41513_resume(st); + if (ret) + return ret; + + st->powerdown =3D val; + return len; +} + +static const struct iio_chan_spec_ext_info adf41513_ext_info[] =3D { + { + .name =3D "frequency_resolution", + .read =3D adf41513_read_resolution, + .write =3D adf41513_write_resolution, + .shared =3D IIO_SEPARATE, + }, + { + .name =3D "powerdown", + .read =3D adf41513_read_powerdown, + .write =3D adf41513_write_powerdown, + .shared =3D IIO_SEPARATE, + }, + { } +}; + +static const struct iio_chan_spec adf41513_chan =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D 0, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_FREQUENCY) | + BIT(IIO_CHAN_INFO_PHASE), + .ext_info =3D adf41513_ext_info, +}; + +static int adf41513_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u64 tmp64; + + guard(mutex)(&st->lock); + + switch (info) { + case IIO_CHAN_INFO_FREQUENCY: + if (st->lock_detect && + !gpiod_get_value_cansleep(st->lock_detect)) { + dev_dbg(&st->spi->dev, "PLL un-locked\n"); + return -EBUSY; + } + tmp64 =3D adf41513_pll_get_rate(st); + iio_val_s64_decompose(tmp64, val, val2); + return IIO_VAL_DECIMAL64_MICRO; + case IIO_CHAN_INFO_PHASE: + tmp64 =3D FIELD_GET(ADF41513_REG2_PHASE_VAL_MSK, + st->regs_hw[ADF41513_REG2]); + tmp64 =3D (tmp64 * ADF41513_MAX_PHASE_MICRORAD) >> 12; + iio_val_s64_decompose(tmp64, val, val2); + return IIO_VAL_DECIMAL64_MICRO; + default: + return -EINVAL; + } +} + +static int adf41513_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u64 tmp64 =3D iio_val_s64_compose(val, val2); + u16 phase_val; + int ret; + + guard(mutex)(&st->lock); + + switch (info) { + case IIO_CHAN_INFO_FREQUENCY: + return adf41513_set_frequency(st, tmp64, ADF41513_SYNC_DIFF); + case IIO_CHAN_INFO_PHASE: + if (tmp64 >=3D ADF41513_MAX_PHASE_MICRORAD) + return -EINVAL; + + phase_val =3D DIV_U64_ROUND_CLOSEST(tmp64 << 12, + ADF41513_MAX_PHASE_MICRORAD); + phase_val =3D min(phase_val, ADF41513_MAX_PHASE_VAL); + st->regs[ADF41513_REG2] |=3D ADF41513_REG2_PHASE_ADJ_MSK; + FIELD_MODIFY(ADF41513_REG2_PHASE_VAL_MSK, + &st->regs[ADF41513_REG2], phase_val); + ret =3D adf41513_sync_config(st, ADF41513_SYNC_REG0); + /* clear phase adjust for the next sync */ + st->regs[ADF41513_REG2] &=3D ~ADF41513_REG2_PHASE_ADJ_MSK; + return ret; + default: + return -EINVAL; + } +} + +static int adf41513_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_FREQUENCY: + case IIO_CHAN_INFO_PHASE: + return IIO_VAL_DECIMAL64_MICRO; + default: + return -EINVAL; + } +} + +static int adf41513_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + + if (reg > ADF41513_REG13) + return -EINVAL; + + guard(mutex)(&st->lock); + + if (!readval) { + if (reg <=3D ADF41513_REG6) + st->settings.mode =3D ADF41513_MODE_INVALID; + st->regs[reg] =3D writeval & ~0xF; /* Clear control bits */ + return adf41513_sync_config(st, BIT(reg)); + } + + *readval =3D st->regs_hw[reg]; + return 0; +} + +static const struct iio_info adf41513_info =3D { + .read_raw =3D adf41513_read_raw, + .write_raw =3D adf41513_write_raw, + .write_raw_get_fmt =3D adf41513_write_raw_get_fmt, + .debugfs_reg_access =3D &adf41513_reg_access, +}; + +static int adf41513_parse_fw(struct adf41513_state *st) +{ + struct device *dev =3D &st->spi->dev; + u32 tmp, cp_resistance, cp_current; + int ret; + + tmp =3D ADF41510_MAX_RF_FREQ_HZ / MEGA; + device_property_read_u32(dev, "adi,power-up-frequency-mhz", &tmp); + st->data.power_up_frequency_hz =3D (u64)tmp * MEGA; + if (st->data.power_up_frequency_hz < ADF41513_MIN_RF_FREQ_HZ || + st->data.power_up_frequency_hz > st->chip_info->max_rf_freq_hz) + return dev_err_probe(dev, -ERANGE, + "power-up frequency %llu Hz out of range\n", + st->data.power_up_frequency_hz); + + tmp =3D ADF41513_MIN_R_CNT; + device_property_read_u32(dev, "adi,reference-div-factor", &tmp); + if (tmp < ADF41513_MIN_R_CNT || tmp > ADF41513_MAX_R_CNT) + return dev_err_probe(dev, -ERANGE, + "invalid reference div factor %u\n", tmp); + st->data.ref_div_factor =3D tmp; + + st->data.ref_div2_en =3D device_property_read_bool(dev, "adi,reference-di= v2-enable"); + st->data.ref_doubler_en =3D device_property_read_bool(dev, "adi,reference= -doubler-enable"); + + if (st->data.ref_doubler_en && + st->ref_freq_hz > ADF41513_MAX_REF_FREQ_DOUBLER_HZ) { + return dev_err_probe(dev, -ERANGE, + "Ref frequency not supported with doubler enabled\n"); + } + + cp_resistance =3D ADF41513_DEFAULT_R_SET; + device_property_read_u32(dev, "adi,charge-pump-resistor-ohms", &cp_resist= ance); + if (cp_resistance < ADF41513_MIN_R_SET || cp_resistance > ADF41513_MAX_R_= SET) + return dev_err_probe(dev, -ERANGE, "R_SET %u Ohms out of range\n", cp_re= sistance); + + st->data.charge_pump_voltage_mv =3D ADF41513_DEFAULT_CP_VOLTAGE_mV; + ret =3D device_property_read_u32(dev, "adi,charge-pump-current-microamp",= &cp_current); + if (!ret) { + if (cp_current < ADF41513_MIN_CP_CURRENT_uA || + cp_current > ADF41513_MAX_CP_CURRENT_uA) + return dev_err_probe(dev, -ERANGE, + "I_CP %u uA out of range\n", cp_current); + + tmp =3D DIV_ROUND_CLOSEST(cp_current * cp_resistance, MILLI); + if (tmp < ADF41513_MIN_CP_VOLTAGE_mV || tmp > ADF41513_MAX_CP_VOLTAGE_mV) + return dev_err_probe(dev, -ERANGE, "I_CP %u uA (%u Ohms) out of range\n= ", + cp_current, cp_resistance); + st->data.charge_pump_voltage_mv =3D tmp; + } + + st->data.phase_detector_polarity =3D + device_property_read_bool(dev, "adi,phase-detector-polarity-positive-ena= ble"); + + st->data.logic_lvl_1v8_en =3D device_property_read_bool(dev, "adi,logic-l= evel-1v8-enable"); + + tmp =3D ADF41513_LD_COUNT_MIN; + device_property_read_u32(dev, "adi,lock-detector-count", &tmp); + if (tmp < ADF41513_LD_COUNT_FAST_MIN || tmp > ADF41513_LD_COUNT_MAX || + !is_power_of_2(tmp)) + return dev_err_probe(dev, -ERANGE, + "invalid lock detect count: %u\n", tmp); + st->data.lock_detect_count =3D tmp; + + st->data.freq_resolution_uhz =3D MICROHZ_PER_HZ; + + return 0; +} + +static void adf41513_chip_disable(void *data) +{ + gpiod_set_value_cansleep(data, 0); +} + +static void adf41513_close(void *data) +{ + adf41513_suspend(data); +} + +static int adf41513_setup(struct device *dev, struct adf41513_state *st) +{ + u32 tmp; + int ret; + + memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); + + /* assuming DLD pin is used for lock detection */ + st->regs[ADF41513_REG5] =3D FIELD_PREP(ADF41513_REG5_DLD_MODES_MSK, + ADF41513_DLD_DIG_LD); + + tmp =3D DIV_ROUND_CLOSEST(st->data.charge_pump_voltage_mv, ADF41513_MIN_C= P_VOLTAGE_mV); + st->regs[ADF41513_REG5] |=3D FIELD_PREP(ADF41513_REG5_CP_CURRENT_MSK, tmp= - 1); + + st->regs[ADF41513_REG6] =3D ADF41513_REG6_ABP_MSK | + ADF41513_REG6_LOL_ENABLE_MSK | + ADF41513_REG6_SD_RESET_MSK; + if (st->data.phase_detector_polarity) + st->regs[ADF41513_REG6] |=3D ADF41513_REG6_PD_POLARITY_MSK; + + st->regs[ADF41513_REG7] =3D FIELD_PREP(ADF41513_REG7_PS_BIAS_MSK, + ADF41513_PS_BIAS_INIT); + tmp =3D ilog2(st->data.lock_detect_count); + if (st->data.lock_detect_count < ADF41513_LD_COUNT_FAST_LIMIT) { + tmp -=3D const_ilog2(ADF41513_LD_COUNT_FAST_MIN); + st->regs[ADF41513_REG7] |=3D ADF41513_REG7_LD_CLK_SEL_MSK; + } else { + tmp -=3D const_ilog2(ADF41513_LD_COUNT_MIN); + } + st->regs[ADF41513_REG7] |=3D FIELD_PREP(ADF41513_REG7_LD_COUNT_MSK, tmp); + + st->regs[ADF41513_REG11] =3D ADF41513_REG11_POWER_DOWN_SEL_MSK; + st->regs[ADF41513_REG12] =3D FIELD_PREP(ADF41513_REG12_LOGIC_LEVEL_MSK, + st->data.logic_lvl_1v8_en ? 0 : 1); + + /* perform initialization sequence with power-up frequency */ + ret =3D adf41513_set_frequency(st, st->data.power_up_frequency_hz * MICRO, + ADF41513_SYNC_ALL); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, adf41513_close, st); +} + +static int adf41513_pm_suspend(struct device *dev) +{ + struct adf41513_state *st =3D dev_get_drvdata(dev); + + guard(mutex)(&st->lock); + return adf41513_suspend(st); +} + +static int adf41513_pm_resume(struct device *dev) +{ + struct adf41513_state *st =3D dev_get_drvdata(dev); + + guard(mutex)(&st->lock); + if (st->powerdown) + return 0; /* nothing to do */ + + return adf41513_resume(st); +} + +static const struct adf41513_chip_info adf41510_chip_info =3D { + .name =3D "adf41510", + .max_rf_freq_hz =3D ADF41510_MAX_RF_FREQ_HZ, + .has_prescaler_8_9 =3D false, +}; + +static const struct adf41513_chip_info adf41513_chip_info =3D { + .name =3D "adf41513", + .max_rf_freq_hz =3D ADF41513_MAX_RF_FREQ_HZ, + .has_prescaler_8_9 =3D true, +}; + +static int adf41513_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct gpio_desc *chip_enable; + struct iio_dev *indio_dev; + struct adf41513_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return -EINVAL; + + spi_set_drvdata(spi, st); + + st->ref_clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(st->ref_clk)) + return PTR_ERR(st->ref_clk); + + st->ref_freq_hz =3D clk_get_rate(st->ref_clk); + if (st->ref_freq_hz < ADF41513_MIN_REF_FREQ_HZ || + st->ref_freq_hz > ADF41513_MAX_REF_FREQ_HZ) + return dev_err_probe(dev, -ERANGE, + "reference frequency %u Hz out of range\n", + st->ref_freq_hz); + + ret =3D adf41513_parse_fw(st); + if (ret) + return ret; + + ret =3D devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(adf41513_power_supplies), + adf41513_power_supplies); + if (ret) + return dev_err_probe(dev, ret, + "failed to get and enable regulators\n"); + + st->lock_detect =3D devm_gpiod_get_optional(dev, "lock-detect", GPIOD_IN); + if (IS_ERR(st->lock_detect)) + return dev_err_probe(dev, PTR_ERR(st->lock_detect), + "fail to request lock detect GPIO\n"); + + chip_enable =3D devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); + if (IS_ERR(chip_enable)) + return dev_err_probe(dev, PTR_ERR(chip_enable), + "fail to request chip enable GPIO\n"); + + ret =3D devm_add_action_or_reset(dev, adf41513_chip_disable, chip_enable); + if (ret) + return dev_err_probe(dev, ret, "Failed to add disable action\n"); + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + indio_dev->name =3D st->chip_info->name; + indio_dev->info =3D &adf41513_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D &adf41513_chan; + indio_dev->num_channels =3D 1; + + ret =3D adf41513_setup(dev, st); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to setup device\n"); + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct spi_device_id adf41513_id[] =3D { + { .name =3D "adf41510", .driver_data =3D (kernel_ulong_t)&adf41510_chip_i= nfo }, + { .name =3D "adf41513", .driver_data =3D (kernel_ulong_t)&adf41513_chip_i= nfo }, + { } +}; +MODULE_DEVICE_TABLE(spi, adf41513_id); + +static const struct of_device_id adf41513_of_match[] =3D { + { .compatible =3D "adi,adf41510", .data =3D &adf41510_chip_info }, + { .compatible =3D "adi,adf41513", .data =3D &adf41513_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, adf41513_of_match); + +static DEFINE_SIMPLE_DEV_PM_OPS(adf41513_pm_ops, adf41513_pm_suspend, adf4= 1513_pm_resume); + +static struct spi_driver adf41513_driver =3D { + .driver =3D { + .name =3D "adf41513", + .pm =3D pm_ptr(&adf41513_pm_ops), + .of_match_table =3D adf41513_of_match, + }, + .probe =3D adf41513_probe, + .id_table =3D adf41513_id, +}; +module_spi_driver(adf41513_driver); + +MODULE_AUTHOR("Rodrigo Alencar "); +MODULE_DESCRIPTION("Analog Devices ADF41513 PLL Frequency Synthesizer"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D0873921C1; Sun, 24 May 2026 10:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; cv=none; b=jmyGrK1mthiXCgPFq1j1/0vanSaazT9jngKzGridaP3tW950W/Yi9GfFG51/2go59EcHu64IPN1qgLsozJkn4Rq8iGFbWqUw+Av/0vpzgokJiZaVC3AZQHcillddMvxOBDBTav5v2CkC2ja3G0Nv99fzfLyhAY7Q+IOqsfRDFQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; c=relaxed/simple; bh=am5M0FfyA32T0RH1j0AQfBPIoRlOufOv8qOkJi+td/E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IjgPfvauoH9yJcBsxsNMJ6jrpXigczkTvWj1YeJSRz1sy3La0ysXZrAedRJC32eb9VOI0M1OtfDVG6e8BqsqJ1Jf5aEY6IYLiH9Tl2nC0A71EpwN76Spyt6a32KPv9RzbkzS1Qe+MCHN0pLUfGImsa4Uw6p4tfj5Z3q/05Q/JtE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tVJJd003; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tVJJd003" Received: by smtp.kernel.org (Postfix) with ESMTPS id E404BC2BCF4; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618940; bh=am5M0FfyA32T0RH1j0AQfBPIoRlOufOv8qOkJi+td/E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tVJJd003jLL4JvU82Ym6vqDEMvomadwMtFPeTQaKM66yYCc8O5vOybj40i9OG4gdo 6WjJnlb7lcly0Sw/0SOBtf/IjHFxXoY6XP4dN0VBncQoSvipyrmsdzYyNKK+HyGQBZ +toKWTXhK4oACYkeS+BWtAUCIbHU4YS9Y8L5N2/Kd+dAP4EeHvnnrR61Qpk8HQBOSg vvzc1w2z0ttYeTIGPsNkoNCCUPtVapuOKmc2YNpsyUWrdQE/sqzBO5/bwPtEbR2GYj ga5Xz/6UVjHfq8DFivcgK+KWLjyjSLrMHMd14HEtFxBMqquveWj02Xwfj30JZW6bRz DE60toEV8NA5A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBB90CD5BC8; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:26 +0100 Subject: [PATCH v14 09/12] iio: frequency: adf41513: handle LE synchronization feature Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-9-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=2690; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=zmkJcNOMxyjybaEg7liQf0jE/fQEjr0YjWYo2BC84cw=; b=/tLPJvOS0ZgwxtTxsdWPvRdvIW3s6teqaVsvKpUjyigqCqd1FNFj7Yq0vENTzLgJRmyPWC2/T tfiokjnVDJ1Duox/EQl3+wrDnMTgDAenPd2k78eHoixS+4nSqzz3UM6 X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar When LE sync is enabled, it must be set after powering up and it must be disabled when powering down. It is recommended when using the PLL as a frequency synthesizer, where reference signal will always be present while the device is being configured. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/adf41513.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/iio/frequency/adf41513.c b/drivers/iio/frequency/adf41= 513.c index 6f952ccc675e..43726b2d4879 100644 --- a/drivers/iio/frequency/adf41513.c +++ b/drivers/iio/frequency/adf41513.c @@ -226,6 +226,7 @@ struct adf41513_data { bool phase_detector_polarity; =20 bool logic_lvl_1v8_en; + bool le_sync_en; }; =20 struct adf41513_pll_settings { @@ -635,13 +636,28 @@ static int adf41513_set_frequency(struct adf41513_sta= te *st, u64 freq_uhz, u16 s static int adf41513_suspend(struct adf41513_state *st) { st->regs[ADF41513_REG6] |=3D FIELD_PREP(ADF41513_REG6_POWER_DOWN_MSK, 1); + st->regs[ADF41513_REG12] &=3D ~ADF41513_REG12_LE_SELECT_MSK; return adf41513_sync_config(st, ADF41513_SYNC_DIFF); } =20 static int adf41513_resume(struct adf41513_state *st) { + int ret; + st->regs[ADF41513_REG6] &=3D ~ADF41513_REG6_POWER_DOWN_MSK; - return adf41513_sync_config(st, ADF41513_SYNC_ALL); + st->regs[ADF41513_REG12] &=3D ~ADF41513_REG12_LE_SELECT_MSK; + ret =3D adf41513_sync_config(st, ADF41513_SYNC_ALL); + if (ret) + return ret; + + if (st->data.le_sync_en) { + st->regs[ADF41513_REG12] |=3D ADF41513_REG12_LE_SELECT_MSK; + ret =3D adf41513_sync_config(st, ADF41513_SYNC_DIFF); + if (ret) + return ret; + } + + return 0; } =20 static ssize_t adf41513_read_resolution(struct iio_dev *indio_dev, @@ -914,6 +930,8 @@ static int adf41513_parse_fw(struct adf41513_state *st) "invalid lock detect count: %u\n", tmp); st->data.lock_detect_count =3D tmp; =20 + /* load enable sync */ + st->data.le_sync_en =3D device_property_read_bool(dev, "adi,le-sync-enabl= e"); st->data.freq_resolution_uhz =3D MICROHZ_PER_HZ; =20 return 0; @@ -970,7 +988,18 @@ static int adf41513_setup(struct device *dev, struct a= df41513_state *st) if (ret) return ret; =20 - return devm_add_action_or_reset(dev, adf41513_close, st); + ret =3D devm_add_action_or_reset(dev, adf41513_close, st); + if (ret) + return ret; + + if (st->data.le_sync_en) { + st->regs[ADF41513_REG12] |=3D ADF41513_REG12_LE_SELECT_MSK; + ret =3D adf41513_sync_config(st, ADF41513_SYNC_DIFF); + if (ret) + return ret; + } + + return 0; } =20 static int adf41513_pm_suspend(struct device *dev) --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41BFE392811; Sun, 24 May 2026 10:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; cv=none; b=kISMmJV5At6KTScJw9GEZDXtDQQANh25h1ca+iU3d0KrjSHNS8w3WQ8AJyVPQ0W2ajmuuwak11N7aay2JcTTNmP5pC0C1j03+wiCpZ7u2hoLLpvtAyskLWz/iHqSn7FemMXcyxmu76ugK3Rxz+jkyktnY1MAojhtkGeD86jfLwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; c=relaxed/simple; bh=lHmXwbdCCTchMGjf+43OCGp7kIZBc5nQLpbg45HcGw4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MrsNFebkNF5aYERvOeq8Dn1AoArIzLTsWxu9sNrmxVWo7IVcnL3Pu0fjUC9JrA6VH0UzrcTjIkH27jHa2MGJ1zotestWqF5Jofdj3FMW7ErzIlSVyLhxF8p1wcx4YZ5iH4MfS5GQYBu01Zovu7+lTG22x324XxTl7gKsnXU9TYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b7GnQiFi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b7GnQiFi" Received: by smtp.kernel.org (Postfix) with ESMTPS id F158AC2BD04; Sun, 24 May 2026 10:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618940; bh=lHmXwbdCCTchMGjf+43OCGp7kIZBc5nQLpbg45HcGw4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=b7GnQiFibDT16XGfkXGqyZ+eLImytdNAD0CJH6gKfQLQMbI/VrotWZ2y3YLXEBoxS WJhbYGoGtKCVSJi64gt4XxVWSRuIMKsTuGmh/G9Ghc5qxGlxKWY3fw0FanULLO0U9j VmMpD/5aZyyNqSnffXMylV/I2KalJ2144qh2l8rM0NiCBWENHXfP1zdaubsb8J7UcF rGjERk2Xi7Zz2WSzqkmk8tmUWplq/jcutwYk3cjj2NMiwPjc86MntUtGfjSyv/oqAB EzZ9/L9vW/vTmsTpqtNr+vHOOodWFiMgsbBN2LWIL2m+KI9vot3lc1w4F5nlVXIyDm HEGUxGOGgLg0A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9EFCCD5BAB; Sun, 24 May 2026 10:35:39 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:27 +0100 Subject: [PATCH v14 10/12] iio: frequency: adf41513: features on frequency change Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-10-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=6090; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=8IfAGT4KE3XVA9QAl7cqwMohYPT/5znW/x2FgZPV7Wg=; b=n5FuG/dl/rW1EtO1YgGZ+GyJ8xFtfh0e5XASdYEJS7v15muSjgWLU695HRpPI6ZU1ZYbFk4ng 4iGtVBs1X4ZD79zA1jLAFZn7TM2kZzEFOS0MtnS1j6pZvPf9ly5XL0T X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Set Bleed current when PFD frequency changes (bleed enabled when in fractional mode). Set lock detector window size, handling bias and precision. Add phase resync support, setting clock dividers when PFD frequency changes. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/adf41513.c | 108 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 108 insertions(+) diff --git a/drivers/iio/frequency/adf41513.c b/drivers/iio/frequency/adf41= 513.c index 43726b2d4879..4f52c6f5df25 100644 --- a/drivers/iio/frequency/adf41513.c +++ b/drivers/iio/frequency/adf41513.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include =20 @@ -152,6 +153,10 @@ #define ADF41513_PRESCALER_8_9 1 #define ADF41513_PRESCALER_AUTO 2 =20 +/* CLK Divider mode */ +#define ADF41513_CLK_DIV_MODE_OFF 0 +#define ADF41513_CLK_DIV_MODE_PHASE_RESYNC 2 + /* Specifications */ #define ADF41510_MAX_RF_FREQ_HZ (10ULL * HZ_PER_GHZ) #define ADF41513_MIN_RF_FREQ_HZ (1ULL * HZ_PER_GHZ) @@ -217,6 +222,7 @@ struct adf41513_chip_info { struct adf41513_data { u64 power_up_frequency_hz; u64 freq_resolution_uhz; + u32 phase_resync_period_ns; u32 charge_pump_voltage_mv; u32 lock_detect_count; =20 @@ -276,6 +282,16 @@ struct adf41513_state { bool powerdown; }; =20 +static const u16 adf41513_ld_window_x10_ns[] =3D { + 9, 12, 16, 17, 21, 28, 29, 35, /* 0 - 7 */ + 43, 47, 49, 52, 70, 79, 115, /* 8 - 14 */ +}; + +static const u8 adf41513_ldp_bias[] =3D { + 0xC, 0xD, 0xE, 0x8, 0x9, 0x4, 0xA, 0x5, /* 0 - 7 */ + 0x0, 0x6, 0xB, 0x1, 0x2, 0x7, 0x3, /* 8 - 14 */ +}; + static const char * const adf41513_power_supplies[] =3D { "avdd1", "avdd2", "avdd3", "avdd4", "avdd5", "vp", }; @@ -579,9 +595,86 @@ static int adf41513_calc_pll_settings(struct adf41513_= state *st, return 0; } =20 +static void adf41513_set_bleed_val(struct adf41513_state *st) +{ + u32 bleed_value, cp_index; + + if (!(st->regs[ADF41513_REG6] & ADF41513_REG6_BLEED_ENABLE_MSK)) + return; + + if (st->data.phase_detector_polarity) + bleed_value =3D 90; + else + bleed_value =3D 144; + + cp_index =3D 1 + FIELD_GET(ADF41513_REG5_CP_CURRENT_MSK, + st->regs[ADF41513_REG5]); + bleed_value =3D div64_u64(st->settings.pfd_frequency_uhz * cp_index * ble= ed_value, + 1600ULL * MEGA * MICROHZ_PER_HZ); + + FIELD_MODIFY(ADF41513_REG6_BLEED_CURRENT_MSK, &st->regs[ADF41513_REG6], + bleed_value); +} + +static void adf41513_set_ld_window(struct adf41513_state *st) +{ + /* + * The ideal lock detector window size is halfway between the max + * window, set by the phase comparison period t_PFD =3D (1 / f_PFD), + * and the minimum is set by (I_BLEED/I_CP) =C3=97 t_PFD + */ + u16 ld_window_10x_ns =3D div64_u64(10ULL * NSEC_PER_SEC * MICROHZ_PER_HZ, + st->settings.pfd_frequency_uhz << 1); + u8 ld_idx, ldp, ld_bias; + + if (st->settings.mode !=3D ADF41513_MODE_INTEGER_N) { + /* account for bleed current (deduced from eq.6 and eq.7) */ + if (st->data.phase_detector_polarity) + ld_window_10x_ns +=3D 4; + else + ld_window_10x_ns +=3D 6; + } + + ld_idx =3D find_closest(ld_window_10x_ns, adf41513_ld_window_x10_ns, + ARRAY_SIZE(adf41513_ld_window_x10_ns)); + ldp =3D (adf41513_ldp_bias[ld_idx] >> 2) & 0x3; + ld_bias =3D adf41513_ldp_bias[ld_idx] & 0x3; + + FIELD_MODIFY(ADF41513_REG6_LDP_MSK, &st->regs[ADF41513_REG6], ldp); + FIELD_MODIFY(ADF41513_REG9_LD_BIAS_MSK, &st->regs[ADF41513_REG9], ld_bias= ); +} + +static void adf41513_set_phase_resync(struct adf41513_state *st) +{ + u32 total_div, clk1_div, clk2_div; + + if (!st->data.phase_resync_period_ns) + return; + + /* assuming both clock dividers hold similar values */ + total_div =3D mul_u64_u64_div_u64(st->settings.pfd_frequency_uhz, + st->data.phase_resync_period_ns, + 1ULL * MICROHZ_PER_HZ * NSEC_PER_SEC); + clk1_div =3D clamp(int_sqrt(total_div), 1, + ADF41513_MAX_CLK_DIVIDER); + clk2_div =3D clamp(DIV_ROUND_CLOSEST(total_div, clk1_div), 1, + ADF41513_MAX_CLK_DIVIDER); + + FIELD_MODIFY(ADF41513_REG5_CLK1_DIV_MSK, &st->regs[ADF41513_REG5], + clk1_div); + FIELD_MODIFY(ADF41513_REG7_CLK2_DIV_MSK, &st->regs[ADF41513_REG7], + clk2_div); + + /* enable phase resync */ + FIELD_MODIFY(ADF41513_REG7_CLK_DIV_MODE_MSK, &st->regs[ADF41513_REG7], + ADF41513_CLK_DIV_MODE_PHASE_RESYNC); +} + static int adf41513_set_frequency(struct adf41513_state *st, u64 freq_uhz,= u16 sync_mask) { struct adf41513_pll_settings result; + bool pfd_change =3D false; + bool mode_change =3D false; int ret; =20 ret =3D adf41513_calc_pll_settings(st, &result, freq_uhz); @@ -589,6 +682,8 @@ static int adf41513_set_frequency(struct adf41513_state= *st, u64 freq_uhz, u16 s return ret; =20 /* apply computed results to pll settings */ + pfd_change =3D st->settings.pfd_frequency_uhz !=3D result.pfd_frequency_u= hz; + mode_change =3D st->settings.mode !=3D result.mode; st->settings =3D result; =20 dev_dbg(&st->spi->dev, @@ -630,6 +725,14 @@ static int adf41513_set_frequency(struct adf41513_stat= e *st, u64 freq_uhz, u16 s st->regs[ADF41513_REG6] |=3D ADF41513_REG6_BLEED_ENABLE_MSK; } =20 + if (pfd_change) { + adf41513_set_bleed_val(st); + adf41513_set_phase_resync(st); + } + + if (pfd_change || mode_change) + adf41513_set_ld_window(st); + return adf41513_sync_config(st, sync_mask | ADF41513_SYNC_REG0); } =20 @@ -920,6 +1023,11 @@ static int adf41513_parse_fw(struct adf41513_state *s= t) st->data.phase_detector_polarity =3D device_property_read_bool(dev, "adi,phase-detector-polarity-positive-ena= ble"); =20 + st->data.phase_resync_period_ns =3D 0; + ret =3D device_property_read_u32(dev, "adi,phase-resync-period-ns", &tmp); + if (!ret) + st->data.phase_resync_period_ns =3D tmp; + st->data.logic_lvl_1v8_en =3D device_property_read_bool(dev, "adi,logic-l= evel-1v8-enable"); =20 tmp =3D ADF41513_LD_COUNT_MIN; --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FB043921EC; Sun, 24 May 2026 10:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; cv=none; b=uk46lFtMdV5N1fKwlXVgnQkIhjoWXMqSAZc0eRuQ8IRkhTsNUqG0HVb0EvidXPsFt5ErXxoxAC/xPq0ymCgXm7x8Qbv8Upz28TJHwyNzH1dP8jy/a6DR3IGXCi+quVhgswzxb0hxNMNxOHn2Abj0vz2xlH7NPU+dPjDxJv+DLE4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; c=relaxed/simple; bh=vCCVBPrrpCyOW1pPOsJh6jvf99OH3fFh5OwBpgLkL+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uIWyB8UMIHV6yLE8GGpukKLBLFD8jGzmV9y9gmZ7LsWZDVvJc+yoH6PaeTSpw8yiQtu2HsftOqrg1R09agkBZdBo1aDaMctW++aMBhLC3xunDxAQRNuBkdmPuRYMKvJi8XTekLfErQUFmO+73VG3Jy5fD6zo20juhpbsuDlzPOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e110cpvR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e110cpvR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0E25FC2BCB8; Sun, 24 May 2026 10:35:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618940; bh=vCCVBPrrpCyOW1pPOsJh6jvf99OH3fFh5OwBpgLkL+k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=e110cpvRHbYMLAp5/LbQq+/2jenHsK0Z/9z/hzZB4qh3ZdWaOGSEutPe5aL3znvsu /wLkFDX2d+NU2P/FzSVuHYIZmsH+jmkX274ELEbCIkoA6JEiCzOFTkkdwZ11cIw6he NiX0+S55nbJMvWecZChvZ0VdaPJfkraCrgsp83STpqZQk5DaR8TkHxvZRSXvDJYG0v /1PNwMyYlwmCZKreNqYHXA8R+KfS0PNNUXhPbb3SNtFFAALIeA3eGNNn2dlsmZo8Xf lY0jYsCYgODp/4annumw5wvXZO2FLQ5YiqKxobzsDSFFNDe1V4dw0ZyaNfAHQYECZI Dh+YzTO1UNBiw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0450ECD5BC7; Sun, 24 May 2026 10:35:40 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:28 +0100 Subject: [PATCH v14 11/12] docs: iio: add documentation for adf41513 driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-11-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=9329; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=AvtUh1Q2wOSppdZq2ewDKuAEItFf+BjGvoFJPXHGb4k=; b=JsufrXplz3vqpCLcyBFO87aGqPpGbzXsPJu5u4RGzSpSKimRDNFuSdEa9nNJQmr0Es5fSa47K ts9cUppoU48A7YbhHiVNpatyiuYLBA3Iqf2Q94bOGKFyopXyZBAPHXJ X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add documentation for ADF41513 driver, which describes the device driver files and shows how userspace may consume the ABI for various tasks. Signed-off-by: Rodrigo Alencar --- Documentation/iio/adf41513.rst | 199 +++++++++++++++++++++++++++++++++++++= ++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 201 insertions(+) diff --git a/Documentation/iio/adf41513.rst b/Documentation/iio/adf41513.rst new file mode 100644 index 000000000000..244453cce6f6 --- /dev/null +++ b/Documentation/iio/adf41513.rst @@ -0,0 +1,199 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +ADF41513 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver supports Analog Devices' ADF41513 and similar SPI PLL frequency +synthesizers. + +1. Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* `ADF41510 `_ +* `ADF41513 `_ + +The ADF41513 is an ultralow noise frequency synthesizer that can be used to +implement local oscillators (LOs) as high as 26.5 GHz in the upconversion = and +downconversion sections of wireless receivers and transmitters. The ADF415= 10 +is a similar device that supports frequencies up to 10 GHz. + +Both devices support integer-N and fractional-N operation modes, providing +excellent phase noise performance and flexible frequency generation +capabilities. + +Key Features: + +- **ADF41510**: 1 GHz to 10 GHz frequency range +- **ADF41513**: 1 GHz to 26.5 GHz frequency range +- Integer-N and fractional-N operation modes +- Ultra-low phase noise (-235 dBc/Hz integer-N, -231 dBc/Hz fractional-N) +- High maximum PFD frequency (250 MHz integer-N, 125 MHz fractional-N) +- 25-bit fixed modulus or 49-bit variable modulus fractional modes +- Programmable charge pump currents with 16x range +- Digital lock detect functionality +- Phase resync capability for consistent output phase + +2. Device attributes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The ADF41513 driver provides the following IIO extended attributes for +frequency control and monitoring: + +Each IIO device has a device folder under ``/sys/bus/iio/devices/iio:devic= eX``, +where X is the IIO index of the device. Under these folders reside a set of +device files that provide access to the synthesizer's functionality. + +The following table shows the ADF41513 related device files: + ++--------------------------------------+----------------------------------= ---------------------+ +| Device file | Description = | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| out_altvoltage0_frequency | RF output frequency control and r= eadback (Hz) | ++--------------------------------------+----------------------------------= ---------------------+ +| out_altvoltage0_frequency_resolution | Target frequency resolution contr= ol (Hz) | ++--------------------------------------+----------------------------------= ---------------------+ +| out_altvoltage0_powerdown | Power management control (0=3Dact= ive, 1=3Dpower down) | ++--------------------------------------+----------------------------------= ---------------------+ +| out_altvoltage0_phase | RF output phase adjustment and re= adback (radians) | ++--------------------------------------+----------------------------------= ---------------------+ + +2.1 Frequency Control +---------------------- + +The ``out_altvoltage0_frequency`` attribute controls the RF output frequen= cy +with sub-Hz precision. The driver automatically selects between integer-N = and +fractional-N modes to achieve the requested frequency with the best possib= le +phase noise performance. + +**Supported ranges:** + +- **ADF41510**: 1,000,000,000 Hz to 10,000,000,000 Hz (1 GHz to 10 GHz) +- **ADF41513**: 1,000,000,000 Hz to 26,500,000,000 Hz (1 GHz to 26.5 GHz) + +The frequency is specified in Hz, for sub-Hz precision use decimal notatio= n. +For example, 12.102 GHz would be written as "12102000000.000000". + +2.2 Frequency Resolution Control +-------------------------------- + +The ``out_altvoltage0_frequency_resolution`` attribute controls the target +frequency resolution that the driver attempts to achieve. This affects the +choice between integer-N and fractional-N modes, including fixed modulus +(25-bit) and variable modulus (49-bit) fractional-N modes: + +- **Integer-N**: Resolution =3D :math:`f_{PFD}` (same as PFD frequency) +- **Fixed modulus**: Resolution =3D :math:`f_{PFD} / 2^{25}` (~3 Hz with 1= 00 MHz PFD) +- **Variable modulus**: Resolution =3D :math:`f_{PFD} / 2^{49}` (=C2=B5Hz = resolution possible) + +Default resolution is 1 Hz (1,000,000 =C2=B5Hz). + +2.3 Phase adjustment +-------------------- + +The ``out_altvoltage0_phase`` attribute allows adjustment of the output ph= ase +in radians. Setting this attribute enables phase adjustment. It can be set +from 0 to :math:`2\pi` radians. Reading this attribute returns the current +phase offset of the output signal. To create a consistent phase relationsh= ip +with the reference signal, the phase resync feature needs to be enabled by +setting a non-zero value to the ``adi,phase-resync-period-ns`` device prop= erty, +which triggers a phase resynchronization after locking is achieved. + +3. Operating modes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +3.1 Integer-N Mode +------------------ + +When the requested frequency can be achieved as an integer multiple of the= PFD +frequency (within the specified resolution tolerance), the driver automati= cally +selects integer-N mode for optimal phase noise performance. + +In integer-N mode: + +- Phase noise: -235 dBc/Hz normalized floor +- Frequency resolution: :math:`f_{PFD}` (same as PFD frequency) +- Maximum PFD frequency: 250 MHz +- Bleed current: Disabled + +3.2 Fractional-N Mode +--------------------- + +When sub-integer frequency steps are required, the driver automatically se= lects +fractional-N mode using either fixed or variable modulus. + +**Fixed Modulus (25-bit)**: + +- Used when variable modulus is not required +- Resolution: :math:`f_{PFD} / 2^{25}` +- Simpler implementation, faster settling + +**Variable Modulus (49-bit)**: + +- Used for maximum resolution requirements +- Resolution: :math:`f_{PFD} / 2^{49}` (theoretical) +- Exact frequency synthesis capability + +In fractional-N mode: + +- Phase noise: -231 dBc/Hz normalized floor +- Maximum PFD frequency: 125 MHz +- Bleed current: Automatically enabled and optimized +- Dithering: Enabled to reduce fractional spurs + +3.3 Automatic Mode Selection +---------------------------- + +The driver automatically selects the optimal operating mode based on: + +1. **Frequency accuracy requirements**: Determined by ``frequency_resoluti= on`` setting +2. **Phase noise optimization**: Integer-N preferred when possible +3. **PFD frequency constraints**: Different limits for integer vs fraction= al modes +4. **Prescaler selection**: Automatic 4/5 vs 8/9 prescaler selection based= on frequency + +4. Usage examples +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +4.1 Basic Frequency Setting +---------------------------- + +Set output frequency to 12.102 GHz: + +.. code-block:: bash + + root:/sys/bus/iio/devices/iio:device0> echo 12102000000 > out_altvolta= ge0_frequency + +Read current frequency: + +.. code-block:: bash + + root:/sys/bus/iio/devices/iio:device0> cat out_altvoltage0_frequency + 12101999999.582767 + +4.2 High Resolution Frequency Control +------------------------------------- + +Configure for sub-Hz resolution and set a precise frequency: + +.. code-block:: bash + + # Set resolution to 0.1 Hz (100,000 =C2=B5Hz) + root:/sys/bus/iio/devices/iio:device0> echo 0.1 > out_altvoltage0_freq= uency_resolution + + # Set frequency to 12.102 GHz (1 =C2=B5Hz precision) + root:/sys/bus/iio/devices/iio:device0> echo 12102000000 > out_altvolta= ge0_frequency + root:/sys/bus/iio/devices/iio:device0> cat out_altvoltage0_frequency + 12101999999.980131 + +4.3 Monitor Lock Status +----------------------- + +When lock detect GPIO is configured, check if PLL is locked: + +.. code-block:: bash + + # Read frequency - will return error if not locked + root:/sys/bus/iio/devices/iio:device0> cat out_altvoltage0_frequency + +If the PLL is not locked, the frequency read will return ``-EBUSY`` (Devic= e or +resource busy). diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index 007e0a1fcc5a..b02b879b053a 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -31,6 +31,7 @@ Industrial I/O Kernel Drivers ad7625 ad7944 ade9000 + adf41513 adis16475 adis16480 adis16550 diff --git a/MAINTAINERS b/MAINTAINERS index 6d695913e717..33168d20ca48 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1668,6 +1668,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml +F: Documentation/iio/adf41513.rst F: drivers/iio/frequency/adf41513.c =20 ANALOG DEVICES INC ADF4377 DRIVER --=20 2.43.0 From nobody Sun May 24 18:44:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 508E7392C34; Sun, 24 May 2026 10:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; cv=none; b=KMZyje6eXGdwS3gV1OBhDpAPhIrW2WBWc0Qi05H3clKhNAOnDn1/DOpM+XsauKxA6GwtrpKDWDKv3fUZhnXgsszfa0DTQvV4o2K4/meka80XRQ3oQnEkk3kXa8H8LHl0uBgUYv0707oa3DLupTEbxucucSJycMhgl9+P6p2b8BY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779618940; c=relaxed/simple; bh=aM5yeD8D0EpZb33GZB7QNZJF6fH7o1iaBw8tXcjXvyI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MxEghq+cOrl34wQ2bQc03qohIjcAjFaLty1o5LmXfg1Sp4JSW2yQkvLGQnHhD1TZ73N6j9Buy/iGUSWsl27/1itnbI2BKavVWfu8WHvqzTq1TAJDFZ0pKuZwyPyaM434gyhLtEXjlctLJuj1PfzTGuY4nIZnxzVNd5mib5M4KJQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I/OO9VH0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I/OO9VH0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1BBF6C2BCC7; Sun, 24 May 2026 10:35:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779618940; bh=aM5yeD8D0EpZb33GZB7QNZJF6fH7o1iaBw8tXcjXvyI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=I/OO9VH01hnG+df/CbCh+eNo5mwiSV8Oczyq5l5I73XljFCIdMm74qQzvm8z/MMkN CE8x4/WncGSfDBjJz4MYeT4lii1f4GALyfyt4cWqcZuvQ/bqdg4MDce5uOAD6Ki4Zp BshnwwUzu6AV3KwiEVLcBZWmWj59sqz0+HwMJTbhSYHqz8Ouu+2dvb2M1SwKEc4HaU JGJArZmKLIBI05ti6hahFjCr9Q7d6M2ITL6gLjhH2XhRpMLfbXoXf5+HWaDEoxqCQh 0V94KLYyUXM8+q13qxAAcyiorVQvuxVgs1To8ZBHUtxyeDmrgysth6Ug2dzisnO4M7 AjBIwOzUfwoyA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14052CD5BB1; Sun, 24 May 2026 10:35:40 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Sun, 24 May 2026 11:35:29 +0100 Subject: [PATCH v14 12/12] Documentation: ABI: testing: add common ABI file for iio/frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260524-adf41513-iio-driver-v14-12-06824d9c15f4@analog.com> References: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> In-Reply-To: <20260524-adf41513-iio-driver-v14-0-06824d9c15f4@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Andrew Morton , Petr Mladek , Steven Rostedt , Andy Shevchenko , Rasmus Villemoes , Sergey Senozhatsky , Shuah Khan , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779618938; l=2211; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=swStfLGThUgetsoO5JlOQerjXKGwa5yLnNDxX9LhxH8=; b=vcNBy1bbe4a9BDWIKJQ0HpKtDNpgXoM6XodHmx5mFs3MzE+jc57d3CUJv+WNKxZDrB5LUvf6B DpPs4zj9mBoC4h2ePxmy15sMDi+vjUbeUyqA2lA4qjX1voW7PMYRDPa X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add ABI documentation file for PLL/DDS devices with frequency_resolution sysfs entry attribute used by both ADF4350 and ADF41513. Signed-off-by: Rodrigo Alencar --- Documentation/ABI/testing/sysfs-bus-iio-frequency | 11 +++++++++++ Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4350 | 10 ---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency b/Documentat= ion/ABI/testing/sysfs-bus-iio-frequency new file mode 100644 index 000000000000..5af31b5b3a19 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency @@ -0,0 +1,11 @@ +What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_resoluti= on +KernelVersion: 3.4.0 +Contact: linux-iio@vger.kernel.org +Description: + Stores channel Y frequency resolution/channel spacing in Hz for PLL + devices. The given value directly influences the operating mode when + fractional-N synthesis is required, as it derives values for + configurable modulus parameters used in the calculation of the output + frequency. It is assumed that the algorithm that is used to compute + the various dividers, is able to generate proper values for multiples + of channel spacing. diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4350 b/Do= cumentation/ABI/testing/sysfs-bus-iio-frequency-adf4350 index 1254457a726e..76987a119feb 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4350 +++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4350 @@ -1,13 +1,3 @@ -What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_resoluti= on -KernelVersion: 3.4.0 -Contact: linux-iio@vger.kernel.org -Description: - Stores channel Y frequency resolution/channel spacing in Hz. - The value given directly influences the MODULUS used by - the fractional-N PLL. It is assumed that the algorithm - that is used to compute the various dividers, is able to - generate proper values for multiples of channel spacing. - What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_refin_frequency KernelVersion: 3.4.0 Contact: linux-iio@vger.kernel.org --=20 2.43.0